)]}'
{
  "commit": "0890a264794f33df540fbaf274699146903b4e6b",
  "tree": "0db148936c0275f7da7e607768e3c1018fb733cc",
  "parents": [
    "05a8256c586ab75bcd6b793737b2022a1a98cb1e",
    "40b8ad8f762cae4c44852ee1736ba766f52d5cc3"
  ],
  "author": {
    "name": "Linus Torvalds",
    "email": "torvalds@linux-foundation.org",
    "time": "Wed Jul 01 09:24:26 2015 -0700"
  },
  "committer": {
    "name": "Linus Torvalds",
    "email": "torvalds@linux-foundation.org",
    "time": "Wed Jul 01 09:24:26 2015 -0700"
  },
  "message": "Merge tag \u0027arc-4.2-rc1\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc\n\nPull ARC architecture updates from Vineet Gupta:\n\n - support for HS38 cores based on ARCv2 ISA\n\n     ARCv2 is the next generation ISA from Synopsys and basis for the\n     HS3{4,6,8} families of processors which retain the traditional ARC mantra of\n     low power and configurability and are now more performant and feature rich.\n\n     HS38x is a 10 stage pipeline core which supports MMU (with huge pages) and\n     SMP (upto 4 cores) among other features.\n\n     + www.synopsys.com/dw/ipdir.php?ds\u003darc-hs38-processor\n     + http://news.synopsys.com/2014-10-14-New-DesignWare-ARC-HS38-Processor-Doubles-Performance-for-Embedded-Linux-Applications\n     + http://www.embedded.com/electronics-news/4435975/Synopsys-ARC-HS38-core-gives-2X-boost-to-Linux-based-apps\n\n - support for ARC SDP (Software Development platform): Main Board + CPU Cards\n    \u003d AXS101: CPU Card with ARC700 in silicon @ 700 MHz\n    \u003d AXS103: CPU Card with HS38x in FPGA\n\n - refactoring of ARCompact port to accomodate new ARCv2 ISA\n\n - misc updates/cleanups\n\n* tag \u0027arc-4.2-rc1\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (72 commits)\n  ARC: Fix build failures for ARCompact in linux-next after ARCv2 support\n  ARCv2: Allow older gcc to cope with new regime of ARCv2/ARCompact support\n  ARCv2: [vdk] dts files and defconfig for HS38 VDK\n  ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x cores\n  ARC: [axs101] Prepare for AXS103\n  ARCv2: [nsim*hs*] Support simulation platforms for HS38x cores\n  ARCv2: All bits in place, allow ARCv2 builds\n  ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)\n  ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock\n  ARC: Reduce bitops lines of code using macros\n  ARCv2: barriers\n  arch: conditionally define smp_{mb,rmb,wmb}\n  ARC: add smp barriers around atomics per Documentation/atomic_ops.txt\n  ARC: add compiler barrier to LLSC based cmpxchg\n  ARCv2: SMP: intc: IDU 2nd level intc for dynamic IRQ distribution\n  ARCv2: SMP: clocksource: Enable Global Real Time counter\n  ARCv2: SMP: ARConnect debug/robustness\n  ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et al\n  ARC: make plat_smp_ops weak to allow over-rides\n  ARCv2: clocksource: Introduce 64bit local RTC counter\n  ...\n",
  "tree_diff": []
}