| commit | b2ab4f08e84d4031f82255447180c559bd076bbf | [log] [tgz] |
|---|---|---|
| author | Steven J. Hill <sjhill@mips.com> | Thu Sep 13 16:47:58 2012 -0500 |
| committer | Steven J. Hill <sjhill@mips.com> | Thu Sep 13 16:55:53 2012 -0500 |
| tree | c43f3abc03b50d68c73c33750528819e349422e6 | |
| parent | fea7a08acb13524b47711625eebea40a0ede69a0 [diff] |
MIPS: Add base architecture support for RI and XI. Originally both Read Inhibit (RI) and Execute Inhibit (XI) were supported by the TLB only for a SmartMIPS core. The MIPSr3(TM) Architecture now defines an optional feature to implement these TLB bits separately. Support for one or both features can be checked by looking at the Config3.RXI bit. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: David Daney <david.daney@cavium.com>