/*
 * Copyright 2018 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include "fsl-imx8mq-som.dtsi"

/ {
	firmware {
		android {
			compatible = "android,firmware";
			fstab {
				compatible = "android,fstab";
				vendor {
					compatible = "android,vendor";
					/* if sd, then dev = "/dev/block/platform/30b50000.usdhc/by-name/vendor"; */
					dev = "/dev/block/platform/30b40000.usdhc/by-name/vendor";
					type = "ext4";
					mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
					fsmgr_flags = "wait,slotselect,avb";
				};
			};
			vbmeta {
				/*we need use FirstStageMountVBootV2 if we enable avb*/
				compatible = "android,vbmeta";
				/*parts means the partition witch can be mount in first stage*/
				parts = "vbmeta,boot,system,vendor";
			};
		};
	};
};


/ {
	model = "Freescale i.MX8MQ Phanbell";
	compatible = "fsl,imx8mq-phanbell", "fsl,imx8mq";

	sound-rt5645 {
		compatible = "google,edgetpu-audio-card";
		model = "edgetpu-audio-card";
		audio-cpu = <&sai2>;
		audio-codec = <&rt5645>;
		google,model = "edgetpu-audio-card";
        status = "okay";
	};

	busfreq {
		status = "disabled";
	};
};

&iomuxc {
	imx8mq-phanbell {
		pinctrl_sai1: sai1grp {
			fsl,pins = <
					MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC     0xd6
					MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK      0xd6
					MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK        0xd6
					MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0    0xd6
					MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0    0xd6
				>;
		};
		pinctrl_sai2: sai2grp {
			fsl,pins = <
					MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
					MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
					MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6
					MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
					MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6
					MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4         0xd6
				>;
		};
	};
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "okay";
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "okay";
};

&ecspi1 {
	fsl,spi-num-chipselects = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
	cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>,
		   <&gpio3 2 GPIO_ACTIVE_HIGH>;
	status = "okay";

	spidev@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "rohm,dh2228fv";
		spi-max-frequency = <20000000>;
		reg = <0>;
		status = "okay";
	};
	spidev@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "rohm,dh2228fv";
		spi-max-frequency = <20000000>;
		reg = <1>;
		status = "okay";
	};

};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio>;

	imx8mq-phanbell {
		pinctrl_gpio: gpio_ctrlgrp{
			fsl,pins = <
				MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
				MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
				MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x19
				MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9		0x19
				MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13		0x19
				MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19
				MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17		0x19
				MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10		0x19
				MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12		0x19
				MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x19
			>;
		};

		pinctrl_pwm1: pwm1 {
			fsl,pins = <
				MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT		0x7f
			>;
		};

		pinctrl_pwm2: pwm2 {
			fsl,pins = <
				MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT		0x7f
			>;
		};

		pinctrl_pwm3: pwm3 {
			fsl,pins = <
				MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT		0x7f
			>;
		};
		pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x82
				MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x82
				MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x82
			>;
		};
		pinctrl_ecspi1_cs: ecspi1_cs_grp {
			fsl,pins = <
				MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x82
				MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x82
			>;
		};
		pinctrl_csi1: csi1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8		0x19 /* PWDN */
				MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x19 /* RESETB */
				/* vsync pin mux? can't find in schematic */
			>;
		};
	};
};

&hdmi {
	status = "okay";
};

&hdmi_cec {
	status = "okay";
};

&dcss {
	disp-dev = "hdmi_disp";
	status = "okay";
};

&sai1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "okay";
};

&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	assigned-clocks =
		<&clk IMX8MQ_CLK_SAI2_SRC>,
		<&clk IMX8MQ_CLK_SAI2_DIV>;
	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <0>, <24576000>;
	status = "okay";

	clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
		<&clk IMX8MQ_CLK_SAI2_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
		<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
		<&clk IMX8MQ_AUDIO_PLL2_OUT>;
	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
};

&i2c2 {
	status = "okay";

	power_monitor_a: power_monitor_a@40 {
		compatible = "ti,ina226";
		reg = <0x40>;
		shunt-resistor = <68000>;
	};
	power_monitor_b: power_monitor_b@41 {
		compatible = "ti,ina226";
		reg = <0x41>;
		shunt-resistor = <68000>;
	};
};

&usb_dwc3_0 {
	extcon = <&typec_ptn5150>;
};

&i2c3 {
	status = "okay";

	rt5645: rt5645@1a {
		compatible = "realtek,rt5645";
		reg = <0x1a>;
		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
		clock-names = "mclk1";
		status = "okay";
		realtek,dmic1-data-pin = <2>; // GPIO5
		realtek,jd-mode = <0>;
		realtek,jd-invert;
		realtek,jd-low-volt-enable;
		interrupt-parent = <&gpio5>;
		interrupts = <4 IRQ_TYPE_EDGE_BOTH>;
		hp-detect-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
	};

	typec_ptn5150: ptn5150@3d {
		compatible = "nxp,ptn5150a";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_typec>;
		reg = <0x3d>;
		interrupt-parent = <&gpio3>;
		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
	};
};

&i2c2 {
	status = "okay";

	ov5645_mipi: ov5645_mipi@3c {
		compatible = "ovti,ov5645_mipi";
		reg = <0x3c>;
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_csi1>;
		clocks = <&clk IMX8MQ_CLK_DUMMY>;
		clock-names = "csi_mclk";
		csi_id = <0>;
		pwn-gpios = <&gpio3 8 1>;
		rst-gpios = <&gpio1 12 0>;
		mclk = <20000000>;
		mclk_source = <0>;
		ae_target = <52>;
		port {
			ov5645_mipi1_ep: endpoint {
				remote-endpoint = <&mipi1_sensor_ep>;
			};
		};
	};
};

&csi1_bridge {
	fsl,mipi-mode;
	fsl,two-8bit-sensor-mode;
	status = "okay";

	port {
		csi1_ep: endpoint {
			remote-endpoint = <&csi1_mipi_ep>;
		};
	};
};

&mipi_csi_1 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	port {
		mipi1_sensor_ep: endpoint1 {
			remote-endpoint = <&ov5645_mipi1_ep>;
			data-lanes = <1 2>;
		};

		csi1_mipi_ep: endpoint2 {
			remote-endpoint = <&csi1_ep>;
		};
	};
};