/*
 * Copyright 2017 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/dts-v1/;

#include "fsl-imx8mq.dtsi"

/ {
	chosen {
		bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
		stdout-path = &uart1;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_usdhc2_vmmc: usdhc2_vmmc {
			compatible = "regulator-fixed";
			regulator-name = "VSD_3V3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_apex: apex_pmic {
			compatible = "regulator-fixed";
			regulator-name = "apex_regulators";
			regulator-min-microvolt = <1000000>;
			regulator-max-microvolt = <1000000>;
			gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
			enable-active-high;
			gpio-open-drain;
			regulator-boot-on;
			regulator-always-on;
			startup-delay-us = <100000>;
		};
	};

	modem_reset: modem-reset {
		compatible = "gpio-reset";
		reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
		reset-delay-us = <2000>;
		reset-post-delay-ms = <40>;
		#reset-cells = <0>;
	};

	bt_rfkill {
		compatible = "fsl,mxc_bt_rfkill";
		bt-power-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
		status ="okay";
	};

};

&clk {
	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
	assigned-clock-rates = <786432000>, <722534400>;
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx8mq-evk {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19
				MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17		0x19
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3
				MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
				MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
				MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
				MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
				MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
				MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
				MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
				MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
				MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
				MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
				MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
				MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
				MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
				MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
				MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
				MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
			>;
		};

		pinctrl_i2c3: i2c3grp {
			fsl,pins = <
				MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
				MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
			>;
		};


		pinctrl_dvfs: dvfsgrp {
			fsl,pins = <
				MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x16
			>;
		};

		pinctrl_typec: typecgrp {
			fsl,pins = <
				MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5		0x16
				MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0		0x19
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
				MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		 0x49
				MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		 0x49
				MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
				MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
				MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6     0x19 /* BT_EN */
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			fsl,pins = <
				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x85
				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			fsl,pins = <
				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x87
				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
			>;
		};

		pinctrl_usdhc2_gpio: usdhc2grpgpio {
			fsl,pins = <
				MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
				MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
			>;
		};

		pinctrl_wdog: wdoggrp {
			fsl,pins = <
				MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
			>;
		};
		pinctrl_pmic: pmicirq {
			fsl,pins = <
				MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41 /*0x17059*/
			>;
		};
	  pinctrl_mipi_dsi_en: mipi_dsi_en {
			fsl,pins = <
				MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6	0x16
			>;
		};
	};

	imx8mq-phanbell {
		pinctrl_pcie0: pcie0grp {
			fsl,pins = <
				MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B        0x76 /* open drain, pull up */
				MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11     0x16 /* Disable - wl_regon */
				MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10     0x16 /* Reset - wl_nreset */
				MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K      0x05
			>;
		};

		pinctrl_pcie1: pcie1grp {
		 fsl,pins = <
			 MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B	0x76 /* open drain, pull up */
			 MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18       0x19 /* APEX_SYS_RST_L */
		 >;
		};
	};
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	disable-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
	reset-gpio = <&gpio3 10 GPIO_ACTIVE_LOW>;
	fsl,max-link-speed = <1>;
	status = "okay";
};

&pcie1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie1>;
	reset-gpio = <&gpio3 18 GPIO_ACTIVE_LOW>;
	ext_osc = <1>;
	hard-wired = <1>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			at803x,led-act-blind-workaround;
			at803x,eee-disabled;
		};
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic: bd71837@4b {
		reg = <0x4b>;
		compatible = "rohm,bd71837";
		/* PMIC BD71837 PMIC_nINT GPIO1_IO12 */
		pinctrl-0 = <&pinctrl_pmic>;
		gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;

		bd71837,pmic-buck1-uses-i2c-dvs;
		bd71837,pmic-buck1-dvs-voltage = <850000>, <850000>, <800000>; /* VDD_SOC: Run-Idle-Suspend */
		bd71837,pmic-buck2-uses-i2c-dvs;
		bd71837,pmic-buck2-dvs-voltage = <1000000>, <850000>, <0>; /* VDD_ARM: Run-Idle */
		bd71837,pmic-buck3-uses-i2c-dvs;
		bd71837,pmic-buck3-dvs-voltage = <850000>, <0>, <0>; /* VDD_GPU: Run */
		bd71837,pmic-buck4-uses-i2c-dvs;
		bd71837,pmic-buck4-dvs-voltage = <850000>, <0>, <0>; /* VDD_VPU: Run */
		bd71837,pmic-buck5-uses-i2c-dvs;
		bd71837,pmic-buck5-dvs-voltage = <900000>, <700000>, <0>; /* VDD_DRAM: Run-Idle */


		gpo {
			rohm,drv = <0x0C>;	/* 0b0000_1100 all gpos with cmos output mode */
		};

		regulators {
			#address-cells = <1>;
			#size-cells = <0>;

			buck1_reg: regulator@0 {
				reg = <0>;
				regulator-compatible = "buck1";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
			};

			buck2_reg: regulator@1 {
				reg = <1>;
				regulator-compatible = "buck2";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck3_reg: regulator@2 {
				reg = <2>;
				regulator-compatible = "buck3";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
			};

			buck4_reg: regulator@3 {
				reg = <3>;
				regulator-compatible = "buck4";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
			};

			buck5_reg: regulator@4 {
				reg = <4>;
				regulator-compatible = "buck5";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6_reg: regulator@5 {
				reg = <5>;
				regulator-compatible = "buck6";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck7_reg: regulator@6 {
				reg = <6>;
				regulator-compatible = "buck7";
				regulator-min-microvolt = <1605000>;
				regulator-max-microvolt = <1995000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck8_reg: regulator@7 {
				reg = <7>;
				regulator-compatible = "buck8";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1_reg: regulator@8 {
				reg = <8>;
				regulator-compatible = "ldo1";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2_reg: regulator@9 {
				reg = <9>;
				regulator-compatible = "ldo2";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3_reg: regulator@10 {
				reg = <10>;
				regulator-compatible = "ldo3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4_reg: regulator@11 {
				reg = <11>;
				regulator-compatible = "ldo4";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo5_reg: regulator@12 {
				reg = <12>;
				regulator-compatible = "ldo5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo6_reg: regulator@13 {
				reg = <13>;
				regulator-compatible = "ldo6";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo7_reg: regulator@14 {
				reg = <14>;
				regulator-compatible = "ldo7";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "disabled";
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

&uart1 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
	status = "okay";
};

&uart2 { /* BT */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	assigned-clocks = <&clk IMX8MQ_CLK_UART2_SRC>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
	fsl,uart-has-rtscts;
	resets = <&modem_reset>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&usb3_phy0 {
	status = "okay";
};

&usb3_0 {
	status = "okay";
};

&usb_dwc3_0 {
	status = "okay";
	dr_mode = "peripheral";
};

&usb3_phy1 {
	status = "okay";
};

&usb3_1 {
	status = "okay";
};

&usb_dwc3_1 {
	status = "okay";
	dr_mode = "host";
};

&gpu_pd {
	power-supply = <&buck3_reg>;
};

&vpu_pd {
	power-supply = <&buck4_reg>;
};

&gpu {
	status = "okay";
};

&vpu {
	regulator-supply = <&buck4_reg>;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&mu {
	status = "okay";
};

&rpmsg{
	/*
	 * 64K for one rpmsg instance:
	 * --0xb8000000~0xb800ffff: pingpong
	 */
	vdev-nums = <1>;
	reg = <0x0 0xb8000000 0x0 0x10000>;
	status = "okay";
};

&A53_0 {
	operating-points = <
		/* kHz    uV */
		1500000 1000000
		1000000 850000
		500000  850000
	>;
	dc-supply = <&buck2_reg>;
};

&hdmi {
	status = "disabled";
};

&hdmi_cec {
	status = "disabled";
};

&dcss {
	status = "disabled";
	disp-dev = "mipi_disp";

	assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI_SRC>,
			  <&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
			  <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>,
			  <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
			  <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
			  <&clk IMX8MQ_VIDEO_PLL1>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
				 <&clk IMX8MQ_SYS1_PLL_800M>,
				 <&clk IMX8MQ_CLK_DISP_RTRM_CG>,
				 <&clk IMX8MQ_VIDEO_PLL1_OUT>,
				 <&clk IMX8MQ_CLK_25M>;
	assigned-clock-rates = <800000000>,
			       <400000000>,
			       <400000000>,
			       <120000000>,
			       <0>,
			       <599999999>;

	dcss_disp0: port@0 {
		reg = <0>;

		dcss_disp0_mipi_dsi: mipi_dsi {
			remote-endpoint = <&mipi_dsi_in>;
		};
	};
};

&mipi_dsi {
	status = "disabled";
	assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
			  <&clk IMX8MQ_CLK_DSI_CORE_SRC>,
			  <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
			  <&clk IMX8MQ_VIDEO_PLL1>;
	assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
				 <&clk IMX8MQ_SYS1_PLL_266M>,
				 <&clk IMX8MQ_CLK_25M>;
	assigned-clock-rates = <24000000>,
			       <266000000>,
			       <0>,
			       <599999999>;

	port@1 {
		mipi_dsi_in: endpoint {
			remote-endpoint = <&dcss_disp0_mipi_dsi>;
		};
	};

};

&mipi_dsi_bridge {
	status = "disabled";

	panel@0 {
		compatible = "raydium,rm67191";
		reg = <0>;
		pinctrl-0 = <&pinctrl_mipi_dsi_en>;
		reset-gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>;
		dsi-lanes = <4>;
		panel-width-mm = <68>;
		panel-height-mm = <121>;
		port {
			panel1_in: endpoint {
				remote-endpoint = <&mipi_dsi_bridge_out>;
			};
		};
	};

	port@1 {
		mipi_dsi_bridge_out: endpoint {
			remote-endpoint = <&panel1_in>;
		};
	};
};