tree 6bed00d13dfefc41b5ad060358426d299f1fc0d8
parent bf911e985d6bbaa328c20c3e05f4eb03de11fdd6
author Daniel Jurgens <danielj@mellanox.com> 1477409784 +0300
committer David S. Miller <davem@davemloft.net> 1477756839 -0400

{net, ib}/mlx5: Make cache line size determination at runtime.

ARM 64B cache line systems have L1_CACHE_BYTES set to 128.
cache_line_size() will return the correct size.

Fixes: cf50b5efa2fe('net/mlx5_core/ib: New device capabilities
handling.')
Signed-off-by: Daniel Jurgens <danielj@mellanox.com>

Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>