diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c
index 54459b5..84b28ef 100644
--- a/drivers/pci/dwc/pci-imx6.c
+++ b/drivers/pci/dwc/pci-imx6.c
@@ -92,6 +92,7 @@
 	u32			dma_unroll_offset;
 	int			link_gen;
 	struct regulator	*vpcie;
+	struct regulator	*vph;
 	struct regmap		*reg_src;
 	struct regmap		*reg_gpc;
 	void __iomem		*phy_base;
@@ -295,6 +296,7 @@
 #define IMX8MQ_GPR_PCIE_REF_USE_PAD		BIT(9)
 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN	BIT(10)
 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE	BIT(11)
+#define IMX8MQ_GPR_PCIE_VREG_BYPASS		BIT(12)
 #define IMX8MQ_ANA_PLLOUT_REG			0x74
 #define IMX8MQ_ANA_PLLOUT_CKE			BIT(4)
 #define IMX8MQ_ANA_PLLOUT_SEL_MASK		0xF
@@ -1192,6 +1194,16 @@
 		else
 			val = IOMUXC_GPR16;
 
+		/*
+		 * Regarding to the datasheet, the PCIE_VPH is suggested
+		 * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the
+		 * VREG_BYPASS should be cleared to zero.
+		 */
+		if ((imx_pcie->variant == IMX8MQ) && imx_pcie->vph &&
+		    regulator_get_voltage(imx_pcie->vph) > 3000000)
+			regmap_update_bits(imx_pcie->iomuxc_gpr, val,
+					   IMX8MQ_GPR_PCIE_VREG_BYPASS,
+					   0);
 		if (imx_pcie->ext_osc) {
 			regmap_update_bits(imx_pcie->iomuxc_gpr, val,
 					IMX8MQ_GPR_PCIE_REF_USE_PAD,
@@ -2561,6 +2573,13 @@
 		imx_pcie->vpcie = NULL;
 	}
 
+	imx_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
+	if (IS_ERR(imx_pcie->vph)) {
+		if (PTR_ERR(imx_pcie->vph) != -ENODEV)
+			return PTR_ERR(imx_pcie->vph);
+		imx_pcie->vph = NULL;
+	}
+
 	platform_set_drvdata(pdev, imx_pcie);
 
 	if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)