MediaTek Frame Engine Ethernet controller
=========================================

The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
have dual GMAC each represented by a child node..

* Ethernet controller node

Required properties:
- compatible: Should be
		"mediatek,mt2701-eth": for MT2701 SoC
		"mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
		"mediatek,mt7622-eth": for MT7622 SoC
- reg: Address and length of the register set for the device
- interrupts: Should contain the three frame engines interrupts in numeric
	order. These are fe_int0, fe_int1 and fe_int2.
- clocks: the clock used by the core
- clock-names: the names of the clock listed in the clocks property. These are
	"ethif", "esw", "gp2", "gp1" : For MT2701 and MT7623 SoC
        "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m",
	"sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC
- power-domains: phandle to the power domain that the ethernet is part of
- resets: Should contain phandles to the ethsys reset signals
- reset-names: Should contain the names of reset signal listed in the resets
		property
		These are "fe", "gmac" and "ppe"
- mediatek,ethsys: phandle to the syscon node that handles the port setup
- mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup
	which is required for those SoCs equipped with SGMII such as MT7622 SoC.
- mediatek,pctl: phandle to the syscon node that handles the ports slew rate
	and driver current

Optional properties:
- interrupt-parent: Should be the phandle for the interrupt controller
  that services interrupts for this device
* Ethernet MAC node

Required properties:
- compatible: Should be "mediatek,eth-mac"
- reg: The number of the MAC
- phy-handle: see ethernet.txt file in the same directory and
	the phy-mode "trgmii" required being provided when reg
	is equal to 0 and the MAC uses fixed-link to connect
	with internal switch such as MT7530.

Example:

eth: ethernet@1b100000 {
	compatible = "mediatek,mt7623-eth";
	reg = <0 0x1b100000 0 0x20000>;
	clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
		 <&ethsys CLK_ETHSYS_ESW>,
		 <&ethsys CLK_ETHSYS_GP2>,
		 <&ethsys CLK_ETHSYS_GP1>;
	clock-names = "ethif", "esw", "gp2", "gp1";
	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
		      GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
		      GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
	resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
	reset-names = "eth";
	mediatek,ethsys = <&ethsys>;
	mediatek,pctl = <&syscfg_pctl_a>;
	#address-cells = <1>;
	#size-cells = <0>;

	gmac1: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-handle = <&phy0>;
	};

	gmac2: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		phy-handle = <&phy1>;
	};

	mdio-bus {
		phy0: ethernet-phy@0 {
			reg = <0>;
			phy-mode = "rgmii";
		};

		phy1: ethernet-phy@1 {
			reg = <1>;
			phy-mode = "rgmii";
		};
	};
};