* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX

Required properties:
- compatible : Should be one of
      "fsl,imx25-sdma"
      "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
      "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
      "fsl,imx51-sdma"
      "fsl,imx53-sdma"
      "fsl,imx6q-sdma"
      "fsl,imx7d-sdma"
      "fsl,imx8mq-sdma"
  The -to variants should be preferred since they allow to determine the
  correct ROM script addresses needed for the driver to work without additional
  firmware.
- reg : Should contain SDMA registers location and length
- interrupts : Should contain SDMA interrupt
- #dma-cells : Must be <3>.
  The first cell specifies the DMA request/event ID.  See details below
  about the second and third cell.
- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
  scripts firmware

The second cell of dma phandle specifies the peripheral type of DMA transfer.
The full ID of peripheral types can be found below.

	ID	transfer type
	---------------------
	0	MCU domain SSI
	1	Shared SSI
	2	MMC
	3	SDHC
	4	MCU domain UART
	5	Shared UART
	6	FIRI
	7	MCU domain CSPI
	8	Shared CSPI
	9	SIM
	10	ATA
	11	CCM
	12	External peripheral
	13	Memory Stick Host Controller
	14	Shared Memory Stick Host Controller
	15	DSP
	16	Memory
	17	FIFO type Memory
	18	SPDIF
	19	IPU Memory
	20	ASRC
	21	ESAI
	22	SSI Dual FIFO	(needs firmware ver >= 2)
	23	Shared ASRC
	24	SAI
	25	HDMI Audio

The third cell specifies the transfer priority and software done
as below.

	Bit31: sw_done
	Bit15~Bit8: selector
	Bit7~Bit0: priority level

	ID	transfer priority
	-------------------------
	0	High
	1	Medium
	2	Low

For example: 0x80000000 means sw_done enabled for done0 sector and
	High priority for PDM on i.mx8mm.

Optional properties:

- gpr : The phandle to the General Purpose Register (GPR) node.
- fsl,sdma-event-remap : Register bits of sdma event remap, the format is
  <reg shift val>.
    reg is the GPR register offset.
    shift is the bit position inside the GPR register.
    val is the value of the bit (0 or 1).
- fsl,ratio-1-1: AHB/SDMA core clock ration 1:1, 2:1 without this.

Examples:

sdma@83fb0000 {
	compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
	reg = <0x83fb0000 0x4000>;
	interrupts = <6>;
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "sdma-imx51.bin";
};

DMA clients connected to the i.MX SDMA controller must use the format
described in the dma.txt file.

Examples:

ssi2: ssi@70014000 {
	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
	reg = <0x70014000 0x4000>;
	interrupts = <30>;
	clocks = <&clks 49>;
	dmas = <&sdma 24 1 0>,
	       <&sdma 25 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
};

Using the fsl,sdma-event-remap property:

If we want to use SDMA on the SAI1 port on a MX6SX:

&sdma {
	gpr = <&gpr>;
	/* SDMA events remap for SAI1_RX and SAI1_TX */
	fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
};

The fsl,sdma-event-remap property in this case has two values:
- <0 15 1> means that the offset is 0, so GPR0 is the register of the
SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.
Setting bit 15 to 1 selects SAI1_RX.
- <0 16 1> means that the offset is 0, so GPR0 is the register of the
SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.
Setting bit 16 to 1 selects SAI1_TX.