/*
 * Copyright 2018-2019 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/dts-v1/;

/memreserve/ 0x84000000 0x2000000;
/memreserve/ 0x86000000 0x400000;
/memreserve/ 0x90000000 0x400000;
/memreserve/ 0x90400000 0x1C00000;
/memreserve/ 0x92000000 0x200000;
/memreserve/ 0x92400000 0x2000000;

#include "fsl-imx8qm-mek.dtsi"
#include "fsl-imx8qm-xen.dtsi"

/ {
	model = "Freescale i.MX8QM MEK DOM0";
	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";

	chosen {
		#address-cells = <2>;
		#size-cells = <2>;

		/* Could be updated by U-Boot */
		module@0 {
			bootargs = "earlycon=xen console=hvc0 loglevel=8 root=/dev/mmcblk1p2 rw  rootwait";
			compatible = "xen,linux-zimage", "xen,multiboot-module";
			reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>;
               };
	};

	domu {
		/*
		 * There are 5 MUs, 0A is used by Dom0, 1A is used
		 * by ATF, so for DomU, 2A/3A/4A could be used.
		 * SC_R_MU_0A
		 * SC_R_MU_1A
		 * SC_R_MU_2A
		 * SC_R_MU_3A
		 * SC_R_MU_4A
		 * The rsrcs and pads will be configured by uboot scu_rm cmd
		 */
		#address-cells = <1>;
		#size-cells = <0>;
		doma {
			compatible = "xen,domu";
			/*
			 * The name entry in VM configuration file
			 * needs to be same as here.
			 */
			domain_name = "DomU";
			/*
			 * The reg property will be updated by U-Boot to
			 * reflect the partition id.
			 */
			reg = <0>;
			init_on_rsrcs = <
				SC_R_MU_2A
			>;
			/* Resources that will be transferred between
			 * M41 and AP, when support android auto.
			 */
			rsrcs-m41-ap = <
				SC_R_CSI_0
				SC_R_CSI_0_PWM_0
				SC_R_CSI_0_I2C_0
				SC_R_LVDS_1
				SC_R_LVDS_1_I2C_0
				SC_R_LVDS_1_PWM_0
				SC_R_DC_1
				SC_R_DC_1_BLIT0
				SC_R_DC_1_BLIT1
				SC_R_DC_1_BLIT2
				SC_R_DC_1_BLIT_OUT
				SC_R_DC_1_WARP
				SC_R_DC_1_VIDEO0
				SC_R_DC_1_VIDEO1
				SC_R_DC_1_FRAC0
				SC_R_DC_1_PLL_0
				SC_R_DC_1_PLL_1
				SC_R_ISI_CH0
			>;
			rsrcs = <
				SC_R_MU_6A
				SC_R_GPU_1_PID0
				SC_R_GPU_1_PID1
				SC_R_GPU_1_PID2
				SC_R_GPU_1_PID3
				SC_R_LVDS_1
				SC_R_LVDS_1_I2C_0
				SC_R_LVDS_1_PWM_0
				SC_R_DC_1
				SC_R_DC_1_BLIT0
				SC_R_DC_1_BLIT1
				SC_R_DC_1_BLIT2
				SC_R_DC_1_BLIT_OUT
				SC_R_DC_1_WARP
				SC_R_DC_1_VIDEO0
				SC_R_DC_1_VIDEO1
				SC_R_DC_1_FRAC0
				SC_R_DC_1_PLL_0
				SC_R_DC_1_PLL_1
				SC_R_MIPI_1
				SC_R_MIPI_1_I2C_0
				SC_R_MIPI_1_I2C_1
				SC_R_MIPI_1_PWM_0
				SC_R_SDHC_0
				SC_R_USB_0
				SC_R_USB_0_PHY
				SC_R_UART_1
				SC_R_DMA_0_CH14
				SC_R_DMA_0_CH15
				SC_R_MU_2A
				/* pcie */
				SC_R_PCIE_B
				SC_R_PCIE_A
				SC_R_SERDES_0
				SC_R_HSIO_GPIO
				/*vpu*/
				SC_R_VPU
				SC_R_VPU_PID0
				SC_R_VPU_PID1
				SC_R_VPU_PID2
				SC_R_VPU_PID3
				SC_R_VPU_PID4
				SC_R_VPU_PID5
				SC_R_VPU_PID6
				SC_R_VPU_PID7
				SC_R_VPU_DEC_0
				SC_R_VPU_ENC_0
				SC_R_VPU_ENC_1
				SC_R_VPU_TS_0
				SC_R_VPU_MU_0
				SC_R_VPU_MU_1
				SC_R_VPU_MU_2
				SC_R_VPU_MU_3
				/* crypto */
				SC_R_CAAM_JR2
				SC_R_CAAM_JR2_OUT
				SC_R_CAAM_JR3
				SC_R_CAAM_JR3_OUT
				/* Camera */
				SC_R_ISI_CH0
				SC_R_ISI_CH1
				SC_R_ISI_CH2
				SC_R_ISI_CH3
				SC_R_MIPI_0
				SC_R_MIPI_0_PWM_0
				SC_R_MIPI_0_I2C_0
				SC_R_MIPI_0_I2C_1
				SC_R_CSI_0
				SC_R_CSI_0_PWM_0
				SC_R_CSI_0_I2C_0
				/* usbotg3 */
				SC_R_USB_2
				SC_R_USB_2_PHY
				/* SAI0 */
				SC_R_DMA_2_CH12
				SC_R_DMA_2_CH13
				SC_R_SAI_0
				/* ESAI0 */
				SC_R_DMA_2_CH6
				SC_R_DMA_2_CH7
				SC_R_ESAI_0
				/* ASRC0 */
				SC_R_DMA_2_CH0
				SC_R_DMA_2_CH1
				SC_R_DMA_2_CH2
				SC_R_DMA_2_CH3
				SC_R_DMA_2_CH4
				SC_R_DMA_2_CH5
				SC_R_ASRC_0
				SC_R_AUDIO_CLK_1
				SC_R_AUDIO_CLK_0
				SC_R_AUDIO_PLL_1
				SC_R_AUDIO_PLL_0

				SC_R_MCLK_OUT_0
				SC_R_MCLK_OUT_1

				/* HIFI DSP */
				SC_R_DSP
				SC_R_DSP_RAM
			>;
			/* Pads that will be transferred between M41 and AP */
			pads-m41-ap = <
				SC_P_MIPI_CSI0_GPIO0_00
				SC_P_MIPI_CSI0_GPIO0_01
				SC_P_LVDS1_I2C1_SCL
				SC_P_LVDS1_I2C1_SDA
			>;
			pads = <
				/* i2c1_lvds1 */
				SC_P_LVDS1_I2C1_SCL
				SC_P_LVDS1_I2C1_SDA
				/* emmc */
				SC_P_EMMC0_CLK
				SC_P_EMMC0_CMD
				SC_P_EMMC0_DATA0
				SC_P_EMMC0_DATA1
				SC_P_EMMC0_DATA2
				SC_P_EMMC0_DATA3
				SC_P_EMMC0_DATA4
				SC_P_EMMC0_DATA5
				SC_P_EMMC0_DATA6
				SC_P_EMMC0_DATA7
				SC_P_EMMC0_STROBE
				SC_P_EMMC0_RESET_B
				/* usb otg */
				SC_P_USB_SS3_TC0
				/* uart1 */
				SC_P_UART1_RX
				SC_P_UART1_TX
				SC_P_UART1_CTS_B
				SC_P_UART1_RTS_B
				SC_P_QSPI1A_DQS
				/* pciea */
				SC_P_PCIE_CTRL0_CLKREQ_B
				SC_P_PCIE_CTRL0_WAKE_B
				SC_P_PCIE_CTRL0_PERST_B
				SC_P_LVDS1_I2C0_SDA
				SC_P_USDHC2_RESET_B
				/*usbotgs typec */
				SC_P_QSPI1A_SS0_B
				SC_P_USB_SS3_TC3
				SC_P_QSPI1A_DATA0
				/* isl29023 */
				SC_P_USDHC2_WP
				SC_P_MIPI_CSI0_GPIO0_00
				SC_P_MIPI_CSI0_GPIO0_01

				/* SAI0 */
				SC_P_SPI0_CS1
				SC_P_SPI2_CS1
				SC_P_SAI1_RXFS
				SC_P_SAI1_RXC

				/* ESAI0 */
				SC_P_ESAI0_FSR
				SC_P_ESAI0_FST
				SC_P_ESAI0_SCKR
				SC_P_ESAI0_SCKT
				SC_P_ESAI0_TX0
				SC_P_ESAI0_TX1
				SC_P_ESAI0_TX2_RX3
				SC_P_ESAI0_TX3_RX2
				SC_P_ESAI0_TX4_RX1
				SC_P_ESAI0_TX5_RX0

				/* lvds pwm */
				SC_P_LVDS1_GPIO00
				>;

			gpios = <&gpio1 13 GPIO_ACTIVE_LOW>,
				<&gpio1 27 GPIO_ACTIVE_LOW>,
				<&gpio1 28 GPIO_ACTIVE_LOW>,
				<&gpio4 6 GPIO_ACTIVE_LOW>,
				<&gpio4 9 GPIO_ACTIVE_LOW>,
				<&gpio4 11 GPIO_ACTIVE_HIGH>,
				<&gpio4 19 GPIO_ACTIVE_HIGH>,
				<&gpio4 22 GPIO_ACTIVE_LOW>,
				<&gpio4 26 GPIO_ACTIVE_HIGH>,
				<&gpio4 25 GPIO_ACTIVE_HIGH>,
				<&gpio4 27 GPIO_ACTIVE_LOW>,
				<&gpio4 29 GPIO_ACTIVE_LOW>;
		};
	};

	reserved-memory {
		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0 0x28000000>;
			alloc-ranges = <0 0xa0000000 0 0x40000000>;
			linux,cma-default;
		};
	};

	display-subsystem {
		compatible = "fsl,imx-display-subsystem";
		ports = <&dpu1_disp0>, <&dpu1_disp1>;
	};

	/* Passthrough to domu */
	mu2: mu@5d1d0000 {
		compatible = "fsl,imx8-mu";
		reg = <0x0 0x5d1d0000 0x0 0x10000>;
		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
		fsl,scu_ap_mu_id = <0>;
		xen,passthrough;
		status = "disabled";
	};

	irqsteer_cm41: irqsteer_cm41@0x51080000 {
		reg = <0x0 0x51080000 0x0 0x10000>;
		xen,passthrough;
	};

	mu_rpmsg1_b: mu_rpmsg1_b@0x5d2a0000 {
		reg = <0x0 0x5d2a0000 0x0 0x10000>;
		xen,passthrough;
	};

	dsp_mu_b: dsp_mu_b@0x5d310000 {
		reg = <0x0 0x5d310000 0x0 0x10000>;
		xen,passthrough;
	};

	decoder_boot_mem: decoder_boot_mem@0x84000000 {
		xen,passthrough;
		reg = <0 0x84000000 0 0x2000000>;
	};

	encoder_boot_mem: encoder_boot_mem@0x86000000 {
		xen,passthrough;
		reg = <0 0x86000000 0 0x400000>;
	};

	rpmsg_reserved_mem: rpmsg_reserved_mem@90000000 {
		xen,passthrough;
		reg = <0x0 0x90000000 0x0 0x400000>;
	};

	rpmsg_dma_mem: rpmsg_dma_mem@90400000 {
		xen,passthrough;
		reg = <0x0 0x90400000 0x0 0x1c00000>;
	};

	decoder_rpc_mem: decoder_rpc_mem@0x92000000 {
		xen,passthrough;
		reg = <0 0x92000000 0 0x200000>;
	};

	encoder_rpc_mem: encoder_rpc_mem@0x92200000 {
		xen,passthrough;
		reg = <0 0x92200000 0 0x200000>;
	};

	dsp_reserved_mem: dsp@0x92400000 {
		xen,passthrough;
		reg = <0 0x92400000 0 0x2000000>;
	};
	encoder_reserved_mem: encoder_reserved_mem@0x94400000 {
		xen,passthrough;
		reg = <0 0x94400000 0 0x800000>;
	};

	/* This piece memory is used by M41, M40 is not covered */
	m41_mem: m41_mem@0x94400000 {
		xen,passthrough;
		reg = <0 0x88800000 0 0x7800000>;
	};

	gpio4_dummy: gpio4_dummy@0{
		/* Passthrough gpio4 interrupt to DomU */
		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
		xen,passthrough;
	};

	/* Interrupt 33 is not used, use it virtual PL031 */
	rtc0: rtc@23000000 {
		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		xen,passthrough;
	};
};

&mu_rpmsg1 {
	xen,passthrough;
};

&rpmsg1 {
	/* Let xen not create mapping form dom0 */
	/delete-property/ reg;
	status = "disabled";
};

&rpmsg {
	/delete-property/ reg;
	status = "disabled";
};

&mu_6_lpcg {
	xen,passthrough;
};

&mu_6_lpcg_b {
	xen,passthrough;
};

&mu_7_lpcg_b {
	xen,passthrough;
};

&usbotg1_lpcg {
	xen,passthrough;
};

&sdhc1_lpcg {
	xen,passthrough;
};

&lpuart1 {
	xen,passthrough;
};

&lpuart1_lpcg {
	xen,passthrough;
};

/*
 * DomU CM41 use this, but DomU OS not need this,
 * because smmu is enabled for CM41, so need to
 *create the lpuart2 mapping in SMMU
 */
&lpuart2 {
	xen,passthrough;
};

&lpuart2_lpcg {
	xen,passthrough;
};

&di_lvds1_lpcg {
	xen,passthrough;
};

&dc_1_lpcg {
	xen,passthrough;
};

&edma01 {
	#stream-id-cells = <1>;
	xen,passthrough;
};

&edma20 {
	#stream-id-cells = <1>;
	xen,passthrough;
	/* Put edma20 and edma21 resource here */
	fsl,sc_rsrc_id = <SC_R_DMA_2_CH0>,
			 <SC_R_DMA_2_CH1>,
			 <SC_R_DMA_2_CH2>,
			 <SC_R_DMA_2_CH3>,
			 <SC_R_DMA_2_CH4>,
			 <SC_R_DMA_2_CH5>,
			 <SC_R_DMA_2_CH6>,
			 <SC_R_DMA_2_CH7>,
			 <SC_R_DMA_2_CH12>,
			 <SC_R_DMA_2_CH13>;
};

&edma21 {
	xen,passthrough;
};

&edma24 {
	xen,passthrough;
};

/*
 * SMMU, for simplity, we put all all the resources needs to programmed
 * for VPU under vpu_decoder node, then in cfg file only add vpu_decoder
 * in dt_dev is enough.
 */
&smmu {
	mmu-masters = <&dpu2 0x13>, <&gpu_3d1 0x15>, <&edma20 0x14>,
		      <&usdhc1 0x12>, <&usbotg1 0x11>,
		      <&edma01 0x10>, <&pciea 0x08>,
		      <&vpu_decoder 0x7>, <&crypto 0x6>, <&isi_0 0x5>,
		      <&usbotg3 0x4>, <&dsp 0x3>;
};

&lvds_region2 {
	xen,passthrough;
};

&irqsteer_lvds1 {
	xen,passthrough;
};

&i2c1_lvds1 {
	xen,passthrough;
};

&ldb2_phy {
	xen,passthrough;
};

&ldb2 {
	xen,passthrough;
};

&dpu2_intsteer {
	xen,passthrough;
};

&dpu2 {
	xen,passthrough;
	#stream-id-cells = <1>;
	iommus = <&smmu>;
};

&pixel_combiner2 {
	xen,passthrough;
};

&prg10 {
	xen,passthrough;
};

&prg11 {
	xen,passthrough;
};

&prg12 {
	xen,passthrough;
};

&prg13 {
	xen,passthrough;
};

&prg14 {
	xen,passthrough;
};

&prg15 {
	xen,passthrough;
};

&prg16 {
	xen,passthrough;
};

&prg17 {
	xen,passthrough;
};

&prg18 {
	xen,passthrough;
};

&dpr3_channel1 {
	xen,passthrough;
};

&dpr3_channel2 {
	xen,passthrough;
};

&dpr3_channel3 {
	xen,passthrough;
};

&dpr4_channel1 {
	xen,passthrough;
};

&dpr4_channel2 {
	xen,passthrough;
};

&dpr4_channel3 {
	xen,passthrough;
};

/* GPU */
&pd_gpu1 {
	xen,passthrough;
};

&gpu_3d1 {
	xen,passthrough;
	#stream-id-cells = <1>;
	iommus = <&smmu>;
};

&imx8_gpu_ss {
	cores = <&gpu_3d0>;
	reg = <0x0 0xa0000000 0x0 0x40000000>, <0x0 0x0 0x0 0x10000000>;
	reg-names = "phys_baseaddr", "contiguous_mem";
};

&sata {
	status = "disabled";
};

&usdhc1 {
	xen,passthrough;
	#stream-id-cells = <1>;
	iommus = <&smmu>;
};

&usbotg1 {
	/* Hack reg */
	reg = <0x0 0x5b0d0000 0x0 0x1000>;
	xen,passthrough;
	#stream-id-cells = <1>;
	iommus = <&smmu>;
};

&usbmisc1 {
	/* Hack */
	/delete-property/ reg;
	status = "disabled";
};

&usbphy1 {
	reg = <0x0 0x5b100000 0x0 0x1000>;
	xen,passthrough;
};

&hsio {
	xen,passthrough;
};

&hsio_pcie_x2_lpcg {
	xen,passthrough;
};

&hsio_phy_x2_lpcg {
	xen,passthrough;
};

&hsio_pcie_x2_crr2_lpcg {
	xen,passthrough;
};

&hsio_pcie_x1_lpcg {
	xen,passthrough;
};

&pciea {
       #stream-id-cells = <1>;
       iommus = <&smmu>;
       xen,passthrough;
       fsl,sc_rsrc_id = <SC_R_PCIE_A>;
};

&pcieb {
       xen,passthrough;
};

&gpio1 {
	xen,shared;
};

&gpt0 {
	/delete-property/ interrupts;
	status = "disabled";
};

&gpio4 {
	/*
	 * Use GPT0 interrupt for hack
	 * This could be removed when interrupt sharing be supported.
	 */
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	xen,domu-irq;
	xen,shared;
};

&dsp {
       xen,passthrough;
       #stream-id-cells = <1>;
       iommus = <&smmu>;
};

&mu13 {
	xen,passthrough;
};

&mu_m0 {
	xen,passthrough;
};

&mu1_m0 {
	xen,passthrough;
};

&mu2_m0 {
	xen,passthrough;
};

&vpu_decoder {
       #stream-id-cells = <1>;
       iommus = <&smmu>;
       xen,passthrough;
       fsl,sc_rsrc_id = <SC_R_VPU_PID0>,
			<SC_R_VPU_PID1>,
			<SC_R_VPU_PID2>,
			<SC_R_VPU_PID3>,
			<SC_R_VPU_PID4>,
			<SC_R_VPU_PID5>,
			<SC_R_VPU_PID6>,
			<SC_R_VPU_PID7>,
			<SC_R_VPU_DEC_0>,
			<SC_R_VPU_ENC_0>,
			<SC_R_VPU_ENC_1>,
			<SC_R_VPU_TS_0>;
};

&vpu_decoder_csr {
	xen,passthrough;
};

&vpu_encoder {
       iommus = <&smmu>;
       #stream-id-cells = <1>;
       xen,passthrough;
};

&{/vpu_encoder@2d000000/core0@1020000} {
	xen,passthrough;
};

&{/vpu_encoder@2d000000/core1@1040000} {
	xen,passthrough;
};

&crypto {
	xen,passthrough;
	iommus = <&smmu>;
	#stream-id-cells = <1>;
	/* JR1 is not used by Linux */
	fsl,sc_rsrc_id = <SC_R_CAAM_JR2>, <SC_R_CAAM_JR2_OUT>,
			 <SC_R_CAAM_JR3>, <SC_R_CAAM_JR3_OUT>;
};

&sec_jr2 {
	xen,passthrough;
};

&sec_jr3 {
	xen,passthrough;
};

&caam_sm {
	xen,passthrough;
};

&i2c0 {
	isl29023@44 {
		xen,passthrough;
	};

	fxos8700@1e {
		xen,passthrough;
	};

	fxas2100x@20 {
		xen,passthrough;
	};

	mpl3115@60 {
		xen,passthrough;
	};

	typec_ptn5110: typec@50 {
		xen,passthrough;
	};
};

/* Camera */
&img_pdma_0_lpcg {
	xen,passthrough;
};

&img_pdma_1_lpcg {
	xen,passthrough;
};

&img_pdma_2_lpcg {
	xen,passthrough;
};

&img_pdma_3_lpcg {
	xen,passthrough;
};

&mipi_csi_0_lpcg {
	xen,passthrough;
};

&img_pxl_link_csi0_lpcg {
	xen,passthrough;
};

&gpio0_mipi_csi0 {
	xen,passthrough;
};

&irqsteer_csi0 {
	xen,passthrough;
};

&isi_0 {
	xen,passthrough;
	#stream-id-cells = <1>;
	iommus = <&smmu>;
	fsl,sc_rsrc_id = <SC_R_ISI_CH0>,
			 <SC_R_ISI_CH1>,
			 <SC_R_ISI_CH2>,
			 <SC_R_ISI_CH3>;
};

&isi_1 {
	xen,passthrough;
};

&isi_2 {
	xen,passthrough;
};

&isi_3 {
	xen,passthrough;
};

&mipi_csi_0 {
	xen,passthrough;
};

&i2c0_mipi_csi0 {
	xen,passthrough;
};

&isi_4 {
	status = "okay";
};

&isi_5 {
	status = "okay";
};

&isi_6 {
	status = "okay";
};

&isi_7 {
	status = "okay";
};

&mipi_csi_1 {
	status = "okay";
};

&i2c0_mipi_csi1 {
	status = "okay";
};

&usbotg3_lpcg {
	xen,passthrough;
};

&usbotg3 {
	xen,passthrough;
	#stream-id-cells = <1>;
	iommus = <&smmu>;
};

/delete-node/ &{/sound-cs42888};

&acm {
	xen,passthrough;
};

&sai0 {
	xen,passthrough;
};

&aud_sai_0_lpcg {
	xen,passthrough;
};

&esai0 {
	xen,passthrough;
};

&asrc0 {
	xen,passthrough;
};

&aud_asrc_0_lpcg {
	xen,passthrough;
};

&aud_esai_0_lpcg {
	xen,passthrough;
};

&aud_pll_clk0_lpcg {
	xen,passthrough;
};

&aud_pll_clk1_lpcg {
	xen,passthrough;
};

&aud_mclkout0_lpcg {
	xen,passthrough;
};

&aud_mclkout1_lpcg {
	xen,passthrough;
};

&aud_rec_clk0_lpcg {
	xen,passthrough;
};

&aud_rec_clk1_lpcg {
	xen,passthrough;
};

&lvds1_pwm {
	xen,passthrough;
};