commit 517df5f5134af207c90ac92185dc8c7ed5a86f92
author Hawking Zhang <Hawking.Zhang@amd.com> Sat May 27 13:40:45 2017 +0800
committer Alex Deucher <alexander.deucher@amd.com> Fri Aug 04 08:24:51 2017 -0400
tree 979724fc6710c71c5776bcee6a2b740d6e282b97
parent 0167e6836e91947418fec36c3b4b396760d0f345

tests/amdgpu: bypass UVD CS tests on raven

raven doesn't support UVD decode

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

tests/amdgpu/cs_tests.c

diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
index 081ec9c..df55c70 100644
--- a/tests/amdgpu/cs_tests.c
+++ b/tests/amdgpu/cs_tests.c
@@ -90,6 +90,11 @@
 	chip_rev = device_handle->info.chip_rev;
 	chip_id = device_handle->info.chip_external_rev;
 
+	if (family_id >= AMDGPU_FAMILY_RV) {
+		printf("\n\nThe ASIC NOT support UVD, all sub-tests will pass\n");
+		return CUE_SUCCESS;
+	}
+
 	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
 	if (r)
 		return CUE_SINIT_FAILED;
@@ -114,6 +119,9 @@
 {
 	int r;
 
+	if (family_id >= AMDGPU_FAMILY_RV)
+		return CUE_SUCCESS;
+
 	r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
 				     ib_mc_address, IB_SIZE);
 	if (r)
@@ -192,6 +200,9 @@
 	void *msg;
 	int i, r;
 
+	if (family_id >= AMDGPU_FAMILY_RV)
+		return;
+
 	req.alloc_size = 4*1024;
 	req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 
@@ -263,6 +274,9 @@
 	uint8_t *ptr;
 	int i, r;
 
+	if (family_id >= AMDGPU_FAMILY_RV)
+                return;
+
 	req.alloc_size = 4*1024; /* msg */
 	req.alloc_size += 4*1024; /* fb */
 	if (family_id >= AMDGPU_FAMILY_VI)
@@ -402,6 +416,9 @@
 	void *msg;
 	int i, r;
 
+	if (family_id >= AMDGPU_FAMILY_RV)
+                return;
+
 	req.alloc_size = 4*1024;
 	req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;