#define __ASSEMBLY__

#include <ddrc_mem_map.h>
#include <ddr_phy_mem_map.h>

/*
 * Device Configuration Data (DCD)
 *
 * Each entry must have the format:
 * Addr-type           Address        Value
 *
 * where:
 * Addr-type register length (1,2 or 4 bytes)
 * Address   absolute address of the register
 * value   value to be stored in the register
 */

#ifndef SCFW_DCD
/* For 1200MHz DDR, DRC 600MHz operation */
DATA 4	0xff148000	0x00000CC8	/* DRC0 bringup */
DATA 4	0xff1a0000	0x00000CC8	/* DRC1 bringup */
#else
/* Set the DRC rate to 600MHz, the PHY PLL will double this for the DRAM rate. */
uint32_t rate2 = SC_600MHZ;
pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2);
pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &rate2);
#endif

DATA 4	0x41a40208	0x1
DATA 4	0x41d00208	0x1
DATA 4	0x41a40040	0xb
DATA 4	0x41d00040	0xb
DATA 4	0x41a40204	0x1
DATA 4	0x41d00204	0x1
/* DRAM 0 controller configuration begin */
DATA 4 	DDRC_MSTR_0   	0xC3080020	// Set LPDDR4, BL = 16 and active ranks
DATA 4 	DDRC_DERATEEN_0   	0x00000213	// derate enable, derate values, byte to read MRR data
DATA 4 	DDRC_DERATEINT_0   	0x0124F800	// derate MR4 interval read
DATA 4  DDRC_RFSHCTL0_0	0x0021f070 	// REFRESH_BURST = 7
DATA 4 	DDRC_RFSHTMG_0	0x004900A8	// tREFI, tRFC
DATA 4 	DDRC_INIT0_0  	0x40030495	// pre_cke = 2ms, post_cke = 2us
DATA 4 	DDRC_INIT1_0  	0x00770000	// dram_rstn = 200us
DATA 4 	DDRC_INIT3_0  	0x00440024	// MR1, MR2
DATA 4 	DDRC_INIT4_0  	0x00F10000	// MR3, MR13
DATA 4	DDRC_RANKCTL_0  	0x0000066F	// diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
DATA 4	DDRC_DRAMTMG0_0 	0x1618141A	// wr2pr, tFAW, tRASmax, tRASmin
DATA 4	DDRC_DRAMTMG1_0 	0x00050526	// tXP, rd2pre, tRC
DATA 4	DDRC_DRAMTMG2_0 	0x060E1714	// WL, RL, rd2wr, wr2rd
DATA 4	DDRC_DRAMTMG3_0 	0x00909000	// tmrw, tmrd, tmod
DATA 4	DDRC_DRAMTMG4_0 	0x0B04060B	// trcd, tccd, trrd, trp
DATA 4	DDRC_DRAMTMG5_0 	0x02030909	// tCKCKEH, tCKCKEL, tckesr, tcke
DATA 4	DDRC_DRAMTMG6_0 	0x02020006	// tckdpde, tckdpdx, tckcsx
DATA 4	DDRC_DRAMTMG7_0 	0x00000301	// tckpde, tckpdx
DATA 4	DDRC_DRAMTMG12_0	0x00020510	// tCMDCKE, tCKEHCMD
DATA 4	DDRC_DRAMTMG13_0	0x0B100002	// tODTLoff, tCCDMW, tPPD
DATA 4	DDRC_DRAMTMG14_0	0x000000AD	// txsr
DATA 4	DDRC_ZQCTL0_0   	0x02580012	// tZQCAL, tZQLAT
DATA 4	DDRC_ZQCTL1_0   	0x01E0493E	// tZQReset, tzq_short_interval
DATA 4	DDRC_DFITMG0_0  	0x0499820A	// dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat
DATA 4	DDRC_DFITMG1_0  	0x00070303	// dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
DATA 4	DDRC_DFITMG2_0  	0x00001708	// dfi_tphy_rdcslat, dfi_tphy_wrcslat
DATA 4	DDRC_DFIMISC_0  	0x00000005	// dfi_data_cs_polarity
DATA 4	DDRC_DFIUPD0_0  	0x00400003	// Disable the automatic dfi_ctrlupd_req generation
DATA 4	DDRC_DFIUPD1_0  	0x008000A0	// dfi_ctrlupd_req generation interval generation (min and max)
DATA 4	DDRC_DFIUPD2_0  	0x80000000	// dfi_phyupd_en
DATA 4	DDRC_ADDRMAP0_0 	0x00000015	// addrmap_cs_bit0
DATA 4	DDRC_ADDRMAP3_0 	0x00000000	// addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6
DATA 4	DDRC_ADDRMAP4_0 	0x00001F1F	// addrmap_col_b10 and addrmap_col_b11 set to de-activated
DATA 4	DDRC_ADDRMAP1_0 	0x00080808	// addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
DATA 4	DDRC_ADDRMAP5_0 	0x07070707	// addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
DATA 4	DDRC_ADDRMAP6_0 	0x48080707	// addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12
DATA 4	DDRC_DBICTL_0   	0x00000007	// rd_dbi_en=wr_dbi_en=dm_en=1
DATA 4	DDRC_ODTMAP_0   	0x00002211	// rank[3:0]_wr_odt, rank[3:0]_wr_odt
DATA 4	DDRC_PCTRL_0_0  	0x00000001	// Enable port 0
DATA 4	DDRC_DFITMG0_SHADOW_0	0x00808000
/* DRAM 1 controller initialization */
DATA 4	DDRC_MSTR_1     	0xC3080020	// Set LPDDR4, BL = 16 and active ranks
DATA 4 	DDRC_DERATEEN_1 	0x00000213	// derate enable, derate values, byte to read MRR data
DATA 4 	DDRC_DERATEINT_1	0x0124F800	// derate MR4 interval read
DATA 4  DDRC_RFSHCTL0_1 	0x0021f070 	// REFRESH_BURST = 7
DATA 4	DDRC_RFSHTMG_1  	0x004900A8	// tREFI, tRFC
DATA 4	DDRC_INIT0_1    	0x40030495	// pre_cke = 2ms, post_cke = 2us
DATA 4	DDRC_INIT1_1    	0x00770000	// dram_rstn = 200us
DATA 4	DDRC_INIT3_1    	0x00440024	// MR1, MR2
DATA 4	DDRC_INIT4_1    	0x00F10000	// MR3, MR13
DATA 4	DDRC_RANKCTL_1  	0x0000066F	// diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
DATA 4	DDRC_DRAMTMG0_1 	0x1618141A	// wr2pr, tFAW, tRASmax, tRASmin
DATA 4	DDRC_DRAMTMG1_1 	0x00050526	// tXP, rd2pre, tRC
DATA 4	DDRC_DRAMTMG2_1 	0x060E1714	// WL, RL, rd2wr, wr2rd
DATA 4	DDRC_DRAMTMG3_1 	0x00909000	// tmrw, tmrd, tmod
DATA 4	DDRC_DRAMTMG4_1 	0x0B04060B	// trcd, tccd, trrd, trp
DATA 4	DDRC_DRAMTMG5_1 	0x02030909	// tCKCKEH, tCKCKEL, tckesr, tcke
DATA 4	DDRC_DRAMTMG6_1 	0x02020006	// tckdpde, tckdpdx, tckcsx
DATA 4	DDRC_DRAMTMG7_1 	0x00000301	// tckpde, tckpdx
DATA 4	DDRC_DRAMTMG12_1	0x00020510	// tCMDCKE, tCKEHCMD
DATA 4	DDRC_DRAMTMG13_1	0x0B100002	// tODTLoff, tCCDMW, tPPD
DATA 4	DDRC_DRAMTMG14_1	0x000000AD	// txsr
DATA 4	DDRC_ZQCTL0_1   	0x02580012	// tZQCAL, tZQLAT
DATA 4	DDRC_ZQCTL1_1   	0x01E0493E	// tZQReset, tzq_short_interval
DATA 4	DDRC_DFITMG0_1  	0x0499820A	// dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat
DATA 4	DDRC_DFITMG1_1  	0x00070303	// dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
DATA 4	DDRC_DFITMG2_1  	0x00001708	// dfi_tphy_rdcslat, dfi_tphy_wrcslat
DATA 4	DDRC_DFIMISC_1  	0x00000005	// dfi_data_cs_polarity
DATA 4	DDRC_DFIUPD0_1  	0x00400003	// Disable the automatic dfi_ctrlupd_req generation
DATA 4	DDRC_DFIUPD1_1  	0x008000A0	// dfi_ctrlupd_req generation interval generation (min and max)
DATA 4	DDRC_DFIUPD2_1  	0x80000000	// dfi_phyupd_en
DATA 4	DDRC_ADDRMAP0_1 	0x00000015	// addrmap_cs_bit0
DATA 4	DDRC_ADDRMAP3_1 	0x00000000	// addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6
DATA 4	DDRC_ADDRMAP4_1 	0x00001F1F	// addrmap_col_b10 and addrmap_col_b11 set to de-activated
DATA 4	DDRC_ADDRMAP1_1 	0x00080808	// addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
DATA 4	DDRC_ADDRMAP5_1 	0x07070707	// addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
DATA 4	DDRC_ADDRMAP6_1 	0x48080707	// addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12
DATA 4	DDRC_DBICTL_1   	0x00000007	// rd_dbi_en=wr_dbi_en=dm_en=1
DATA 4	DDRC_ODTMAP_1   	0x00002211	// rank[3:0]_wr_odt, rank[3:0]_wr_odt
DATA 4	DDRC_PCTRL_0_1  	0x00000001	// Enable port 0
DATA 4	DDRC_DFITMG0_SHADOW_1	0x00808000

DATA 4 	DDRC_PWRCTL_0 		0x10A		// selfref_en clear when enabling HW Idle
DATA 4 	DDRC_PWRCTL_1 		0x10A		// selfref_en clear when enabling HW Idle
DATA 4 	DDRC_PWRTMG_0 		0x00402010
DATA 4 	DDRC_PWRTMG_1 		0x00402010
DATA 4  DDRC_HWLPCTL_0		0x003F0001
DATA 4  DDRC_HWLPCTL_1		0x003F0001
DATA 4	DDRC_DFILPCFG0_0	0x0700C100
DATA 4	DDRC_DFILPCFG0_1	0x0700C100

DATA 4	0x41a40208	0x1
DATA 4	0x41d00208	0x1
DATA 4 	0x41a40040	0xf
DATA 4 	0x41d00040	0xf
DATA 4 	0x41a40204	0x1
DATA 4 	0x41d00204	0x1
//-------------------------------------------
// Configure registers for PHY initialization
//--------------------------------------------
// Set-up DRAM Configuration Register
DATA 4	DDR_PHY_DCR_0	0x0000040D	// LPDDR4 selection with 8 bank
// Set-up byte and bit swapping registers
DATA 4	DDR_PHY_PGCR8_0    	0x000F0009
DATA 4	DDR_PHY_DX0DQMAP0_0	0x00003465	// DQ bit 0/1/2/3/4 remapping
DATA 4	DDR_PHY_DX0DQMAP1_0	0x00008271	// DQ bit 5/6/7 and DM remapping
DATA 4	DDR_PHY_DX1DQMAP0_0	0x00075632	// DQ bit 0/1/2/3/4 remapping
DATA 4	DDR_PHY_DX1DQMAP1_0	0x00008104	// DQ bit 5/6/7 and DM remapping
DATA 4	DDR_PHY_DX2DQMAP0_0	0x00064732	// DQ bit 0/1/2/3/4 remapping
DATA 4	DDR_PHY_DX2DQMAP1_0	0x00008015	// DQ bit 5/6/7 and DM remapping
DATA 4	DDR_PHY_DX3DQMAP0_0	0x00012574	// DQ bit 0/1/2/3/4 remapping
DATA 4	DDR_PHY_DX3DQMAP1_0	0x00008360	// DQ bit 5/6/7 and DM remapping
DATA 4	DDR_PHY_CATR0_0    	0x00141032	// Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
DATA 4	DDR_PHY_CATR1_0    	0x0013AAAA	// Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
// Set-up PHY General Configuration Register
SET_BIT 4 	DDR_PHY_PGCR1_0	0x000A0000	// DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1
DATA 4	DDR_PHY_PGCR0_0	0x87001E00	// Set ADCP=1 (Address Copy)
DATA 4	DDR_PHY_PGCR2_0	0x00F0A193	// Set tREFPRD
DATA 4	DDR_PHY_PGCR3_0	0x050A1080	// CKEN/CKNEN toggling and polarity
// Set-up PHY Timing Register
// PTR2 is untouched
DATA 4	DDR_PHY_PTR0_0	0x4B025810	// tPLLPD, tPLLGS, tPHYRST
DATA 4	DDR_PHY_PTR1_0	0x3A981518	// tPLLLOCK, tPLLRST
// Set-up PLL Control Register
DATA 4	DDR_PHY_PLLCR0_0      	0x001C0000
DATA 4	DDR_PHY_DX8SLbPLLCR0_0	0x001C0000
// Set-up Impedance Control Register
DATA 4	DDR_PHY_ZQCR_0	0x008A2C58	// Set ODT_MODE=0b10(LPDDR4 stype pullup)
// ZPROG_DRAM_ODT and ZPROG_HOST_ODT
DATA 4 	DDR_PHY_ZQ0PR0_0	0x0001B9BB	// Impedance control for CA bus
DATA 4 	DDR_PHY_ZQ1PR0_0	0x0001B9BB	// Impedance control for DQ bus
// Set-up PHY Initialization Register
DATA 4 	DDR_PHY_PIR_0	0x32
// Launch initialization (set bit 0)
DATA 4	DDR_PHY_PIR_0	0x33
//-------------------------------------------
// Configure registers for PHY initialization
//-------------------------------=------------
// Set-up DRAM 1 PHY Configuration Register
DATA 4	DDR_PHY_DCR_1	0x0000040D	// LPDDR4 selection with 8 bank
// Set-up byte and bit swapping registers
DATA 4	DDR_PHY_PGCR8_1	0x000F0009
DATA 4	DDR_PHY_DX0DQMAP0_1	0x00003465	// DQ bit 0/1/2/3/4 remapping
DATA 4	DDR_PHY_DX0DQMAP1_1	0x00008271	// DQ bit 5/6/7 and DM remapping
DATA 4	DDR_PHY_DX1DQMAP0_1	0x00075632	// DQ bit 0/1/2/3/4 remapping
DATA 4	DDR_PHY_DX1DQMAP1_1	0x00008104	// DQ bit 5/6/7 and DM remapping
DATA 4	DDR_PHY_DX2DQMAP0_1	0x00064732	// DQ bit 0/1/2/3/4 remapping
DATA 4	DDR_PHY_DX2DQMAP1_1	0x00008015	// DQ bit 5/6/7 and DM remapping
DATA 4	DDR_PHY_DX3DQMAP0_1	0x00012574	// DQ bit 0/1/2/3/4 remapping
DATA 4	DDR_PHY_DX3DQMAP1_1	0x00008360	// DQ bit 5/6/7 and DM remapping
DATA 4	DDR_PHY_CATR0_1	0x00141032	// Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
DATA 4	DDR_PHY_CATR1_1	0x0013AAAA	// Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
// Set-up PHY General Configuration Register
SET_BIT 4	DDR_PHY_PGCR1_1	0x000A0000	// DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1
DATA 4	DDR_PHY_PGCR0_1	0x87001E00	// Set ADCP=1 (Address Copy)
DATA 4	DDR_PHY_PGCR2_1	0x00F0A193	// Set tREFPRD
DATA 4	DDR_PHY_PGCR3_1	0x050A1080	// CKEN/CKNEN toggling and polarity
// Set-up PHY Timing Register
// PTR2 is untouched
DATA 4	DDR_PHY_PTR0_1	0x4B025810	// tPLLPD, tPLLGS, tPHYRST
DATA 4	DDR_PHY_PTR1_1	0x3A981518	// tPLLLOCK, tPLLRST
// Set-up PLL Control Register
DATA 4	DDR_PHY_PLLCR0_1	0x001C0000
DATA 4	DDR_PHY_DX8SLbPLLCR0_1	0x001C0000
// Set-up Impedance Control Register
DATA 4	DDR_PHY_ZQCR_1	0x008A2C58	// Set ODT_MODE=0b10(LPDDR4 stype pullup)
// ZPROG_DRAM_ODT and ZPROG_HOST_ODT
DATA 4	DDR_PHY_ZQ0PR0_1	0x0001B9BB	// Impedance control for CA bus
DATA 4	DDR_PHY_ZQ1PR0_1	0x0001B9BB	// Impedance control for DQ bus
// Set-up PHY Initialization Register
DATA 4	DDR_PHY_PIR_1	0x32
// Launch initialization (set bit 0)
DATA 4	DDR_PHY_PIR_1	0x33
//-------------------------------------------
// Configure registers for DRAM initialization
//-------------------------------------------
// Set-up Mode Register
// MR0, MR3, MR4, MR5 MR6 are untouched
DATA 4	DDR_PHY_MR1_0	0x44	// Set BL, WR-PRE, nWR, RPST
DATA 4	DDR_PHY_MR2_0	0x24	// Set RL/WL
DATA 4	DDR_PHY_MR3_0	0xF1	// Set drive strength

DATA 4	DDR_PHY_MR11_0	0x54	// Set CA ODT and DQ ODT
DATA 4	DDR_PHY_MR22_0	0x15	// Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks)
/* LPDDR4 mode register writes for CA and DQ VREF settings */
DATA 4	DDR_PHY_MR12_0	0x48
DATA 4	DDR_PHY_MR14_0	0x48
// Set-up DRAM Timing Parameters Register
// DTPR6 is untouched
DATA 4	DDR_PHY_DTPR0_0	0x0C331A09	// tRRD, tRAS, tRP, tRTP
DATA 4	DDR_PHY_DTPR1_0	0x28300411	// tWLMRD, tFAW, tODTUP, tMRD
DATA 4	DDR_PHY_DTPR2_0	0x0069615A	// tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
DATA 4	DDR_PHY_DTPR3_0	0x01800501	// tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
DATA 4	DDR_PHY_DTPR4_0	0x01502B0C	// tRFC, tWLO, tXP
DATA 4	DDR_PHY_DTPR5_0	0x194C160D	// tRC, tRCD, tWTR
// Set-up PHY Timing Register
DATA 4	DDR_PHY_PTR3_0	0x00249F00	// tDINIT0
DATA 4	DDR_PHY_PTR4_0	0x00000960	// tDINIT1
DATA 4	DDR_PHY_PTR5_0	0x0003A980	// tDINIT2
DATA 4	DDR_PHY_PTR6_0	0x027004B0	// tDINIT4, tDINIT3
// Set-up ODT Configuration Register
// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
DATA 4	DDR_PHY_RANKIDR_0	0x00000001	// Select rank 1 to write
DATA 4	DDR_PHY_ODTCR_0	0x00000000	// ODT of rank1 disabled
DATA 4	DDR_PHY_RANKIDR_0	0x00000000	// Select rank 0 to write
DATA 4	DDR_PHY_ODTCR_0	0x00000000	// ODT of rank0 disabled
// Set-up AC I/O Configuration Register
// ACIOCR1-4 are untouched
DATA 4	DDR_PHY_ACIOCR0_0	0x30070800	// PNUM2 (i.e.LPDDR4) selection  [10:11] = 0x2
DATA 4	DDR_PHY_ACIOCR5_0	0x09000000	// I/O mode = LPDDR4
// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON.
DATA 4	DDR_PHY_ACIOCR1_0	0x44000000
// Set-up VREF Training Control Registers
DATA 4	DDR_PHY_VTCR0_0	0xF0032008	// CK1, CK0, DRAM VREF set to same as MR12
DATA 4	DDR_PHY_VTCR1_0	0x07F0018F	// HVIO=1, SHREN=1, SHRNK=0
// Set-up DATX8 General Configuration Registers
// DXnGCR0-4 are untouched
SET_BIT 4	DDR_PHY_PGCR5_0	0x4
DATA 4	DDR_PHY_PGCR6_0	0x00033200	// Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit
// Set-up DATX8 General Configuration Registers
DATA 4	DDR_PHY_DX0GCR5_0	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4	DDR_PHY_DX1GCR5_0	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4	DDR_PHY_DX2GCR5_0	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4	DDR_PHY_DX3GCR5_0	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4	DDR_PHY_DX0GCR4_0	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4	DDR_PHY_DX1GCR4_0	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4	DDR_PHY_DX2GCR4_0	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4	DDR_PHY_DX3GCR4_0	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
// Set-up DATX8 DX Control Register 2
// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA
DATA 4	DDR_PHY_DX8SLbDXCTL2_0	0x001C1600
DATA 4	DDR_PHY_PGCR4_0		0x001900B1
// Set-up DATX8 IO Control Register
DATA 4	DDR_PHY_DX8SLbIOCR_0	0x79000000	// I/O mode = LPDDR4
//-------------------------------------------
// Configure registers for DRAM initialization
//-------------------------------------------
// Set-up Mode Register
// MR0, MR3, MR4, MR5 MR6 are untouched
DATA 4	DDR_PHY_MR1_1	0x44	// Set BL, WR-PRE, nWR, RPST
DATA 4	DDR_PHY_MR2_1	0x24	// Set RL/WL
DATA 4	DDR_PHY_MR3_1	0xF1	// Set drive strength

DATA 4	DDR_PHY_MR11_1	0x54	// Set CA ODT and DQ ODT
DATA 4	DDR_PHY_MR22_1	0x15	// Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks)
/* LPDDR4 mode register writes for CA and DQ VREF settings */
DATA 4	DDR_PHY_MR12_1	0x48
DATA 4	DDR_PHY_MR14_1	0x48
// Set-up DRAM Timing Parameters Register			
// DTPR6 is untouched			
DATA 4	DDR_PHY_DTPR0_1	0x0C331A09	// tRRD, tRAS, tRP, tRTP
DATA 4	DDR_PHY_DTPR1_1	0x28300411	// tWLMRD, tFAW, tODTUP, tMRD
DATA 4	DDR_PHY_DTPR2_1	0x0069615A	// tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
DATA 4	DDR_PHY_DTPR3_1	0x01800501	// tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
DATA 4	DDR_PHY_DTPR4_1	0x01502B0C	// tRFC, tWLO, tXP
DATA 4	DDR_PHY_DTPR5_1	0x194C160D	// tRC, tRCD, tWTR
// Set-up PHY Timing Register			
DATA 4	DDR_PHY_PTR3_1	0x00249F00	// tDINIT0
DATA 4	DDR_PHY_PTR4_1	0x00000960	// tDINIT1
DATA 4	DDR_PHY_PTR5_1	0x0003A980	// tDINIT2
DATA 4	DDR_PHY_PTR6_1	0x027004B0	// tDINIT4, tDINIT3 (1us)
// Set-up ODT Configuration Register			
// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.			
DATA 4	DDR_PHY_RANKIDR_1	0x00000001	// Select rank 1 to write
DATA 4	DDR_PHY_ODTCR_1	0x00000000	// ODT of rank1 disabled
DATA 4	DDR_PHY_RANKIDR_1	0x00000000	// Select rank 0 to write
DATA 4	DDR_PHY_ODTCR_1	0x00000000	// ODT of rank0 disabled
// Set-up AC I/O Configuration Register			
// ACIOCR1-4 are untouched			
DATA 4	DDR_PHY_ACIOCR0_1	0x30070800	// PNUM2 (i.e.LPDDR4) selection  [10:11] = 0x2
DATA 4	DDR_PHY_ACIOCR5_1	0x09000000	// I/O mode = LPDDR4
// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON.			
DATA 4	DDR_PHY_ACIOCR1_1	0x44000000	
// Set-up VREF Training Control Registers			
DATA 4	DDR_PHY_VTCR0_1	0xF0032008	// CK1, CK0, DRAM VREF set to same as MR12
DATA 4	DDR_PHY_VTCR1_1	0x07F0018F	// HVIO=1, SHREN=1, SHRNK=0
// Set-up DATX8 General Configuration Registers			
// DXnGCR0-4 are untouched			
SET_BIT 4	DDR_PHY_PGCR5_1	0x4	
DATA 4	DDR_PHY_PGCR6_1	0x00033200	// Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit
// Set-up DATX8 General Configuration Registers			
DATA 4	DDR_PHY_DX0GCR5_1	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4	DDR_PHY_DX1GCR5_1	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4	DDR_PHY_DX2GCR5_1	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4	DDR_PHY_DX3GCR5_1	0x09092020	// Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4	DDR_PHY_DX0GCR4_1	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4	DDR_PHY_DX1GCR4_1	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4	DDR_PHY_DX2GCR4_1	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4	DDR_PHY_DX3GCR4_1	0x0E00BF3C	// Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
// Set-up DATX8 DX Control Register 2
// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA			
DATA 4	DDR_PHY_DX8SLbDXCTL2_1	0x001C1600
DATA 4	DDR_PHY_PGCR4_1		0x001900B1
// Set-up DATX8 IO Control Register
DATA 4	DDR_PHY_DX8SLbIOCR_1	0x79000000	// I/O mode = LPDDR4

#if DDR_TRAIN_IN_DCD
// Wait PHY initialization end then launch DRAM initialization
// Wait for bit 0 of PGSR0 to be '1'
CHECK_BITS_SET 4 	DDR_PHY_PGSR0_0	0x1
// Wait for bit 0 of PGSR0 to be '1'
CHECK_BITS_SET 4 	DDR_PHY_PGSR0_1	0x1

// Launch DRAM 0 initialization (set bit 0)
DATA 4 	DDR_PHY_PIR_0	0x180
DATA 4 	DDR_PHY_PIR_0	0x181
// Launch DRAM 1 initialization (set bit 0)
DATA 4 	DDR_PHY_PIR_1	0x180
DATA 4 	DDR_PHY_PIR_1	0x181

// DRAM 0 initialization end
CHECK_BITS_SET 4 	DDR_PHY_PGSR0_0	0x1
// DRAM 1 initialization end
CHECK_BITS_SET 4 	DDR_PHY_PGSR0_1	0x1

// Launch a second time DRAM initialization due to following Synopsys PHY bug:
// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration"
// Workaround: "Run DRAM Initialization twice"
DATA 4 	DDR_PHY_PIR_0	0x100
DATA 4 	DDR_PHY_PIR_0	0x101
DATA 4 	DDR_PHY_PIR_1	0x100
DATA 4 	DDR_PHY_PIR_1	0x101

// Wait (second time) DRAM 0 initialization end
CHECK_BITS_SET 4	DDR_PHY_PGSR0_0	0x1
// Wait (second time) DRAM 1 initialization end
CHECK_BITS_SET 4	DDR_PHY_PGSR0_1	0x1

//---------------------------------------------------------------//
// DATA training
//---------------------------------------------------------------//
// configure PHY for data training
// The following register writes are recommended by SNPS prior to running training
CLR_BIT 4 	DDR_PHY_DQSDR0_0	0x00000001	// Disable drift
SET_BIT 4 	DDR_PHY_PGCR6_0	0x00000001	// Disable VT compensation
CHECK_BITS_SET 4 	DDR_PHY_PGSR1_0	0x40000000	// Disable VT compensation
SET_BIT 4 	DDR_PHY_PGCR1_0	0x00020040	// DISDIC=1; PUBMODE=1
// Per SNPS initialize BIST registers for VREF training
DATA 4 	DDR_PHY_BISTAR1_0	0x00010100	//BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16)
DATA 4 	DDR_PHY_BISTAR2_0	0x700003FF	// BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC)
DATA 4 	DDR_PHY_BISTAR4_0	0x00003FFF	// BMROW=0x4000 (limit to min rows in JEDEC)

CLR_BIT 4 	DDR_PHY_DQSDR0_1	0x00000001	// Disable drift
SET_BIT 4 	DDR_PHY_PGCR6_1	0x00000001	// Disable VT compensation
CHECK_BITS_SET 4 	DDR_PHY_PGSR1_1	0x40000000	// Disable VT compensation
SET_BIT 4 	DDR_PHY_PGCR1_1	0x00020040	// DISDIC=1; PUBMODE=1
// Per SNPS initialize BIST registers for VREF training
DATA 4 	DDR_PHY_BISTAR1_1	0x00010100	//BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16)
DATA 4 	DDR_PHY_BISTAR2_1	0x700003FF	// BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC)
DATA 4 	DDR_PHY_BISTAR4_1	0x00003FFF	// BMROW=0x4000 (limit to min rows in JEDEC)

// Set-up Data Training Configuration Register			
// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys			
// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training).			
// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED).			
DATA 4 	DDR_PHY_DTCR0_0	0x000071C7	// Set DTRPTN to 0x7. RFSHDT=0
DATA 4 	DDR_PHY_DTCR1_0	0x00030236	// Set RANKEN
DATA 4 	DDR_PHY_DTCR0_1	0x000071C7	// Set DTRPTN to 0x7. RFSHDT=0
DATA 4 	DDR_PHY_DTCR1_1	0x00030236	// Set RANKEN

// Launch Write leveling			
DATA 4 	DDR_PHY_PIR_0	0x200	
DATA 4 	DDR_PHY_PIR_0	0x201	
DATA 4 	DDR_PHY_PIR_1	0x200	
DATA 4 	DDR_PHY_PIR_1	0x201	
// Wait Write leveling to complete			
CHECK_BITS_SET 4	DDR_PHY_PGSR0_0	0x1
CHECK_BITS_SET 4	DDR_PHY_PGSR0_1	0x1

// Set DQS/DQSn glitch suppression resistor for training PHY0			
DATA 4 	DDR_PHY_DX8SLbDQSCTL_0	0x012240F7
// Launch Read DQS training			
DATA 4 	DDR_PHY_PIR_0	0x400	
DATA 4 	DDR_PHY_PIR_0	0x401	
// Set DQS/DQSn glitch suppression resistor for training PHY1			
DATA 4 	DDR_PHY_DX8SLbDQSCTL_1	0x012240F7
// Launch Read DQS training			
DATA 4 	DDR_PHY_PIR_1	0x400	
DATA 4 	DDR_PHY_PIR_1	0x401	
// Wait Read DQS training to complete PHY0			
CHECK_BITS_SET 4 	DDR_PHY_PGSR0_0	0x1
CHECK_BITS_CLR 4 	DDR_PHY_PGSR0_0	0x00400000	
// Remove DQS/DQSn glitch suppression resistor PHY0			
DATA 4 	DDR_PHY_DX8SLbDQSCTL_0	0x01224000
// Wait Read DQS training to complete PHY1			
CHECK_BITS_SET 4	DDR_PHY_PGSR0_1	0x1
CHECK_BITS_CLR 4	DDR_PHY_PGSR0_1	0x00400000	
// Remove DQS/DQSn glitch suppression resistor PHY1			
DATA 4 	DDR_PHY_DX8SLbDQSCTL_1	0x01224000

// DQS2DQ training, Write leveling, Deskew and eye trainings			
DATA 4	DDR_PHY_PIR_0	0x0010F800	
DATA 4	DDR_PHY_PIR_0	0x0010F801	
DATA 4	DDR_PHY_PIR_1	0x0010F800	
DATA 4	DDR_PHY_PIR_1	0x0010F801	
// Wait for training to complete			
CHECK_BITS_SET 4	DDR_PHY_PGSR0_0 	0x1
CHECK_BITS_SET 4	DDR_PHY_PGSR0_1 	0x1

// Launch VREF training			
DATA 4	DDR_PHY_PIR_0	0x00020000	
DATA 4	DDR_PHY_PIR_0	0x00020001	
DATA 4	DDR_PHY_PIR_1	0x00020000	
DATA 4	DDR_PHY_PIR_1	0x00020001	
// Wait for training to complete			
CHECK_BITS_SET 4	DDR_PHY_PGSR0_0	0x1
CHECK_BITS_SET 4	DDR_PHY_PGSR0_1	0x1

//Re-allow uMCTL2 to send commands to DDR			
CLR_BIT 4	DDR_PHY_PGCR1_0	0x00020040	// DISDIC=0, PUBMODE=0
CLR_BIT 4	DDR_PHY_PGCR1_1	0x00020040	// DISDIC=0, PUBMODE=0

//DQS Drift Registers PHY0			
CLR_BIT 4	DDR_PHY_DX0GCR3_0	0x08000000	
CLR_BIT 4	DDR_PHY_DX1GCR3_0	0x08000000	
CLR_BIT 4	DDR_PHY_DX2GCR3_0	0x08000000	
CLR_BIT 4	DDR_PHY_DX3GCR3_0	0x08000000	
// Enable DQS drift detection PHY0			
DATA 4 	DDR_PHY_DQSDR0_0	0x20188005
DATA 4 	DDR_PHY_DQSDR1_0	0xA8AA0000	
DATA 4 	DDR_PHY_DQSDR2_0	0x00070200	
//DQS Drift Registers PHY1			
CLR_BIT 4	DDR_PHY_DX0GCR3_1	0x08000000	
CLR_BIT 4	DDR_PHY_DX1GCR3_1	0x08000000	
CLR_BIT 4	DDR_PHY_DX2GCR3_1	0x08000000	
CLR_BIT 4	DDR_PHY_DX3GCR3_1	0x08000000	
// Enable DQS drift detection PHY1			
DATA 4 	DDR_PHY_DQSDR0_1	0x20188005
DATA 4 	DDR_PHY_DQSDR1_1	0xA8AA0000	
DATA 4 	DDR_PHY_DQSDR2_1	0x00070200	

//Enable QCHAN HWidle
DATA 4	0x41A40504	0x400
DATA 4	0x41D00504	0x400

// Enable VT compensation			
CLR_BIT 4	DDR_PHY_PGCR6_0	0x1 	
CLR_BIT 4	DDR_PHY_PGCR6_1	0x1 	

//Check that controller is ready to operate			
CHECK_BITS_SET 4	DDRC_STAT_0	0x1
CHECK_BITS_SET 4	DDRC_STAT_1	0x1

#endif