#define __ASSEMBLY__

#include <ddrc_mem_map.h>
#include <ddr_phy_mem_map.h>

/*
 * Device Configuration Data (DCD)
 *
 * Each entry must have the format:
 * Addr-type           Address        Value
 *
 * where:
 *	Addr-type register length (1,2 or 4 bytes)
 *	Address	  absolute address of the register
 *	value	  value to be stored in the register
 */

#ifndef SCFW_DCD
/* For 1200MHz DDR, DRC 600MHz operation */
DATA 4 0xff190000 0x00000CC8    /* DRC0 bringup */
#else
/* Set the DRC rate to 1.2GHz. */
uint32_t rate2 = SC_600MHZ;
pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2);
#endif

DATA 4 0x41C80208 0x1

DATA 4 0x41C80040 0xb

DATA 4 0x41C80204 0x1

/* DRAM 0 controller configuration begin */
DATA 4 DDRC_MSTR_0 0xC3081020   // Set LPDDR4, BL = 16 and active ranks
DATA 4 DDRC_RFSHTMG_0 0x004800A9   // tREFI, tRFC
DATA 4 DDRC_INIT0_0 0x4003049A   // pre_cke = 2ms is too long - LPDDR4 model hacked for 20us
DATA 4 DDRC_INIT1_0 0x007A0000   // dram_rstn - LPDDR4 model hacked for 20us;
DATA 4 DDRC_INIT3_0 0x00440024   // MR1=0x54: nWR=30 BL=16;  MR2=0x2d: RL=28 WL=14
//DATA 4 DDRC_INIT4_0 0x00310000   // MR3, MR13
DATA 4 DDRC_INIT4_0 0x00F10000   // MR3=0xF1: DBI-WR=DBI-RD=1, PU-CAL=VDDQ/3 PDDS=RZQ/6, MR13
//DATA 4 DDRC_RANKCTL_0 0x0000075f   // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd
DATA 4 DDRC_RANKCTL_0 0x0000066f   // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd, waiting for SNPS feedback
DATA 4 DDRC_DRAMTMG0_0 0x1619141a   // wr2pr, tFAW, tRASmax, tRASmin
DATA 4 DDRC_DRAMTMG1_0 0x00050527   // tXP, rd2pre, tRC
//DATA 4 DDRC_DRAMTMG2_0 0x060c1011   // WL, RL, rd2wr, wr2rd
DATA 4 DDRC_DRAMTMG2_0 0x060E1111   // WL, RL (DBI enabled, 28), rd2wr, wr2rd
DATA 4 DDRC_DRAMTMG3_0 0x0090900a   // tmrw, tmrd, tmod
DATA 4 DDRC_DRAMTMG4_0 0x0c04070c   // trcd, tccd, trrd, trp
DATA 4 DDRC_DRAMTMG5_0 0x02040a05   // tCKCKEH, tCKCKEL, tckesr, tcke
DATA 4 DDRC_DRAMTMG6_0 0x02020006   // tckdpde, tckdpdx, tckcsx
DATA 4 DDRC_DRAMTMG7_0 0x00000401   // tckpde, tckpdx
DATA 4 DDRC_DRAMTMG12_0 0x00020510   // tCMDCKE, tCKEHCMD (=tXP?)
DATA 4 DDRC_DRAMTMG13_0 0x0b100002   // tODTLoff, tCCDMW, tPPD
DATA 4 DDRC_DRAMTMG14_0 0x000000ae   // txsr
DATA 4 DDRC_ZQCTL0_0 0x025b0013   // tZQCAL, tZQLAT

DATA 4 DDRC_ZQCTL1_0 0x01f00100   // tZQReset, tzq_short_interval

//DATA 4 DDRC_DFITMG0_0 0x0495820a   // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat
DATA 4 DDRC_DFITMG0_0 0x0499820a   // dfi_t_ctrl_delay, dfi_t_rddata_en RL=28 with DBI enabled, dfi_tphy_wrdata, dfi_tphy_wrlat
DATA 4 DDRC_DFITMG1_0 0x00070303   // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable
//DATA 4 DDRC_DFITMG2_0 0x00001308   // dfi_tphy_rdcslat, dfi_tphy_wrcslat
DATA 4 DDRC_DFITMG2_0 0x00001708   // dfi_tphy_rdcslat RL=28 with DBI enabled, dfi_tphy_wrcslat
DATA 4 DDRC_DFIMISC_0 0x00000005   // dfi_data_cs_polarity
DATA 4 DDRC_DFIUPD0_0 0x00400003   // Disable the automatic dfi_ctrlupd_req generation
DATA 4 DDRC_DFIUPD1_0 0x008000A0   // dfi_ctrlupd_req generation interval generation (min and max)
DATA 4 DDRC_DFIUPD2_0 0x80000000   // dfi_phyupd_en

DATA 4 DDRC_ADDRMAP0_0 0x00000014   // addrmap_cs_bit0
DATA 4 DDRC_ADDRMAP4_0 0x00001F1F   // addrmap_col_b10 and addrmap_col_b11 set to de-activated

DATA 4 DDRC_ADDRMAP1_0 0x00070707   // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0
DATA 4 DDRC_ADDRMAP5_0 0x06060606   // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0
DATA 4 DDRC_ADDRMAP6_0 0x07070606   // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12

DATA 4 DDRC_DBICTL_0 0x00000007     // rd_dbi_en=wr_dbi_en=dm_en=1

DATA 4 DDRC_ODTMAP_0 0x00002211   // rank[3:0]_wr_odt, rank[3:0]_wr_odt
DATA 4 DDRC_PCTRL_0_0 0x00000001   // Enable port 0

DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000

DATA 4 DDRC_PWRCTL_0 0x10D

DATA 4 0x41C80208 0x1

DATA 4 0x41C80040 0xf

DATA 4 0x41C80204 0x1

  //-------------------------------------------
  // Configure registers for PHY initialization
  // Timings are computed for a PHY at 800MHz (DRAM at 1600MHz)
  //-------------------------------=------------

  // Set-up DRAM Configuration Register
DATA 4 DDR_PHY_DCR_0 0x0000040D   // LPDDR4 selection with 8 bank

  // Set-up byte and bit swapping registers
DATA 4 DDR_PHY_PGCR8_0 0x000F000A   // Set BSWAPMSB='b1001 (byte 0 and 1 are swapped)
DATA 4 DDR_PHY_DX0DQMAP0_0 0x00061032   // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004578   // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_DX1DQMAP0_0 0x00071032   // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004685   // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_DX2DQMAP0_0 0x00016578   // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004203   // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_DX3DQMAP0_0 0x00015867   // DQ bit 0/1/2/3/4 remapping
DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004320   // DQ bit 5/6/7 and DM remapping
DATA 4 DDR_PHY_CATR0_0 0x00141032   // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY
DATA 4 DDR_PHY_CATR1_0 0x0013AAAA   // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY

  // Set-up PHY General Configuration Register
  // PGCR1,4,5,6,7 are untouched
SET_BIT 4 DDR_PHY_PGCR1_0 0x00020000   // DISDIC=1 (no uMCTL2 commands can go to memory)
DATA 4 DDR_PHY_PGCR0_0 0x07001E00   // Set ADCP=1 (Address Copy)
CLR_BIT 4 DDR_PHY_DX2GCR1_0 0x000000FF
CLR_BIT 4 DDR_PHY_DX3GCR1_0 0x000000FF
DATA 4 DDR_PHY_PGCR2_0 0x00F0A190   // Set tREFPRD (9*3.904us - 600)
DATA 4 DDR_PHY_PGCR3_0 0x050A1080   // CKEN/CKNEN toggling and polarity

  // Set-up PHY Timing Register
  // PTR2 is untouched
DATA 4 DDR_PHY_PTR0_0 0x4B025810   // tPLLPD, tPLLGS, tPHYRST
DATA 4 DDR_PHY_PTR1_0 0x3AA01520   // tPLLLOCK reduced to 4.3us, tPLLRST=9us

  // Set-up PLL Control Register
DATA 4 DDR_PHY_PLLCR0_0 0x000E0000   // FREQSEL=0
DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x000E0000

  // Set-up Impedance Control Register
DATA 4 DDR_PHY_ZQCR_0 0x008A2C58   // Set ODT_MODE=0b10(LPDDR4 stype pullup)

  // ZPROG_DRAM_ODT and ZPROG_HOST_ODT = 60ohm
//DATA 4 DDR_PHY_ZQ0PR0_0 0x0B7BB        // comment is wrong => PU_DRV_ADJUST 3b001 = Adjust calibrated drive strength by 2/8 to obtain 1.25x of original strength
//DATA 4 DDR_PHY_ZQ1PR0_0 0x0B7BB
//DATA 4 DDR_PHY_ZQ2PR0_0 0x0B7BB
//DATA 4 DDR_PHY_ZQ3PR0_0 0x0B7BB
DATA 4 DDR_PHY_ZQ0PR0_0 0x1B7BB        // PU_DRV_ADJUST 3b001 = Adjust calibrated drive strength by 2/8 to obtain 1.25x of original strength
DATA 4 DDR_PHY_ZQ1PR0_0 0x1B7BB
DATA 4 DDR_PHY_ZQ2PR0_0 0x1B7BB
DATA 4 DDR_PHY_ZQ3PR0_0 0x1B7BB


  // Set-up PHY Initialization Register
DATA 4 DDR_PHY_PIR_0 0x32

  // Launch initialization (set bit 0)
DATA 4 DDR_PHY_PIR_0 0x33

  //-------------------------------------------
  // Configure registers for DRAM initialization
  //-------------------------------------------

  // Set-up Mode Register
  // MR0, MR3, MR4, MR5 MR6 are untouched
DATA 4 DDR_PHY_MR1_0 0x44         // Set BL, WR-PRE, nWR=24, RPST
DATA 4 DDR_PHY_MR2_0 0x24         // Set RL=14/WL=8
//DATA 4 DDR_PHY_MR3_0 0x31         // Set drive strength (40 Ohms by default)
DATA 4 DDR_PHY_MR3_0 0xF1         // Set drive strength (40 Ohms by default), DBI_RD=DBI_WR=1
DATA 4 DDR_PHY_MR11_0 0x05        // Set CA ODT=Disable DQ_ODT=RZQ/5
DATA 4 DDR_PHY_MR22_0 0x15        // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks), SoC ODT = RZQ/5

/* LPDDR4 mode register writes for CA and DQ VREF settings; range=1, 27.2% */
DATA 4 DDR_PHY_MR12_0 0x48
DATA 4 DDR_PHY_MR14_0 0x48

  // Set-up DRAM Timing Parameters Register
  // DTPR6 is untouched
DATA 4 DDR_PHY_DTPR0_0 0x0d331a09   // tRRD, tRAS, tRP, tRTP
DATA 4 DDR_PHY_DTPR1_0 0x28310411   // tWLMRD, tFAW, tODTUP, tMRD
DATA 4 DDR_PHY_DTPR2_0 0x006a615a   // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS
DATA 4 DDR_PHY_DTPR3_0 0x01800501   // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK)
DATA 4 DDR_PHY_DTPR4_0 0x01512b0D   // tRFC, tWLO, tXP
DATA 4 DDR_PHY_DTPR5_0 0x194c160d   // tRC, tRCD, tWTR

  // Set-up PHY Timing Register
DATA 4 DDR_PHY_PTR3_0 0x00249F80   // tDINIT0 - 2ms
DATA 4 DDR_PHY_PTR4_0 0x00000970   // tDINIT1 (2000ns)
DATA 4 DDR_PHY_PTR5_0 0x0003A9A0   // tDINIT2 - normally 200us but memory model hacked to 20us
DATA 4 DDR_PHY_PTR6_0 0x027004B5   // tDINIT4 (30ns), tDINIT3 (1us)

  // RDIMMGCR0-2 RDIMMGCR0-4??

  // Set-up DATX8 Common Configuration Register
  // DXCCR is untouched

  // Set-up DDR System General Configuration Register
  // DSGCR is untouched

  // Set-up ODT Configuration Register
  // DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically.
DATA 4 DDR_PHY_RANKIDR_0 1            // Select rank 1 to write
DATA 4 DDR_PHY_ODTCR_0 0x00000000     // ODT of rank1 disabled
DATA 4 DDR_PHY_RANKIDR_0 0            // Select rank 0 to write
DATA 4 DDR_PHY_ODTCR_0 0x00000000     // ODT of rank0 disabled

  // Set-up Anti-Aging Control Register
  // AACR is untouched

  // Set-up Data Training Address Register
  // DTAR0-3 are untouched
  // !! DTAR3 is not described in spec !!

  // Set-up AC I/O Configuration Register
  // ACIOCR1-4 are untouched
DATA 4 DDR_PHY_ACIOCR0_0 0x30070800   // PNUM2 (i.e.LPDDR4) selection  [10:11] = 0x2
DATA 4 DDR_PHY_ACIOCR5_0 0x09000000   // I/O mode = LPDDR4
  // Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON.
DATA 4 DDR_PHY_ACIOCR1_0 0x44000000

  // IOVCR0-1, DXnGCR0-4??, CALBYP

  // Set-up VREF Training Control Registers
DATA 4 DDR_PHY_VTCR0_0 0xF0032019   // CK1, CK0
DATA 4 DDR_PHY_VTCR1_0 0x07F00193   // HVIO=1, SHREN=1, SHRNK=0

  // Set-up DATX8 General Configuration Registers
  // DXnGCR0-4 are untouched
DATA 4 DDR_PHY_PGCR5_0 0x01010004
DATA 4 DDR_PHY_PGCR6_0 0x00033200   // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit

// Set-up DATX8 General Configuration Registers
DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults
DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults
DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults

  // Set-up DATX8 DX Control Register 2
  // PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA
DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400

  // Set-up DATX8 IO Control Register
DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000  // I/O mode = LPDDR4

#if 1
/* DDR training is performed in FW, remove here */

  // Wait for bit 0 of PGSR0 to be '1'
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
  // Check that no error occured
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000

  // Launch DRAM initialization
DATA 4 DDR_PHY_PIR_0 0x180
DATA 4 DDR_PHY_PIR_0 0x181

  // Wait for bit 0 of PGSR0 to be '1'
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
  // Check that no error occured
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000

  // Launch a second time DRAM initialization due to following Synopsys PHY bug:
  // Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration"
  // Workaround: "Run DRAM Initialization twice"
DATA 4 DDR_PHY_PIR_0 0x100
DATA 4 DDR_PHY_PIR_0 0x101

  // Wait for bit 0 of PGSR0 to be '1'
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
  // Check that no error occured
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000

  // Set-up Data Training Configuration Register
  // Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys
  // case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training).
  // (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED).
DATA 4 DDR_PHY_DTCR0_0 0x000071CF   // Set DTRPTN to 0xF. RFSHDT=0
DATA 4 DDR_PHY_DTCR1_0 0x00030236   // Set RANKEN=3

CLR_BIT 4 DDR_PHY_DX4GCR1_0 0xFF

/*  -- Write leveling */
DATA 4 DDR_PHY_PIR_0 0x00000200
DATA 4 DDR_PHY_PIR_0 0x00000201

  // Wait for bit 0 of PGSR0 to be '1'
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
  // Check that no error occured
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000

// -- Read DQS training
// Set DQS/DQSn glitch suppression resistor for training
DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7

/* Launch training for DRC_0 */
DATA 4 DDR_PHY_PIR_0 0x00000400
DATA 4 DDR_PHY_PIR_0 0x00000401

  // Wait for bit 0 of PGSR0 to be '1'
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
  // Check that no error occured
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000

/* Remove DQS/DQSn glitch suppression resistor */
DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000

/* DQS2DQ training, Write leveling, Deskew and eye trainings */
DATA 4 DDR_PHY_PIR_0 0x0010F800
DATA 4 DDR_PHY_PIR_0 0x0010F801

  // Wait for bit 0 of PGSR0 to be '1'
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
  // Check that no error occured
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000

/* VREF training for DRC_0 */
DATA 4 DDR_PHY_PIR_0 0x00020000
DATA 4 DDR_PHY_PIR_0 0x00020001

  // Wait for bit 0 of PGSR0 to be '1'
CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1
  // Check that no error occured
CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00080000

  //Re-allow uMCTL2 to send commands to DDR
CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020000

SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000
SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000

//DQS Drift Registers
CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000
CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000
CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000
CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000
DATA 4 DDR_PHY_DQSDR0_0 0x20188005
//DATA 4 DDR_PHY_DQSDR1_0 0xA8770100
//DATA 4 DDR_PHY_DQSDR2_0 0x00062000
DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000  // SNPS recommendation
DATA 4 DDR_PHY_DQSDR2_0 0x00070200 // SNPS recommendation

//Check that controller is ready to operate
CHECK_BITS_SET 4 DDRC_STAT_0 0x1
#endif