| /* |
| * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. |
| * |
| * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| * |
| * |
| * Permission to use, copy, modify, and/or distribute this software for |
| * any purpose with or without fee is hereby granted, provided that the |
| * above copyright notice and this permission notice appear in all |
| * copies. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| * PERFORMANCE OF THIS SOFTWARE. |
| */ |
| |
| /* |
| * This file was originally distributed by Qualcomm Atheros, Inc. |
| * under proprietary terms before Copyright ownership was assigned |
| * to the Linux Foundation. |
| */ |
| |
| /** |
| * @file htt.h |
| * |
| * @details the public header file of HTT layer |
| */ |
| |
| #ifndef _HTT_H_ |
| #define _HTT_H_ |
| |
| #include <a_types.h> /* A_UINT32 */ |
| #include <a_osapi.h> /* PREPACK, POSTPACK */ |
| #ifdef ATHR_WIN_NWF |
| #pragma warning( disable:4214 ) //bit field types other than int |
| #endif |
| #include "wlan_defs.h" |
| #include <htt_common.h> |
| |
| /* |
| * Unless explicitly specified to use 64 bits to represent physical addresses |
| * (or more precisely, bus addresses), default to 32 bits. |
| */ |
| #ifndef HTT_PADDR64 |
| #define HTT_PADDR64 0 |
| #endif |
| |
| #ifndef offsetof |
| #define offsetof(type, field) ((unsigned int)(&((type *)0)->field)) |
| #endif |
| |
| /* |
| * HTT version history: |
| * 1.0 initial numbered version |
| * 1.1 modifications to STATS messages. |
| * These modifications are not backwards compatible, but since the |
| * STATS messages themselves are non-essential (they are for debugging), |
| * the 1.1 version of the HTT message library as a whole is compatible |
| * with the 1.0 version. |
| * 1.2 reset mask IE added to STATS_REQ message |
| * 1.3 stat config IE added to STATS_REQ message |
| *---- |
| * 2.0 FW rx PPDU desc added to RX_IND message |
| * 2.1 Enable msdu_ext/frag_desc banking change for WIFI2.0 |
| *---- |
| * 3.0 Remove HTT_H2T_MSG_TYPE_MGMT_TX message |
| * 3.1 Added HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND message |
| * 3.2 Added HTT_H2T_MSG_TYPE_WDI_IPA_CFG, |
| * HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQUEST messages |
| * 3.3 Added HTT_H2T_MSG_TYPE_AGGR_CFG_EX message |
| * 3.4 Added tx_compl_req flag in HTT tx descriptor |
| * 3.5 Added flush and fail stats in rx_reorder stats structure |
| * 3.6 Added frag flag in HTT RX INORDER PADDR IND header |
| * 3.7 Made changes to support EOS Mac_core 3.0 |
| * 3.8 Added txq_group information element definition; |
| * added optional txq_group suffix to TX_CREDIT_UPDATE_IND message |
| * 3.9 Added HTT_T2H CHAN_CHANGE message; |
| * Allow buffer addresses in bus-address format to be stored as |
| * either 32 bits or 64 bits. |
| * 3.10 Add optional TLV extensions to the VERSION_REQ and VERSION_CONF |
| * messages to specify which HTT options to use. |
| * Initial TLV options cover: |
| * - whether to use 32 or 64 bits to represent LL bus addresses |
| * - whether to use TX_COMPL_IND or TX_CREDIT_UPDATE_IND in HL systems |
| * - how many tx queue groups to use |
| * 3.11 Expand rx debug stats: |
| * - Expand the rx_reorder_stats struct with stats about successful and |
| * failed rx buffer allcoations. |
| * - Add a new rx_remote_buffer_mgmt_stats struct with stats about |
| * the supply, allocation, use, and recycling of rx buffers for the |
| * "remote ring" of rx buffers in host member in LL systems. |
| * Add RX_REMOTE_RING_BUFFER_INFO stats type for uploading these stats. |
| * 3.12 Add "rx offload packet error" message with initial "MIC error" subtype |
| * 3.13 Add constants + macros to support 64-bit address format for the |
| * tx fragments descriptor, the rx ring buffer, and the rx ring |
| * index shadow register. |
| * 3.14 Add a method for the host to provide detailed per-frame tx specs: |
| * - Add htt_tx_msdu_desc_ext_t struct def. |
| * - Add TLV to specify whether the target supports the HTT tx MSDU |
| * extension descriptor. |
| * - Change a reserved bit in the HTT tx MSDU descriptor to an |
| * "extension" bit, to specify whether a HTT tx MSDU extension |
| * descriptor is present. |
| * 3.15 Add HW rx desc info to per-MSDU info elems in RX_IN_ORD_PADDR_IND msg. |
| * (This allows the host to obtain key information about the MSDU |
| * from a memory location already in the cache, rather than taking a |
| * cache miss for each MSDU by reading the HW rx descs.) |
| * 3.16 Add htt_pkt_type_eth2 and define pkt_subtype flags to indicate |
| * whether a copy-engine classification result is appended to TX_FRM. |
| * 3.17 Add a version of the WDI_IPA_CFG message; add RX_RING2 to WDI_IPA_CFG |
| * 3.18 Add a PEER_DEL tx completion indication status, for HL cleanup of |
| * tx frames in the target after the peer has already been deleted. |
| * 3.19 Add HTT_DBG_STATS_RX_RATE_INFO_V2 and HTT_DBG_STATS_TX_RATE_INFO_V2 |
| * 3.20 Expand rx_reorder_stats. |
| * 3.21 Add optional rx channel spec to HL RX_IND. |
| * 3.22 Expand rx_reorder_stats |
| * (distinguish duplicates within vs. outside block ack window) |
| * 3.23 Add HTT_T2H_MSG_TYPE_RATE_REPORT to report peer justified rate. |
| * The justified rate is calculated by two steps. The first is to |
| * multiply user-rate by (1 - PER) and the other is to smooth the |
| * step 1's result by a low pass filter. |
| * This change allows HL download scheduling to consider the WLAN |
| * rate that will be used for transmitting the downloaded frames. |
| * 3.24 Expand rx_reorder_stats |
| * (add counter for decrypt / MIC errors) |
| * 3.25 Expand rx_reorder_stats |
| * (add counter of frames received into both local + remote rings) |
| * 3.26 Add stats struct for counting rx of tx BF, MU, SU, and NDPA frames |
| * (HTT_DBG_STATS_TXBF_MUSU_NDPA_PKT, rx_txbf_musu_ndpa_pkts_stats) |
| * 3.27 Add a new interface for flow-control. The following t2h messages have |
| * been included: HTT_T2H_MSG_TYPE_FLOW_POOL_MAP and |
| * HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP |
| * 3.28 Add a new interface for ring interface change. The following two h2t |
| * and one t2h messages have been included: |
| * HTT_H2T_MSG_TYPE_SRING_SETUP, HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG, |
| * and HTT_T2H_MSG_TYPE_SRING_SETUP_DONE |
| */ |
| #define HTT_CURRENT_VERSION_MAJOR 3 |
| #define HTT_CURRENT_VERSION_MINOR 28 |
| |
| #define HTT_NUM_TX_FRAG_DESC 1024 |
| |
| #define HTT_WIFI_IP_VERSION(x,y) ((x) == (y)) |
| |
| #define HTT_CHECK_SET_VAL(field, val) \ |
| A_ASSERT(!((val) & ~((field ## _M) >> (field ## _S)))) |
| |
| /* macros to assist in sign-extending fields from HTT messages */ |
| #define HTT_SIGN_BIT_MASK(field) \ |
| ((field ## _M + (1 << field ## _S)) >> 1) |
| #define HTT_SIGN_BIT(_val, field) \ |
| (_val & HTT_SIGN_BIT_MASK(field)) |
| #define HTT_SIGN_BIT_UNSHIFTED(_val, field) \ |
| (HTT_SIGN_BIT(_val, field) >> field ## _S) |
| #define HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field) \ |
| (HTT_SIGN_BIT_UNSHIFTED(_val, field) - 1) |
| #define HTT_SIGN_BIT_EXTENSION(_val, field) \ |
| (~(HTT_SIGN_BIT_UNSHIFTED(_val, field) | \ |
| HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field))) |
| #define HTT_SIGN_BIT_EXTENSION_MASK(_val, field) \ |
| (HTT_SIGN_BIT_EXTENSION(_val, field) & ~(field ## _M >> field ## _S)) |
| |
| |
| /* |
| * TEMPORARY: |
| * Provide HTT_H2T_MSG_TYPE_MGMT_TX as an alias for |
| * DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX until all code |
| * that refers to HTT_H2T_MSG_TYPE_MGMT_TX has been |
| * updated. |
| */ |
| #define HTT_H2T_MSG_TYPE_MGMT_TX DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX |
| |
| /* |
| * TEMPORARY: |
| * Provide HTT_T2H_MSG_TYPE_RC_UPDATE_IND as an alias for |
| * DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND until all code |
| * that refers to HTT_T2H_MSG_TYPE_RC_UPDATE_IND has been |
| * updated. |
| */ |
| #define HTT_T2H_MSG_TYPE_RC_UPDATE_IND DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND |
| |
| /* HTT Access Category values */ |
| enum HTT_AC_WMM { |
| /* WMM Access Categories */ |
| HTT_AC_WMM_BE = 0x0, |
| HTT_AC_WMM_BK = 0x1, |
| HTT_AC_WMM_VI = 0x2, |
| HTT_AC_WMM_VO = 0x3, |
| /* extension Access Categories */ |
| HTT_AC_EXT_NON_QOS = 0x4, |
| HTT_AC_EXT_UCAST_MGMT = 0x5, |
| HTT_AC_EXT_MCAST_DATA = 0x6, |
| HTT_AC_EXT_MCAST_MGMT = 0x7, |
| }; |
| enum HTT_AC_WMM_MASK { |
| /* WMM Access Categories */ |
| HTT_AC_WMM_BE_MASK = (1 << HTT_AC_WMM_BE), |
| HTT_AC_WMM_BK_MASK = (1 << HTT_AC_WMM_BK), |
| HTT_AC_WMM_VI_MASK = (1 << HTT_AC_WMM_VI), |
| HTT_AC_WMM_VO_MASK = (1 << HTT_AC_WMM_VO), |
| /* extension Access Categories */ |
| HTT_AC_EXT_NON_QOS_MASK = (1 << HTT_AC_EXT_NON_QOS), |
| HTT_AC_EXT_UCAST_MGMT_MASK = (1 << HTT_AC_EXT_UCAST_MGMT), |
| HTT_AC_EXT_MCAST_DATA_MASK = (1 << HTT_AC_EXT_MCAST_DATA), |
| HTT_AC_EXT_MCAST_MGMT_MASK = (1 << HTT_AC_EXT_MCAST_MGMT), |
| }; |
| #define HTT_AC_MASK_WMM \ |
| (HTT_AC_WMM_BE_MASK | HTT_AC_WMM_BK_MASK | \ |
| HTT_AC_WMM_VI_MASK | HTT_AC_WMM_VO_MASK) |
| #define HTT_AC_MASK_EXT \ |
| (HTT_AC_EXT_NON_QOS_MASK | HTT_AC_EXT_UCAST_MGMT_MASK | \ |
| HTT_AC_EXT_MCAST_DATA_MASK | HTT_AC_EXT_MCAST_MGMT_MASK) |
| #define HTT_AC_MASK_ALL (HTT_AC_MASK_WMM | HTT_AC_MASK_EXT) |
| |
| /* |
| * htt_dbg_stats_type - |
| * bit positions for each stats type within a stats type bitmask |
| * The bitmask contains 24 bits. |
| */ |
| enum htt_dbg_stats_type { |
| HTT_DBG_STATS_WAL_PDEV_TXRX = 0, /* bit 0 -> 0x1 */ |
| HTT_DBG_STATS_RX_REORDER = 1, /* bit 1 -> 0x2 */ |
| HTT_DBG_STATS_RX_RATE_INFO = 2, /* bit 2 -> 0x4 */ |
| HTT_DBG_STATS_TX_PPDU_LOG = 3, /* bit 3 -> 0x8 */ |
| HTT_DBG_STATS_TX_RATE_INFO = 4, /* bit 4 -> 0x10 */ |
| HTT_DBG_STATS_TIDQ = 5, /* bit 5 -> 0x20 */ |
| HTT_DBG_STATS_TXBF_INFO = 6, /* bit 6 -> 0x40 */ |
| HTT_DBG_STATS_SND_INFO = 7, /* bit 7 -> 0x80 */ |
| HTT_DBG_STATS_ERROR_INFO = 8, /* bit 8 -> 0x100 */ |
| HTT_DBG_STATS_TX_SELFGEN_INFO = 9, /* bit 9 -> 0x200 */ |
| HTT_DBG_STATS_TX_MU_INFO = 10, /* bit 10 -> 0x400 */ |
| HTT_DBG_STATS_SIFS_RESP_INFO = 11, /* bit 11 -> 0x800 */ |
| HTT_DBG_STATS_RX_REMOTE_RING_BUFFER_INFO = 12, /* bit 12 -> 0x1000*/ |
| HTT_DBG_STATS_RX_RATE_INFO_V2 = 13, /* bit 13 -> 0x2000 */ |
| HTT_DBG_STATS_TX_RATE_INFO_V2 = 14, /* bit 14 -> 0x4000 */ |
| HTT_DBG_STATS_TXBF_MUSU_NDPA_PKT = 15, /* bit 15 -> 0x8000 */ |
| /* bits 16-23 currently reserved */ |
| |
| /* keep this last */ |
| HTT_DBG_NUM_STATS |
| }; |
| |
| /*=== HTT option selection TLVs === |
| * Certain HTT messages have alternatives or options. |
| * For such cases, the host and target need to agree on which option to use. |
| * Option specification TLVs can be appended to the VERSION_REQ and |
| * VERSION_CONF messages to select options other than the default. |
| * These TLVs are entirely optional - if they are not provided, there is a |
| * well-defined default for each option. If they are provided, they can be |
| * provided in any order. Each TLV can be present or absent independent of |
| * the presence / absence of other TLVs. |
| * |
| * The HTT option selection TLVs use the following format: |
| * |31 16|15 8|7 0| |
| * |---------------------------------+----------------+----------------| |
| * | value (payload) | length | tag | |
| * |-------------------------------------------------------------------| |
| * The value portion need not be only 2 bytes; it can be extended by any |
| * integer number of 4-byte units. The total length of the TLV, including |
| * the tag and length fields, must be a multiple of 4 bytes. The length |
| * field specifies the total TLV size in 4-byte units. Thus, the typical |
| * TLV, with a 1-byte tag field, a 1-byte length field, and a 2-byte value |
| * field, would store 0x1 in its length field, to show that the TLV occupies |
| * a single 4-byte unit. |
| */ |
| |
| /*--- TLV header format - applies to all HTT option TLVs ---*/ |
| |
| enum HTT_OPTION_TLV_TAGS { |
| HTT_OPTION_TLV_TAG_RESERVED0 = 0x0, |
| HTT_OPTION_TLV_TAG_LL_BUS_ADDR_SIZE = 0x1, |
| HTT_OPTION_TLV_TAG_HL_SUPPRESS_TX_COMPL_IND = 0x2, |
| HTT_OPTION_TLV_TAG_MAX_TX_QUEUE_GROUPS = 0x3, |
| HTT_OPTION_TLV_TAG_SUPPORT_TX_MSDU_DESC_EXT = 0x4, |
| }; |
| |
| PREPACK struct htt_option_tlv_header_t { |
| A_UINT8 tag; |
| A_UINT8 length; |
| } POSTPACK; |
| |
| #define HTT_OPTION_TLV_TAG_M 0x000000ff |
| #define HTT_OPTION_TLV_TAG_S 0 |
| #define HTT_OPTION_TLV_LENGTH_M 0x0000ff00 |
| #define HTT_OPTION_TLV_LENGTH_S 8 |
| /* |
| * value0 - 16 bit value field stored in word0 |
| * The TLV's value field may be longer than 2 bytes, in which case |
| * the remainder of the value is stored in word1, word2, etc. |
| */ |
| #define HTT_OPTION_TLV_VALUE0_M 0xffff0000 |
| #define HTT_OPTION_TLV_VALUE0_S 16 |
| |
| #define HTT_OPTION_TLV_TAG_SET(word, tag) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_OPTION_TLV_TAG, tag); \ |
| (word) |= ((tag) << HTT_OPTION_TLV_TAG_S); \ |
| } while (0) |
| #define HTT_OPTION_TLV_TAG_GET(word) \ |
| (((word) & HTT_OPTION_TLV_TAG_M) >> HTT_OPTION_TLV_TAG_S) |
| |
| #define HTT_OPTION_TLV_LENGTH_SET(word, tag) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_OPTION_TLV_LENGTH, tag); \ |
| (word) |= ((tag) << HTT_OPTION_TLV_LENGTH_S); \ |
| } while (0) |
| #define HTT_OPTION_TLV_LENGTH_GET(word) \ |
| (((word) & HTT_OPTION_TLV_LENGTH_M) >> HTT_OPTION_TLV_LENGTH_S) |
| |
| #define HTT_OPTION_TLV_VALUE0_SET(word, tag) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_OPTION_TLV_VALUE0, tag); \ |
| (word) |= ((tag) << HTT_OPTION_TLV_VALUE0_S); \ |
| } while (0) |
| #define HTT_OPTION_TLV_VALUE0_GET(word) \ |
| (((word) & HTT_OPTION_TLV_VALUE0_M) >> HTT_OPTION_TLV_VALUE0_S) |
| |
| /*--- format of specific HTT option TLVs ---*/ |
| |
| /* |
| * HTT option TLV for specifying LL bus address size |
| * Some chips require bus addresses used by the target to access buffers |
| * within the host's memory to be 32 bits; others require bus addresses |
| * used by the target to access buffers within the host's memory to be |
| * 64 bits. |
| * The LL_BUS_ADDR_SIZE TLV can be sent from the target to the host as |
| * a suffix to the VERSION_CONF message to specify which bus address format |
| * the target requires. |
| * If this LL_BUS_ADDR_SIZE TLV is not sent by the target, the host should |
| * default to providing bus addresses to the target in 32-bit format. |
| */ |
| enum HTT_OPTION_TLV_LL_BUS_ADDR_SIZE_VALUES { |
| HTT_OPTION_TLV_LL_BUS_ADDR_SIZE32 = 0x0, |
| HTT_OPTION_TLV_LL_BUS_ADDR_SIZE64 = 0x1, |
| }; |
| PREPACK struct htt_option_tlv_ll_bus_addr_size_t { |
| struct htt_option_tlv_header_t hdr; |
| A_UINT16 ll_bus_addr_size; /* LL_BUS_ADDR_SIZE_VALUES enum */ |
| } POSTPACK; |
| |
| /* |
| * HTT option TLV for specifying whether HL systems should indicate |
| * over-the-air tx completion for individual frames, or should instead |
| * send a bulk TX_CREDIT_UPDATE_IND except when the host explicitly |
| * requests an OTA tx completion for a particular tx frame. |
| * This option does not apply to LL systems, where the TX_COMPL_IND |
| * is mandatory. |
| * This option is primarily intended for HL systems in which the tx frame |
| * downloads over the host --> target bus are as slow as or slower than |
| * the transmissions over the WLAN PHY. For cases where the bus is faster |
| * than the WLAN PHY, the target will transmit relatively large A-MPDUs, |
| * and consquently will send one TX_COMPL_IND message that covers several |
| * tx frames. For cases where the WLAN PHY is faster than the bus, |
| * the target will end up transmitting very short A-MPDUs, and consequently |
| * sending many TX_COMPL_IND messages, which each cover a very small number |
| * of tx frames. |
| * The HL_SUPPRESS_TX_COMPL_IND TLV can be sent by the host to the target as |
| * a suffix to the VERSION_REQ message to request whether the host desires to |
| * use TX_CREDIT_UPDATE_IND rather than TX_COMPL_IND. The target can then |
| * send a HTT_SUPPRESS_TX_COMPL_IND TLV to the host as a suffix to the |
| * VERSION_CONF message to confirm whether TX_CREDIT_UPDATE_IND will be used |
| * rather than TX_COMPL_IND. TX_CREDIT_UPDATE_IND shall only be used if the |
| * host sends a HL_SUPPRESS_TX_COMPL_IND TLV requesting use of |
| * TX_CREDIT_UPDATE_IND, and the target sends a HL_SUPPRESS_TX_COMPLE_IND TLV |
| * back to the host confirming use of TX_CREDIT_UPDATE_IND. |
| * Lack of a HL_SUPPRESS_TX_COMPL_IND TLV from either host --> target or |
| * target --> host is equivalent to a HL_SUPPRESS_TX_COMPL_IND that |
| * explicitly specifies HL_ALLOW_TX_COMPL_IND in the value payload of the |
| * TLV. |
| */ |
| enum HTT_OPTION_TLV_HL_SUPPRESS_TX_COMPL_IND_VALUES { |
| HTT_OPTION_TLV_HL_ALLOW_TX_COMPL_IND = 0x0, |
| HTT_OPTION_TLV_HL_SUPPRESS_TX_COMPL_IND = 0x1, |
| }; |
| PREPACK struct htt_option_tlv_hl_suppress_tx_compl_ind_t { |
| struct htt_option_tlv_header_t hdr; |
| A_UINT16 hl_suppress_tx_compl_ind; /* HL_SUPPRESS_TX_COMPL_IND enum */ |
| } POSTPACK; |
| |
| /* |
| * HTT option TLV for specifying how many tx queue groups the target |
| * may establish. |
| * This TLV specifies the maximum value the target may send in the |
| * txq_group_id field of any TXQ_GROUP information elements sent by |
| * the target to the host. This allows the host to pre-allocate an |
| * appropriate number of tx queue group structs. |
| * |
| * The MAX_TX_QUEUE_GROUPS_TLV can be sent from the host to the target as |
| * a suffix to the VERSION_REQ message to specify whether the host supports |
| * tx queue groups at all, and if so if there is any limit on the number of |
| * tx queue groups that the host supports. |
| * The MAX_TX_QUEUE_GROUPS TLV can be sent from the target to the host as |
| * a suffix to the VERSION_CONF message. If the host has specified in the |
| * VER_REQ message a limit on the number of tx queue groups the host can |
| * supprt, the target shall limit its specification of the maximum tx groups |
| * to be no larger than this host-specified limit. |
| * |
| * If the target does not provide a MAX_TX_QUEUE_GROUPS TLV, then the host |
| * shall preallocate 4 tx queue group structs, and the target shall not |
| * specify a txq_group_id larger than 3. |
| */ |
| enum HTT_OPTION_TLV_MAX_TX_QUEUE_GROUPS_VALUES { |
| HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNSUPPORTED = 0, |
| /* |
| * values 1 through N specify the max number of tx queue groups |
| * the sender supports |
| */ |
| HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNLIMITED = 0xffff, |
| }; |
| /* TEMPORARY backwards-compatibility alias for a typo fix - |
| * The htt_option_tlv_mac_tx_queue_groups_t typo has been corrected |
| * to htt_option_tlv_max_tx_queue_groups_t, but an alias is provided |
| * to support the old name (with the typo) until all references to the |
| * old name are replaced with the new name. |
| */ |
| #define htt_option_tlv_mac_tx_queue_groups_t htt_option_tlv_max_tx_queue_groups_t |
| PREPACK struct htt_option_tlv_max_tx_queue_groups_t { |
| struct htt_option_tlv_header_t hdr; |
| A_UINT16 max_tx_queue_groups; /* max txq_group_id + 1 */ |
| } POSTPACK; |
| |
| /* |
| * HTT option TLV for specifying whether the target supports an extended |
| * version of the HTT tx descriptor. If the target provides this TLV |
| * and specifies in the TLV that the target supports an extended version |
| * of the HTT tx descriptor, the target must check the "extension" bit in |
| * the HTT tx descriptor, and if the extension bit is set, to expect a |
| * HTT tx MSDU extension descriptor immediately following the HTT tx MSDU |
| * descriptor. Furthermore, the target must provide room for the HTT |
| * tx MSDU extension descriptor in the target's TX_FRM buffer. |
| * This option is intended for systems where the host needs to explicitly |
| * control the transmission parameters such as tx power for individual |
| * tx frames. |
| * The SUPPORT_TX_MSDU_DESC_EXT TLB can be sent by the target to the host |
| * as a suffix to the VERSION_CONF message to explicitly specify whether |
| * the target supports the HTT tx MSDU extension descriptor. |
| * Lack of a SUPPORT_TX_MSDU_DESC_EXT from the target shall be interpreted |
| * by the host as lack of target support for the HTT tx MSDU extension |
| * descriptor; the host shall provide HTT tx MSDU extension descriptors in |
| * the HTT_H2T TX_FRM messages only if the target indicates it supports |
| * the HTT tx MSDU extension descriptor. |
| * The host is not required to provide the HTT tx MSDU extension descriptor |
| * just because the target supports it; the target must check the |
| * "extension" bit in the HTT tx MSDU descriptor to determine whether an |
| * extension descriptor is present. |
| */ |
| enum HTT_OPTION_TLV_SUPPORT_TX_MSDU_DESC_EXT_VALUES { |
| HTT_OPTION_TLV_TX_MSDU_DESC_EXT_NO_SUPPORT = 0x0, |
| HTT_OPTION_TLV_TX_MSDU_DESC_EXT_SUPPORT = 0x1, |
| }; |
| PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t { |
| struct htt_option_tlv_header_t hdr; |
| A_UINT16 tx_msdu_desc_ext_support; /* SUPPORT_TX_MSDU_DESC_EXT enum */ |
| } POSTPACK; |
| |
| |
| /*=== host -> target messages ===============================================*/ |
| |
| enum htt_h2t_msg_type { |
| HTT_H2T_MSG_TYPE_VERSION_REQ = 0x0, |
| HTT_H2T_MSG_TYPE_TX_FRM = 0x1, |
| HTT_H2T_MSG_TYPE_RX_RING_CFG = 0x2, |
| HTT_H2T_MSG_TYPE_STATS_REQ = 0x3, |
| HTT_H2T_MSG_TYPE_SYNC = 0x4, |
| HTT_H2T_MSG_TYPE_AGGR_CFG = 0x5, |
| HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 0x6, |
| DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX = 0x7, /* no longer used */ |
| HTT_H2T_MSG_TYPE_WDI_IPA_CFG = 0x8, |
| HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ = 0x9, |
| HTT_H2T_MSG_TYPE_AGGR_CFG_EX = 0xa, /* per vdev amsdu subfrm limit */ |
| HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, |
| HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, |
| /* keep this last */ |
| HTT_H2T_NUM_MSGS |
| }; |
| |
| /* |
| * HTT host to target message type - |
| * stored in bits 7:0 of the first word of the message |
| */ |
| #define HTT_H2T_MSG_TYPE_M 0xff |
| #define HTT_H2T_MSG_TYPE_S 0 |
| |
| #define HTT_H2T_MSG_TYPE_SET(word, msg_type) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE, msg_type); \ |
| (word) |= ((msg_type) << HTT_H2T_MSG_TYPE_S); \ |
| } while (0) |
| #define HTT_H2T_MSG_TYPE_GET(word) \ |
| (((word) & HTT_H2T_MSG_TYPE_M) >> HTT_H2T_MSG_TYPE_S) |
| |
| /** |
| * @brief target -> host version number request message definition |
| * |
| * |31 24|23 16|15 8|7 0| |
| * |----------------+----------------+----------------+----------------| |
| * | reserved | msg type | |
| * |-------------------------------------------------------------------| |
| * : option request TLV (optional) | |
| * :...................................................................: |
| * |
| * The VER_REQ message may consist of a single 4-byte word, or may be |
| * extended with TLVs that specify which HTT options the host is requesting |
| * from the target. |
| * The following option TLVs may be appended to the VER_REQ message: |
| * - HL_SUPPRESS_TX_COMPL_IND |
| * - HL_MAX_TX_QUEUE_GROUPS |
| * These TLVs may appear in an arbitrary order. Any number of these TLVs |
| * may be appended to the VER_REQ message (but only one TLV of each type). |
| * |
| * Header fields: |
| * - MSG_TYPE |
| * Bits 7:0 |
| * Purpose: identifies this as a version number request message |
| * Value: 0x0 |
| */ |
| |
| #define HTT_VER_REQ_BYTES 4 |
| |
| /* TBDXXX: figure out a reasonable number */ |
| #define HTT_HL_DATA_SVC_PIPE_DEPTH 24 |
| #define HTT_LL_DATA_SVC_PIPE_DEPTH 64 |
| |
| /** |
| * @brief HTT tx MSDU descriptor |
| * |
| * @details |
| * The HTT tx MSDU descriptor is created by the host HTT SW for each |
| * tx MSDU. The HTT tx MSDU descriptor contains the information that |
| * the target firmware needs for the FW's tx processing, particularly |
| * for creating the HW msdu descriptor. |
| * The same HTT tx descriptor is used for HL and LL systems, though |
| * a few fields within the tx descriptor are used only by LL or |
| * only by HL. |
| * The HTT tx descriptor is defined in two manners: by a struct with |
| * bitfields, and by a series of [dword offset, bit mask, bit shift] |
| * definitions. |
| * The target should use the struct def, for simplicitly and clarity, |
| * but the host shall use the bit-mast + bit-shift defs, to be endian- |
| * neutral. Specifically, the host shall use the get/set macros built |
| * around the mask + shift defs. |
| */ |
| #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_80211_HDR_S 0 |
| #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_80211_HDR_M 0x1 |
| #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_AGGR_S 1 |
| #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_AGGR_M 0x2 |
| #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_ENCRYPT_S 2 |
| #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_ENCRYPT_M 0x4 |
| #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_CLASSIFY_S 3 |
| #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_CLASSIFY_M 0x8 |
| |
| #define HTT_TX_VDEV_ID_WORD 0 |
| #define HTT_TX_VDEV_ID_MASK 0x3f |
| #define HTT_TX_VDEV_ID_SHIFT 16 |
| |
| #define HTT_TX_L3_CKSUM_OFFLOAD 1 |
| #define HTT_TX_L4_CKSUM_OFFLOAD 2 |
| |
| #define HTT_TX_MSDU_LEN_DWORD 1 |
| #define HTT_TX_MSDU_LEN_MASK 0xffff; |
| |
| /* |
| * HTT_VAR_PADDR macros |
| * Allow physical / bus addresses to be either a single 32-bit value, |
| * or a 64-bit value, stored as a little-endian lo,hi pair of 32-bit parts |
| */ |
| #define HTT_VAR_PADDR32(var_name) \ |
| A_UINT32 var_name |
| #define HTT_VAR_PADDR64_LE(var_name) \ |
| struct { \ |
| /* little-endian: lo precedes hi */ \ |
| A_UINT32 lo; \ |
| A_UINT32 hi; \ |
| } var_name |
| |
| /* |
| * TEMPLATE_HTT_TX_MSDU_DESC_T: |
| * This macro defines a htt_tx_msdu_descXXX_t in which any physical |
| * addresses are stored in a XXX-bit field. |
| * This macro is used to define both htt_tx_msdu_desc32_t and |
| * htt_tx_msdu_desc64_t structs. |
| */ |
| #define TEMPLATE_HTT_TX_MSDU_DESC_T(_paddr_bits_, _paddr__frags_desc_ptr_) \ |
| PREPACK struct htt_tx_msdu_desc ## _paddr_bits_ ## _t \ |
| { \ |
| /* DWORD 0: flags and meta-data */ \ |
| A_UINT32 \ |
| msg_type: 8, /* HTT_H2T_MSG_TYPE_TX_FRM */ \ |
| \ |
| /* pkt_subtype - \ |
| * Detailed specification of the tx frame contents, extending the \ |
| * general specification provided by pkt_type. \ |
| * FIX THIS: ADD COMPLETE SPECS FOR THIS FIELDS VALUE, e.g. \ |
| * pkt_type | pkt_subtype \ |
| * ============================================================== \ |
| * 802.3 | bit 0:3 - Reserved \ |
| * | bit 4: 0x0 - Copy-Engine Classification Results \ |
| * | not appended to the HTT message \ |
| * | 0x1 - Copy-Engine Classification Results \ |
| * | appended to the HTT message in the \ |
| * | format: \ |
| * | [HTT tx desc, frame header, \ |
| * | CE classification results] \ |
| * | The CE classification results begin \ |
| * | at the next 4-byte boundary after \ |
| * | the frame header. \ |
| * ------------+------------------------------------------------- \ |
| * Eth2 | bit 0:3 - Reserved \ |
| * | bit 4: 0x0 - Copy-Engine Classification Results \ |
| * | not appended to the HTT message \ |
| * | 0x1 - Copy-Engine Classification Results \ |
| * | appended to the HTT message. \ |
| * | See the above specification of the \ |
| * | CE classification results location. \ |
| * ------------+------------------------------------------------- \ |
| * native WiFi | bit 0:3 - Reserved \ |
| * | bit 4: 0x0 - Copy-Engine Classification Results \ |
| * | not appended to the HTT message \ |
| * | 0x1 - Copy-Engine Classification Results \ |
| * | appended to the HTT message. \ |
| * | See the above specification of the \ |
| * | CE classification results location. \ |
| * ------------+------------------------------------------------- \ |
| * mgmt | 0x0 - 802.11 MAC header absent \ |
| * | 0x1 - 802.11 MAC header present \ |
| * ------------+------------------------------------------------- \ |
| * raw | bit 0: 0x0 - 802.11 MAC header absent \ |
| * | 0x1 - 802.11 MAC header present \ |
| * | bit 1: 0x0 - allow aggregation \ |
| * | 0x1 - don't allow aggregation \ |
| * | bit 2: 0x0 - perform encryption \ |
| * | 0x1 - don't perform encryption \ |
| * | bit 3: 0x0 - perform tx classification / queuing \ |
| * | 0x1 - don't perform tx classification; \ |
| * | insert the frame into the "misc" \ |
| * | tx queue \ |
| * | bit 4: 0x0 - Copy-Engine Classification Results \ |
| * | not appended to the HTT message \ |
| * | 0x1 - Copy-Engine Classification Results \ |
| * | appended to the HTT message. \ |
| * | See the above specification of the \ |
| * | CE classification results location. \ |
| */ \ |
| pkt_subtype: 5, \ |
| \ |
| /* pkt_type - \ |
| * General specification of the tx frame contents. \ |
| * The htt_pkt_type enum should be used to specify and check the \ |
| * value of this field. \ |
| */ \ |
| pkt_type: 3, \ |
| \ |
| /* vdev_id - \ |
| * ID for the vdev that is sending this tx frame. \ |
| * For certain non-standard packet types, e.g. pkt_type == raw \ |
| * and (pkt_subtype >> 3) == 1, this field is not relevant/valid. \ |
| * This field is used primarily for determining where to queue \ |
| * broadcast and multicast frames. \ |
| */ \ |
| vdev_id: 6, \ |
| /* ext_tid - \ |
| * The extended traffic ID. \ |
| * If the TID is unknown, the extended TID is set to \ |
| * HTT_TX_EXT_TID_INVALID. \ |
| * If the tx frame is QoS data, then the extended TID has the 0-15 \ |
| * value of the QoS TID. \ |
| * If the tx frame is non-QoS data, then the extended TID is set to \ |
| * HTT_TX_EXT_TID_NON_QOS. \ |
| * If the tx frame is multicast or broadcast, then the extended TID \ |
| * is set to HTT_TX_EXT_TID_MCAST_BCAST. \ |
| */ \ |
| ext_tid: 5, \ |
| \ |
| /* postponed - \ |
| * This flag indicates whether the tx frame has been downloaded to \ |
| * the target before but discarded by the target, and now is being \ |
| * downloaded again; or if this is a new frame that is being \ |
| * downloaded for the first time. \ |
| * This flag allows the target to determine the correct order for \ |
| * transmitting new vs. old frames. \ |
| * value: 0 -> new frame, 1 -> re-send of a previously sent frame \ |
| * This flag only applies to HL systems, since in LL systems, \ |
| * the tx flow control is handled entirely within the target. \ |
| */ \ |
| postponed: 1, \ |
| \ |
| /* extension - \ |
| * This flag indicates whether a HTT tx MSDU extension descriptor \ |
| * (htt_tx_msdu_desc_ext_t) follows this HTT tx MSDU descriptor. \ |
| * \ |
| * 0x0 - no extension MSDU descriptor is present \ |
| * 0x1 - an extension MSDU descriptor immediately follows the \ |
| * regular MSDU descriptor \ |
| */ \ |
| extension: 1, \ |
| \ |
| /* cksum_offload - \ |
| * This flag indicates whether checksum offload is enabled or not \ |
| * for this frame. Target FW use this flag to turn on HW checksumming \ |
| * 0x0 - No checksum offload \ |
| * 0x1 - L3 header checksum only \ |
| * 0x2 - L4 checksum only \ |
| * 0x3 - L3 header checksum + L4 checksum \ |
| */ \ |
| cksum_offload: 2, \ |
| \ |
| /* tx_comp_req - \ |
| * This flag indicates whether Tx Completion \ |
| * from fw is required or not. \ |
| * This flag is only relevant if tx completion is not \ |
| * universally enabled. \ |
| * For all LL systems, tx completion is mandatory, \ |
| * so this flag will be irrelevant. \ |
| * For HL systems tx completion is optional, but HL systems in which \ |
| * the bus throughput exceeds the WLAN throughput will \ |
| * probably want to always use tx completion, and thus \ |
| * would not check this flag. \ |
| * This flag is required when tx completions are not used universally, \ |
| * but are still required for certain tx frames for which \ |
| * an OTA delivery acknowledgment is needed by the host. \ |
| * In practice, this would be for HL systems in which the \ |
| * bus throughput is less than the WLAN throughput. \ |
| * \ |
| * 0x0 - Tx Completion Indication from Fw not required \ |
| * 0x1 - Tx Completion Indication from Fw is required \ |
| */ \ |
| tx_compl_req: 1; \ |
| \ |
| \ |
| /* DWORD 1: MSDU length and ID */ \ |
| A_UINT32 \ |
| len: 16, /* MSDU length, in bytes */ \ |
| id: 16; /* MSDU ID used to identify the MSDU to the host, \ |
| * and this id is used to calculate fragmentation \ |
| * descriptor pointer inside the target based on \ |
| * the base address, configured inside the target. \ |
| */ \ |
| \ |
| /* DWORD 2 (or 2-3): fragmentation descriptor bus address */ \ |
| /* frags_desc_ptr - \ |
| * The fragmentation descriptor pointer tells the HW's MAC DMA \ |
| * where the tx frame's fragments reside in memory. \ |
| * This field only applies to LL systems, since in HL systems the \ |
| * (degenerate single-fragment) fragmentation descriptor is created \ |
| * within the target. \ |
| */ \ |
| _paddr__frags_desc_ptr_; \ |
| \ |
| /* DWORD 3 (or 4): peerid, chanfreq */ \ |
| /* \ |
| * Peer ID : Target can use this value to know which peer-id packet \ |
| * destined to. \ |
| * It's intended to be specified by host in case of NAWDS. \ |
| */ \ |
| A_UINT16 peerid; \ |
| \ |
| /* \ |
| * Channel frequency: This identifies the desired channel \ |
| * frequency (in mhz) for tx frames. This is used by FW to help \ |
| * determine when it is safe to transmit or drop frames for \ |
| * off-channel operation. \ |
| * The default value of zero indicates to FW that the corresponding \ |
| * VDEV's home channel (if there is one) is the desired channel \ |
| * frequency. \ |
| */ \ |
| A_UINT16 chanfreq; \ |
| \ |
| /* Reason reserved is commented is increasing the htt structure size \ |
| * leads to some wierd issues. Contact Raj/Kyeyoon for more info \ |
| * A_UINT32 reserved_dword3_bits0_31; \ |
| */ \ |
| } POSTPACK |
| /* define a htt_tx_msdu_desc32_t type */ |
| TEMPLATE_HTT_TX_MSDU_DESC_T(32, HTT_VAR_PADDR32(frags_desc_ptr)); |
| /* define a htt_tx_msdu_desc64_t type */ |
| TEMPLATE_HTT_TX_MSDU_DESC_T(64, HTT_VAR_PADDR64_LE(frags_desc_ptr)); |
| /* |
| * Make htt_tx_msdu_desc_t be an alias for either |
| * htt_tx_msdu_desc32_t or htt_tx_msdu_desc64_t |
| */ |
| #if HTT_PADDR64 |
| #define htt_tx_msdu_desc_t htt_tx_msdu_desc64_t |
| #else |
| #define htt_tx_msdu_desc_t htt_tx_msdu_desc32_t |
| #endif |
| |
| /* decriptor information for Management frame*/ |
| /* |
| * THIS htt_mgmt_tx_desc_t STRUCT IS DEPRECATED - DON'T USE IT. |
| * BOTH MANAGEMENT AND DATA FRAMES SHOULD USE htt_tx_msdu_desc_t. |
| */ |
| #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 |
| extern A_UINT32 mgmt_hdr_len; |
| PREPACK struct htt_mgmt_tx_desc_t { |
| A_UINT32 msg_type; |
| #if HTT_PADDR64 |
| A_UINT64 frag_paddr; /* DMAble address of the data */ |
| #else |
| A_UINT32 frag_paddr; /* DMAble address of the data */ |
| #endif |
| A_UINT32 desc_id; /* returned to host during completion |
| * to free the meory*/ |
| A_UINT32 len; /* Fragment length */ |
| A_UINT32 vdev_id; /* virtual device ID*/ |
| A_UINT8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; /* frm header */ |
| } POSTPACK; |
| |
| PREPACK struct htt_mgmt_tx_compl_ind { |
| A_UINT32 desc_id; |
| A_UINT32 status; |
| } POSTPACK; |
| |
| /* |
| * This SDU header size comes from the summation of the following: |
| * 1. Max of: |
| * a. Native WiFi header, for native WiFi frames: 24 bytes |
| * (frame control, duration / ID, addr1, addr2, addr3, seq ctrl, addr4) |
| * b. 802.11 header, for raw frames: 36 bytes |
| * (frame control, duration / ID, addr1, addr2, addr3, seq ctrl, addr4, |
| * QoS header, HT header) |
| * c. 802.3 header, for ethernet frames: 14 bytes |
| * (destination address, source address, ethertype / length) |
| * 2. Max of: |
| * a. IPv4 header, up through the DiffServ Code Point: 2 bytes |
| * b. IPv6 header, up through the Traffic Class: 2 bytes |
| * 3. 802.1Q VLAN header: 4 bytes |
| * 4. LLC/SNAP header: 8 bytes |
| */ |
| #define HTT_TX_HDR_SIZE_NATIVE_WIFI 30 |
| #define HTT_TX_HDR_SIZE_802_11_RAW 36 |
| #define HTT_TX_HDR_SIZE_ETHERNET 14 |
| |
| #define HTT_TX_HDR_SIZE_OUTER_HDR_MAX HTT_TX_HDR_SIZE_802_11_RAW |
| A_COMPILE_TIME_ASSERT( |
| htt_encap_hdr_size_max_check_nwifi, |
| HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= HTT_TX_HDR_SIZE_NATIVE_WIFI); |
| A_COMPILE_TIME_ASSERT( |
| htt_encap_hdr_size_max_check_enet, |
| HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= HTT_TX_HDR_SIZE_ETHERNET); |
| |
| #define HTT_HL_TX_HDR_SIZE_IP 1600 /* also include payload */ |
| #define HTT_LL_TX_HDR_SIZE_IP 16 /* up to the end of UDP header for IPv4 case */ |
| |
| #define HTT_TX_HDR_SIZE_802_1Q 4 |
| #define HTT_TX_HDR_SIZE_LLC_SNAP 8 |
| |
| |
| #define HTT_COMMON_TX_FRM_HDR_LEN \ |
| (HTT_TX_HDR_SIZE_OUTER_HDR_MAX + \ |
| HTT_TX_HDR_SIZE_802_1Q + \ |
| HTT_TX_HDR_SIZE_LLC_SNAP) |
| |
| #define HTT_HL_TX_FRM_HDR_LEN \ |
| (HTT_COMMON_TX_FRM_HDR_LEN + HTT_HL_TX_HDR_SIZE_IP) |
| |
| #define HTT_LL_TX_FRM_HDR_LEN \ |
| (HTT_COMMON_TX_FRM_HDR_LEN + HTT_LL_TX_HDR_SIZE_IP) |
| |
| #define HTT_TX_DESC_LEN sizeof(struct htt_tx_msdu_desc_t) |
| |
| /* dword 0 */ |
| #define HTT_TX_DESC_PKT_SUBTYPE_OFFSET_BYTES 0 |
| #define HTT_TX_DESC_PKT_SUBTYPE_OFFSET_DWORD 0 |
| #define HTT_TX_DESC_PKT_SUBTYPE_M 0x00001f00 |
| #define HTT_TX_DESC_PKT_SUBTYPE_S 8 |
| |
| #define HTT_TX_DESC_NO_ENCRYPT_OFFSET_BYTES 0 |
| #define HTT_TX_DESC_NO_ENCRYPT_OFFSET_DWORD 0 |
| #define HTT_TX_DESC_NO_ENCRYPT_M 0x00000400 |
| #define HTT_TX_DESC_NO_ENCRYPT_S 10 |
| |
| #define HTT_TX_DESC_PKT_TYPE_OFFSET_BYTES 0 |
| #define HTT_TX_DESC_PKT_TYPE_OFFSET_DWORD 0 |
| #define HTT_TX_DESC_PKT_TYPE_M 0x0000e000 |
| #define HTT_TX_DESC_PKT_TYPE_S 13 |
| |
| #define HTT_TX_DESC_VDEV_ID_OFFSET_BYTES 0 |
| #define HTT_TX_DESC_VDEV_ID_OFFSET_DWORD 0 |
| #define HTT_TX_DESC_VDEV_ID_M 0x003f0000 |
| #define HTT_TX_DESC_VDEV_ID_S 16 |
| |
| #define HTT_TX_DESC_EXT_TID_OFFSET_BYTES 0 |
| #define HTT_TX_DESC_EXT_TID_OFFSET_DWORD 0 |
| #define HTT_TX_DESC_EXT_TID_M 0x07c00000 |
| #define HTT_TX_DESC_EXT_TID_S 22 |
| |
| #define HTT_TX_DESC_POSTPONED_OFFSET_BYTES 0 |
| #define HTT_TX_DESC_POSTPONED_OFFSET_DWORD 0 |
| #define HTT_TX_DESC_POSTPONED_M 0x08000000 |
| #define HTT_TX_DESC_POSTPONED_S 27 |
| |
| #define HTT_TX_DESC_CKSUM_OFFLOAD_OFFSET_BYTES 0 |
| #define HTT_TX_DESC_CKSUM_OFFLOAD_OFFSET_DWORD 0 |
| #define HTT_TX_DESC_CKSUM_OFFLOAD_M 0x60000000 |
| #define HTT_TX_DESC_CKSUM_OFFLOAD_S 29 |
| |
| #define HTT_TX_DESC_TX_COMP_OFFSET_BYTES 0 |
| #define HTT_TX_DESC_TX_COMP_OFFSET_DWORD 0 |
| #define HTT_TX_DESC_TX_COMP_M 0x80000000 |
| #define HTT_TX_DESC_TX_COMP_S 31 |
| |
| /* dword 1 */ |
| #define HTT_TX_DESC_FRM_LEN_OFFSET_BYTES 4 |
| #define HTT_TX_DESC_FRM_LEN_OFFSET_DWORD 1 |
| #define HTT_TX_DESC_FRM_LEN_M 0x0000ffff |
| #define HTT_TX_DESC_FRM_LEN_S 0 |
| |
| #define HTT_TX_DESC_FRM_ID_OFFSET_BYTES 4 |
| #define HTT_TX_DESC_FRM_ID_OFFSET_DWORD 1 |
| #define HTT_TX_DESC_FRM_ID_M 0xffff0000 |
| #define HTT_TX_DESC_FRM_ID_S 16 |
| |
| /* dword 2 */ |
| #define HTT_TX_DESC_FRAGS_DESC_PADDR_OFFSET_BYTES 8 |
| #define HTT_TX_DESC_FRAGS_DESC_PADDR_OFFSET_DWORD 2 |
| /* for systems using 64-bit format for bus addresses */ |
| #define HTT_TX_DESC_FRAGS_DESC_PADDR_HI_M 0xffffffff |
| #define HTT_TX_DESC_FRAGS_DESC_PADDR_HI_S 0 |
| #define HTT_TX_DESC_FRAGS_DESC_PADDR_LO_M 0xffffffff |
| #define HTT_TX_DESC_FRAGS_DESC_PADDR_LO_S 0 |
| /* for systems using 32-bit format for bus addresses */ |
| #define HTT_TX_DESC_FRAGS_DESC_PADDR_M 0xffffffff |
| #define HTT_TX_DESC_FRAGS_DESC_PADDR_S 0 |
| |
| /* dword 3 */ |
| #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 16 |
| #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 12 |
| #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_64 \ |
| (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 >> 2) |
| #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_32 \ |
| (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 >> 2) |
| |
| #if HTT_PADDR64 |
| #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 |
| #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD HTT_TX_DESC_PEER_ID_OFFSET_DWORD_64 |
| #else |
| #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 |
| #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD HTT_TX_DESC_PEER_ID_OFFSET_DWORD_32 |
| #endif |
| |
| #define HTT_TX_DESC_PEER_ID_M 0x0000ffff |
| #define HTT_TX_DESC_PEER_ID_S 0 |
| /* |
| * TEMPORARY: |
| * The original definitions for the PEER_ID fields contained typos |
| * (with _DESC_PADDR appended to this PEER_ID field name). |
| * Retain deprecated original names for PEER_ID fields until all code that |
| * refers to them has been updated. |
| */ |
| #define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_BYTES \ |
| HTT_TX_DESC_PEER_ID_OFFSET_BYTES |
| #define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_DWORD \ |
| HTT_TX_DESC_PEER_ID_OFFSET_DWORD |
| #define HTT_TX_DESC_PEERID_DESC_PADDR_M \ |
| HTT_TX_DESC_PEER_ID_M |
| #define HTT_TX_DESC_PEERID_DESC_PADDR_S \ |
| HTT_TX_DESC_PEER_ID_S |
| |
| #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 16 // to dword with chan freq |
| #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 12 // to dword with chan freq |
| #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_64 \ |
| (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 >> 2) |
| #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_32 \ |
| (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 >> 2) |
| |
| #if HTT_PADDR64 |
| #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 |
| #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_64 |
| #else |
| #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 |
| #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_32 |
| #endif |
| |
| #define HTT_TX_DESC_CHAN_FREQ_M 0xffff0000 |
| #define HTT_TX_DESC_CHAN_FREQ_S 16 |
| |
| #define HTT_TX_DESC_PKT_SUBTYPE_GET(_var) \ |
| (((_var) & HTT_TX_DESC_PKT_SUBTYPE_M) >> HTT_TX_DESC_PKT_SUBTYPE_S) |
| #define HTT_TX_DESC_PKT_SUBTYPE_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_SUBTYPE, _val); \ |
| ((_var) |= ((_val) << HTT_TX_DESC_PKT_SUBTYPE_S)); \ |
| } while (0) |
| |
| #define HTT_TX_DESC_NO_ENCRYPT_GET(_var) \ |
| (((_var) & HTT_TX_DESC_NO_ENCRYPT_M) >> HTT_TX_DESC_NO_ENCRYPT_S) |
| #define HTT_TX_DESC_NO_ENCRYPT_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_DESC_NO_ENCRYPT, _val); \ |
| ((_var) |= ((_val) << HTT_TX_DESC_NO_ENCRYPT_S)); \ |
| } while (0) |
| |
| #define HTT_TX_DESC_PKT_TYPE_GET(_var) \ |
| (((_var) & HTT_TX_DESC_PKT_TYPE_M) >> HTT_TX_DESC_PKT_TYPE_S) |
| #define HTT_TX_DESC_PKT_TYPE_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_TYPE, _val); \ |
| ((_var) |= ((_val) << HTT_TX_DESC_PKT_TYPE_S)); \ |
| } while (0) |
| |
| #define HTT_TX_DESC_VDEV_ID_GET(_var) \ |
| (((_var) & HTT_TX_DESC_VDEV_ID_M) >> HTT_TX_DESC_VDEV_ID_S) |
| #define HTT_TX_DESC_VDEV_ID_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_DESC_VDEV_ID, _val); \ |
| ((_var) |= ((_val) << HTT_TX_DESC_VDEV_ID_S)); \ |
| } while (0) |
| |
| #define HTT_TX_DESC_EXT_TID_GET(_var) \ |
| (((_var) & HTT_TX_DESC_EXT_TID_M) >> HTT_TX_DESC_EXT_TID_S) |
| #define HTT_TX_DESC_EXT_TID_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_DESC_EXT_TID, _val); \ |
| ((_var) |= ((_val) << HTT_TX_DESC_EXT_TID_S)); \ |
| } while (0) |
| |
| #define HTT_TX_DESC_POSTPONED_GET(_var) \ |
| (((_var) & HTT_TX_DESC_POSTPONED_M) >> HTT_TX_DESC_POSTPONED_S) |
| #define HTT_TX_DESC_POSTPONED_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_DESC_POSTPONED, _val); \ |
| ((_var) |= ((_val) << HTT_TX_DESC_POSTPONED_S)); \ |
| } while (0) |
| |
| #define HTT_TX_DESC_FRM_LEN_GET(_var) \ |
| (((_var) & HTT_TX_DESC_FRM_LEN_M) >> HTT_TX_DESC_FRM_LEN_S) |
| #define HTT_TX_DESC_FRM_LEN_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_LEN, _val); \ |
| ((_var) |= ((_val) << HTT_TX_DESC_FRM_LEN_S)); \ |
| } while (0) |
| |
| #define HTT_TX_DESC_FRM_ID_GET(_var) \ |
| (((_var) & HTT_TX_DESC_FRM_ID_M) >> HTT_TX_DESC_FRM_ID_S) |
| #define HTT_TX_DESC_FRM_ID_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_ID, _val); \ |
| ((_var) |= ((_val) << HTT_TX_DESC_FRM_ID_S)); \ |
| } while (0) |
| |
| #define HTT_TX_DESC_CKSUM_OFFLOAD_GET(_var) \ |
| (((_var) & HTT_TX_DESC_CKSUM_OFFLOAD_M) >> HTT_TX_DESC_CKSUM_OFFLOAD_S) |
| #define HTT_TX_DESC_CKSUM_OFFLOAD_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_DESC_CKSUM_OFFLOAD, _val); \ |
| ((_var) |= ((_val) << HTT_TX_DESC_CKSUM_OFFLOAD_S)); \ |
| } while (0) |
| |
| #define HTT_TX_DESC_TX_COMP_GET(_var) \ |
| (((_var) & HTT_TX_DESC_TX_COMP_M) >> HTT_TX_DESC_TX_COMP_S) |
| #define HTT_TX_DESC_TX_COMP_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_DESC_TX_COMP, _val); \ |
| ((_var) |= ((_val) << HTT_TX_DESC_TX_COMP_S)); \ |
| } while (0) |
| |
| #define HTT_TX_DESC_PEER_ID_GET(_var) \ |
| (((_var) & HTT_TX_DESC_PEER_ID_M) >> HTT_TX_DESC_PEER_ID_S) |
| #define HTT_TX_DESC_PEER_ID_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_DESC_PEER_ID, _val); \ |
| ((_var) |= ((_val) << HTT_TX_DESC_PEER_ID_S)); \ |
| } while (0) |
| |
| #define HTT_TX_DESC_CHAN_FREQ_GET(_var) \ |
| (((_var) & HTT_TX_DESC_CHAN_FREQ_M) >> HTT_TX_DESC_CHAN_FREQ_S) |
| #define HTT_TX_DESC_CHAN_FREQ_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_DESC_CHAN_FREQ, _val); \ |
| ((_var) |= ((_val) << HTT_TX_DESC_CHAN_FREQ_S)); \ |
| } while (0) |
| |
| |
| /* enums used in the HTT tx MSDU extension descriptor */ |
| enum { |
| htt_tx_guard_interval_regular = 0, |
| htt_tx_guard_interval_short = 1, |
| }; |
| |
| enum { |
| htt_tx_preamble_type_ofdm = 0, |
| htt_tx_preamble_type_cck = 1, |
| htt_tx_preamble_type_ht = 2, |
| htt_tx_preamble_type_vht = 3, |
| }; |
| |
| enum { |
| htt_tx_bandwidth_5MHz = 0, |
| htt_tx_bandwidth_10MHz = 1, |
| htt_tx_bandwidth_20MHz = 2, |
| htt_tx_bandwidth_40MHz = 3, |
| htt_tx_bandwidth_80MHz = 4, |
| htt_tx_bandwidth_160MHz = 5, /* includes 80+80 */ |
| }; |
| |
| /** |
| * @brief HTT tx MSDU extension descriptor |
| * @details |
| * If the target supports HTT tx MSDU extension descriptors, the host has |
| * the option of appending the following struct following the regular |
| * HTT tx MSDU descriptor (and setting the "extension" flag in the regular |
| * HTT tx MSDU descriptor, to show that the extension descriptor is present). |
| * The HTT tx MSDU extension descriptors allows the host to provide detailed |
| * tx specs for each frame. |
| */ |
| PREPACK struct htt_tx_msdu_desc_ext_t { |
| /* DWORD 0: flags */ |
| A_UINT32 |
| valid_pwr: 1, /* bit 0: if set, tx pwr spec is valid */ |
| valid_mcs_mask: 1, /* bit 1: if set, tx MCS mask spec is valid */ |
| valid_nss_mask: 1, /* bit 2: if set, tx Nss mask spec is valid */ |
| valid_guard_interval: 1, /* bit 3: if set, tx guard intv spec is valid*/ |
| valid_preamble_type_mask: 1, /* 4: if set, tx preamble mask is valid */ |
| valid_chainmask: 1, /* bit 5: if set, tx chainmask spec is valid */ |
| valid_retries: 1, /* bit 6: if set, tx retries spec is valid */ |
| valid_bandwidth: 1, /* bit 7: if set, tx bandwidth spec is valid */ |
| valid_expire_tsf: 1, /* bit 8: if set, tx expire TSF spec is valid*/ |
| is_dsrc: 1, /* bit 9: if set, MSDU is a DSRC frame */ |
| reserved0_31_7: 22; /* bits 31:10 - unused, set to 0x0 */ |
| |
| /* DWORD 1: tx power, tx rate, tx BW */ |
| A_UINT32 |
| /* pwr - |
| * Specify what power the tx frame needs to be transmitted at. |
| * The power a signed (two's complement) value is in units of 0.5 dBm. |
| * The value needs to be appropriately sign-extended when extracting |
| * the value from the message and storing it in a variable that is |
| * larger than A_INT8. (The HTT_TX_MSDU_EXT_DESC_FLAG_PWR_GET macro |
| * automatically handles this sign-extension.) |
| * If the transmission uses multiple tx chains, this power spec is |
| * the total transmit power, assuming incoherent combination of |
| * per-chain power to produce the total power. |
| */ |
| pwr: 8, |
| |
| /* mcs_mask - |
| * Specify the allowable values for MCS index (modulation and coding) |
| * to use for transmitting the frame. |
| * |
| * For HT / VHT preamble types, this mask directly corresponds to |
| * the HT or VHT MCS indices that are allowed. For each bit N set |
| * within the mask, MCS index N is allowed for transmitting the frame. |
| * For legacy CCK and OFDM rates, separate bits are provided for CCK |
| * rates versus OFDM rates, so the host has the option of specifying |
| * that the target must transmit the frame with CCK or OFDM rates |
| * (not HT or VHT), but leaving the decision to the target whether |
| * to use CCK or OFDM. |
| * |
| * For CCK and OFDM, the bits within this mask are interpreted as |
| * follows: |
| * bit 0 -> CCK 1 Mbps rate is allowed |
| * bit 1 -> CCK 2 Mbps rate is allowed |
| * bit 2 -> CCK 5.5 Mbps rate is allowed |
| * bit 3 -> CCK 11 Mbps rate is allowed |
| * bit 4 -> OFDM BPSK modulation, 1/2 coding rate is allowed |
| * bit 5 -> OFDM BPSK modulation, 3/4 coding rate is allowed |
| * bit 6 -> OFDM QPSK modulation, 1/2 coding rate is allowed |
| * bit 7 -> OFDM QPSK modulation, 3/4 coding rate is allowed |
| * bit 8 -> OFDM 16-QAM modulation, 1/2 coding rate is allowed |
| * bit 9 -> OFDM 16-QAM modulation, 3/4 coding rate is allowed |
| * bit 10 -> OFDM 64-QAM modulation, 2/3 coding rate is allowed |
| * bit 11 -> OFDM 64-QAM modulation, 3/4 coding rate is allowed |
| * |
| * The MCS index specification needs to be compatible with the |
| * bandwidth mask specification. For example, a MCS index == 9 |
| * specification is inconsistent with a preamble type == VHT, |
| * Nss == 1, and channel bandwidth == 20 MHz. |
| * |
| * Furthermore, the host has only a limited ability to specify to |
| * the target to select from HT + legacy rates, or VHT + legacy rates, |
| * since this mcs_mask can specify either HT/VHT rates or legacy rates. |
| */ |
| mcs_mask: 12, |
| |
| /* nss_mask - |
| * Specify which numbers of spatial streams (MIMO factor) are permitted. |
| * Each bit in this mask corresponds to a Nss value: |
| * bit 0: if set, Nss = 1 (non-MIMO) is permitted |
| * bit 1: if set, Nss = 2 (2x2 MIMO) is permitted |
| * bit 2: if set, Nss = 3 (3x3 MIMO) is permitted |
| * bit 3: if set, Nss = 4 (4x4 MIMO) is permitted |
| * The values in the Nss mask must be suitable for the recipient, e.g. |
| * a value of 0x4 (Nss = 3) cannot be specified for a tx frame to a |
| * recipient which only supports 2x2 MIMO. |
| */ |
| nss_mask: 4, |
| |
| /* guard_interval - |
| * Specify a htt_tx_guard_interval enum value to indicate whether |
| * the transmission should use a regular guard interval or a |
| * short guard interval. |
| */ |
| guard_interval: 1, |
| |
| /* preamble_type_mask - |
| * Specify which preamble types (CCK, OFDM, HT, VHT) the target |
| * may choose from for transmitting this frame. |
| * The bits in this mask correspond to the values in the |
| * htt_tx_preamble_type enum. For example, to allow the target |
| * to transmit the frame as either CCK or OFDM, this field would |
| * be set to |
| * (1 << htt_tx_preamble_type_ofdm) | |
| * (1 << htt_tx_preamble_type_cck) |
| */ |
| preamble_type_mask: 4, |
| |
| reserved1_31_29: 3; /* unused, set to 0x0 */ |
| |
| /* DWORD 2: tx chain mask, tx retries */ |
| A_UINT32 |
| /* chain_mask - specify which chains to transmit from */ |
| chain_mask: 4, |
| |
| /* retry_limit - |
| * Specify the maximum number of transmissions, including the |
| * initial transmission, to attempt before giving up if no ack |
| * is received. |
| * If the tx rate is specified, then all retries shall use the |
| * same rate as the initial transmission. |
| * If no tx rate is specified, the target can choose whether to |
| * retain the original rate during the retransmissions, or to |
| * fall back to a more robust rate. |
| */ |
| retry_limit: 4, |
| |
| /* bandwidth_mask - |
| * Specify what channel widths may be used for the transmission. |
| * A value of zero indicates "don't care" - the target may choose |
| * the transmission bandwidth. |
| * The bits within this mask correspond to the htt_tx_bandwidth |
| * enum values - bit 0 is for 5 MHz, bit 1 is for 10 MHz, etc. |
| * The bandwidth_mask must be consistent with the preamble_type_mask |
| * and mcs_mask specs, if they are provided. For example, 80 MHz and |
| * 160 MHz can only be enabled in the mask if preamble_type == VHT. |
| */ |
| bandwidth_mask: 6, |
| |
| reserved2_31_14: 18; /* unused, set to 0x0 */ |
| |
| /* DWORD 3: tx expiry time (TSF) LSBs */ |
| A_UINT32 expire_tsf_lo; |
| |
| /* DWORD 4: tx expiry time (TSF) MSBs */ |
| A_UINT32 expire_tsf_hi; |
| |
| A_UINT32 reserved_for_future_expansion_set_to_zero[3]; |
| } POSTPACK; |
| |
| /* DWORD 0 */ |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M 0x00000001 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S 0 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_M 0x00000002 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S 1 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_NSS_MASK_M 0x00000004 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_NSS_MASK_S 2 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_M 0x00000008 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S 3 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_M 0x00000010 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S 4 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_M 0x00000020 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S 5 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_M 0x00000040 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S 6 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_M 0x00000080 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S 7 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_M 0x00000100 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S 8 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_M 0x00000200 |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S 9 |
| |
| /* DWORD 1 */ |
| #define HTT_TX_MSDU_EXT_DESC_PWR_M 0x000000ff |
| #define HTT_TX_MSDU_EXT_DESC_PWR_S 0 |
| #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_M 0x000fff00 |
| #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_S 8 |
| #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_M 0x00f00000 |
| #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_S 20 |
| #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_M 0x01000000 |
| #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S 24 |
| #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_M 0x1c000000 |
| #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S 25 |
| |
| /* DWORD 2 */ |
| #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_M 0x0000000f |
| #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S 0 |
| #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_M 0x000000f0 |
| #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S 4 |
| #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_M 0x00003f00 |
| #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S 8 |
| |
| |
| /* DWORD 0 */ |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S) |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR, _val); \ |
| ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S)); \ |
| } while (0) |
| |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S) |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK, _val); \ |
| ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S)); \ |
| } while (0) |
| |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S) |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL( \ |
| HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL, _val); \ |
| ((_var) |= ((_val) \ |
| << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S)); \ |
| } while (0) |
| |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S) |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL( \ |
| HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK, _val); \ |
| ((_var) |= ((_val) \ |
| << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S)); \ |
| } while (0) |
| |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S) |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK, _val); \ |
| ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S)); \ |
| } while (0) |
| |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S) |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES, _val); \ |
| ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S)); \ |
| } while (0) |
| |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S) |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH, _val); \ |
| ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S)); \ |
| } while (0) |
| |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S) |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME, _val); \ |
| ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S));\ |
| } while (0) |
| |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S) |
| #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC, _val); \ |
| ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S)); \ |
| } while (0) |
| |
| |
| /* DWORD 1 */ |
| #define HTT_TX_MSDU_EXT_DESC_PWR_GET_BASE(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_PWR_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_PWR_S) |
| #define HTT_TX_MSDU_EXT_DESC_PWR_GET(_var) \ |
| (HTT_TX_MSDU_EXT_DESC_PWR_GET_BASE(_var) | \ |
| HTT_SIGN_BIT_EXTENSION_MASK(_var, HTT_TX_MSDU_EXT_DESC_PWR)) |
| #define HTT_TX_MSDU_EXT_DESC_PWR_SET(_var, _val) \ |
| ((_var) |= (((_val) << HTT_TX_MSDU_EXT_DESC_PWR_S)) & \ |
| HTT_TX_MSDU_EXT_DESC_PWR_M) |
| |
| #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_MCS_MASK_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_MCS_MASK_S) |
| #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_MCS_MASK, _val); \ |
| ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_MCS_MASK_S)); \ |
| } while (0) |
| |
| #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_NSS_MASK_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_NSS_MASK_S) |
| #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_NSS_MASK, _val); \ |
| ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_NSS_MASK_S)); \ |
| } while (0) |
| |
| #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S) |
| #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL, _val); \ |
| ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S)); \ |
| } while (0) |
| |
| #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S) |
| #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK, _val); \ |
| ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S)); \ |
| } while (0) |
| |
| |
| /* DWORD 2 */ |
| #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S) |
| #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_CHAIN_MASK, _val); \ |
| ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S)); \ |
| } while (0) |
| |
| #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S) |
| #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT, _val); \ |
| ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S)); \ |
| } while (0) |
| |
| #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_GET(_var) \ |
| (((_var) & HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_M) >> \ |
| HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S) |
| #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK, _val); \ |
| ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S)); \ |
| } while (0) |
| |
| |
| /** |
| * @brief MAC DMA rx ring setup specification |
| * @details |
| * To allow for dynamic rx ring reconfiguration and to avoid race |
| * conditions, the host SW never directly programs the MAC DMA rx ring(s) |
| * it uses. Instead, it sends this message to the target, indicating how |
| * the rx ring used by the host should be set up and maintained. |
| * The message consists of a 4-octet header followed by 1 or 2 rx ring setup |
| * specifications. |
| * |
| * |31 16|15 8|7 0| |
| * |---------------------------------------------------------------| |
| * header: | reserved | num rings | msg type | |
| * |---------------------------------------------------------------| |
| * payload 1: | FW_IDX shadow register physical address (bits 31:0) | |
| #if HTT_PADDR64 |
| * | FW_IDX shadow register physical address (bits 63:32) | |
| #endif |
| * |---------------------------------------------------------------| |
| * | rx ring base physical address (bits 31:0) | |
| #if HTT_PADDR64 |
| * | rx ring base physical address (bits 63:32) | |
| #endif |
| * |---------------------------------------------------------------| |
| * | rx ring buffer size | rx ring length | |
| * |---------------------------------------------------------------| |
| * | FW_IDX initial value | enabled flags | |
| * |---------------------------------------------------------------| |
| * | MSDU payload offset | 802.11 header offset | |
| * |---------------------------------------------------------------| |
| * | PPDU end offset | PPDU start offset | |
| * |---------------------------------------------------------------| |
| * | MPDU end offset | MPDU start offset | |
| * |---------------------------------------------------------------| |
| * | MSDU end offset | MSDU start offset | |
| * |---------------------------------------------------------------| |
| * | frag info offset | rx attention offset | |
| * |---------------------------------------------------------------| |
| * payload 2, if present, has the same format as payload 1 |
| * Header fields: |
| * - MSG_TYPE |
| * Bits 7:0 |
| * Purpose: identifies this as an rx ring configuration message |
| * Value: 0x2 |
| * - NUM_RINGS |
| * Bits 15:8 |
| * Purpose: indicates whether the host is setting up one rx ring or two |
| * Value: 1 or 2 |
| * Payload: |
| * for systems using 64-bit format for bus addresses: |
| * - IDX_SHADOW_REG_PADDR_LO |
| * Bits 31:0 |
| * Value: lower 4 bytes of physical address of the host's |
| * FW_IDX shadow register |
| * - IDX_SHADOW_REG_PADDR_HI |
| * Bits 31:0 |
| * Value: upper 4 bytes of physical address of the host's |
| * FW_IDX shadow register |
| * - RING_BASE_PADDR_LO |
| * Bits 31:0 |
| * Value: lower 4 bytes of physical address of the host's rx ring |
| * - RING_BASE_PADDR_HI |
| * Bits 31:0 |
| * Value: uppper 4 bytes of physical address of the host's rx ring |
| * for systems using 32-bit format for bus addresses: |
| * - IDX_SHADOW_REG_PADDR |
| * Bits 31:0 |
| * Value: physical address of the host's FW_IDX shadow register |
| * - RING_BASE_PADDR |
| * Bits 31:0 |
| * Value: physical address of the host's rx ring |
| * - RING_LEN |
| * Bits 15:0 |
| * Value: number of elements in the rx ring |
| * - RING_BUF_SZ |
| * Bits 31:16 |
| * Value: size of the buffers referenced by the rx ring, in byte units |
| * - ENABLED_FLAGS |
| * Bits 15:0 |
| * Value: 1-bit flags to show whether different rx fields are enabled |
| * bit 0: 802.11 header enabled (1) or disabled (0) |
| * bit 1: MSDU payload enabled (1) or disabled (0) |
| * bit 2: PPDU start enabled (1) or disabled (0) |
| * bit 3: PPDU end enabled (1) or disabled (0) |
| * bit 4: MPDU start enabled (1) or disabled (0) |
| * bit 5: MPDU end enabled (1) or disabled (0) |
| * bit 6: MSDU start enabled (1) or disabled (0) |
| * bit 7: MSDU end enabled (1) or disabled (0) |
| * bit 8: rx attention enabled (1) or disabled (0) |
| * bit 9: frag info enabled (1) or disabled (0) |
| * bit 10: unicast rx enabled (1) or disabled (0) |
| * bit 11: multicast rx enabled (1) or disabled (0) |
| * bit 12: ctrl rx enabled (1) or disabled (0) |
| * bit 13: mgmt rx enabled (1) or disabled (0) |
| * bit 14: null rx enabled (1) or disabled (0) |
| * bit 15: phy data rx enabled (1) or disabled (0) |
| * - IDX_INIT_VAL |
| * Bits 31:16 |
| * Purpose: Specify the initial value for the FW_IDX. |
| * Value: the number of buffers initially present in the host's rx ring |
| * - OFFSET_802_11_HDR |
| * Bits 15:0 |
| * Value: offset in QUAD-bytes of 802.11 header from the buffer start |
| * - OFFSET_MSDU_PAYLOAD |
| * Bits 31:16 |
| * Value: offset in QUAD-bytes of MSDU payload from the buffer start |
| * - OFFSET_PPDU_START |
| * Bits 15:0 |
| * Value: offset in QUAD-bytes of PPDU start rx desc from the buffer start |
| * - OFFSET_PPDU_END |
| * Bits 31:16 |
| * Value: offset in QUAD-bytes of PPDU end rx desc from the buffer start |
| * - OFFSET_MPDU_START |
| * Bits 15:0 |
| * Value: offset in QUAD-bytes of MPDU start rx desc from the buffer start |
| * - OFFSET_MPDU_END |
| * Bits 31:16 |
| * Value: offset in QUAD-bytes of MPDU end rx desc from the buffer start |
| * - OFFSET_MSDU_START |
| * Bits 15:0 |
| * Value: offset in QUAD-bytes of MSDU start rx desc from the buffer start |
| * - OFFSET_MSDU_END |
| * Bits 31:16 |
| * Value: offset in QUAD-bytes of MSDU end rx desc from the buffer start |
| * - OFFSET_RX_ATTN |
| * Bits 15:0 |
| * Value: offset in QUAD-bytes of rx attention word from the buffer start |
| * - OFFSET_FRAG_INFO |
| * Bits 31:16 |
| * Value: offset in QUAD-bytes of frag info table |
| */ |
| /* header fields */ |
| #define HTT_RX_RING_CFG_NUM_RINGS_M 0xff00 |
| #define HTT_RX_RING_CFG_NUM_RINGS_S 8 |
| |
| /* payload fields */ |
| /* for systems using a 64-bit format for bus addresses */ |
| #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_M 0xffffffff |
| #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_S 0 |
| #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_M 0xffffffff |
| #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_S 0 |
| #define HTT_RX_RING_CFG_BASE_PADDR_HI_M 0xffffffff |
| #define HTT_RX_RING_CFG_BASE_PADDR_HI_S 0 |
| #define HTT_RX_RING_CFG_BASE_PADDR_LO_M 0xffffffff |
| #define HTT_RX_RING_CFG_BASE_PADDR_LO_S 0 |
| |
| /* for systems using a 32-bit format for bus addresses */ |
| #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_M 0xffffffff |
| #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_S 0 |
| #define HTT_RX_RING_CFG_BASE_PADDR_M 0xffffffff |
| #define HTT_RX_RING_CFG_BASE_PADDR_S 0 |
| |
| #define HTT_RX_RING_CFG_LEN_M 0xffff |
| #define HTT_RX_RING_CFG_LEN_S 0 |
| #define HTT_RX_RING_CFG_BUF_SZ_M 0xffff0000 |
| #define HTT_RX_RING_CFG_BUF_SZ_S 16 |
| #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_M 0x1 |
| #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_S 0 |
| #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_M 0x2 |
| #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S 1 |
| #define HTT_RX_RING_CFG_ENABLED_PPDU_START_M 0x4 |
| #define HTT_RX_RING_CFG_ENABLED_PPDU_START_S 2 |
| #define HTT_RX_RING_CFG_ENABLED_PPDU_END_M 0x8 |
| #define HTT_RX_RING_CFG_ENABLED_PPDU_END_S 3 |
| #define HTT_RX_RING_CFG_ENABLED_MPDU_START_M 0x10 |
| #define HTT_RX_RING_CFG_ENABLED_MPDU_START_S 4 |
| #define HTT_RX_RING_CFG_ENABLED_MPDU_END_M 0x20 |
| #define HTT_RX_RING_CFG_ENABLED_MPDU_END_S 5 |
| #define HTT_RX_RING_CFG_ENABLED_MSDU_START_M 0x40 |
| #define HTT_RX_RING_CFG_ENABLED_MSDU_START_S 6 |
| #define HTT_RX_RING_CFG_ENABLED_MSDU_END_M 0x80 |
| #define HTT_RX_RING_CFG_ENABLED_MSDU_END_S 7 |
| #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_M 0x100 |
| #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_S 8 |
| #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_M 0x200 |
| #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S 9 |
| #define HTT_RX_RING_CFG_ENABLED_UCAST_M 0x400 |
| #define HTT_RX_RING_CFG_ENABLED_UCAST_S 10 |
| #define HTT_RX_RING_CFG_ENABLED_MCAST_M 0x800 |
| #define HTT_RX_RING_CFG_ENABLED_MCAST_S 11 |
| #define HTT_RX_RING_CFG_ENABLED_CTRL_M 0x1000 |
| #define HTT_RX_RING_CFG_ENABLED_CTRL_S 12 |
| #define HTT_RX_RING_CFG_ENABLED_MGMT_M 0x2000 |
| #define HTT_RX_RING_CFG_ENABLED_MGMT_S 13 |
| #define HTT_RX_RING_CFG_ENABLED_NULL_M 0x4000 |
| #define HTT_RX_RING_CFG_ENABLED_NULL_S 14 |
| #define HTT_RX_RING_CFG_ENABLED_PHY_M 0x8000 |
| #define HTT_RX_RING_CFG_ENABLED_PHY_S 15 |
| #define HTT_RX_RING_CFG_IDX_INIT_VAL_M 0xffff0000 |
| #define HTT_RX_RING_CFG_IDX_INIT_VAL_S 16 |
| #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_M 0xffff |
| #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_S 0 |
| #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_M 0xffff0000 |
| #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S 16 |
| #define HTT_RX_RING_CFG_OFFSET_PPDU_START_M 0xffff |
| #define HTT_RX_RING_CFG_OFFSET_PPDU_START_S 0 |
| #define HTT_RX_RING_CFG_OFFSET_PPDU_END_M 0xffff0000 |
| #define HTT_RX_RING_CFG_OFFSET_PPDU_END_S 16 |
| #define HTT_RX_RING_CFG_OFFSET_MPDU_START_M 0xffff |
| #define HTT_RX_RING_CFG_OFFSET_MPDU_START_S 0 |
| #define HTT_RX_RING_CFG_OFFSET_MPDU_END_M 0xffff0000 |
| #define HTT_RX_RING_CFG_OFFSET_MPDU_END_S 16 |
| #define HTT_RX_RING_CFG_OFFSET_MSDU_START_M 0xffff |
| #define HTT_RX_RING_CFG_OFFSET_MSDU_START_S 0 |
| #define HTT_RX_RING_CFG_OFFSET_MSDU_END_M 0xffff0000 |
| #define HTT_RX_RING_CFG_OFFSET_MSDU_END_S 16 |
| #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_M 0xffff |
| #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_S 0 |
| #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_M 0xffff0000 |
| #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S 16 |
| |
| #define HTT_RX_RING_CFG_HDR_BYTES 4 |
| #define HTT_RX_RING_CFG_PAYLD_BYTES_64 44 |
| #define HTT_RX_RING_CFG_PAYLD_BYTES_32 36 |
| #if HTT_PADDR64 |
| #define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_64 |
| #else |
| #define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_32 |
| #endif |
| #define HTT_RX_RING_CFG_BYTES(num_rings) \ |
| (HTT_RX_RING_CFG_HDR_BYTES + (num_rings) * HTT_RX_RING_CFG_PAYLD_BYTES) |
| |
| |
| #define HTT_RX_RING_CFG_NUM_RINGS_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_NUM_RINGS_M) >> HTT_RX_RING_CFG_NUM_RINGS_S) |
| #define HTT_RX_RING_CFG_NUM_RINGS_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_NUM_RINGS, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_NUM_RINGS_S)); \ |
| } while (0) |
| |
| /* degenerate case for 32-bit fields */ |
| #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_GET(_var) (_var) |
| #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_SET(_var, _val) (_var) = (_val) |
| #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_GET(_var) (_var) |
| #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_SET(_var, _val) (_var) = (_val) |
| #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_GET(_var) (_var) |
| #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_SET(_var, _val) (_var) = (_val) |
| |
| /* degenerate case for 32-bit fields */ |
| #define HTT_RX_RING_CFG_BASE_PADDR_HI_GET(_var) (_var) |
| #define HTT_RX_RING_CFG_BASE_PADDR_HI_SET(_var, _val) (_var) = (_val) |
| #define HTT_RX_RING_CFG_BASE_PADDR_LO_GET(_var) (_var) |
| #define HTT_RX_RING_CFG_BASE_PADDR_LO_SET(_var, _val) (_var) = (_val) |
| #define HTT_RX_RING_CFG_BASE_PADDR_GET(_var) (_var) |
| #define HTT_RX_RING_CFG_BASE_PADDR_SET(_var, _val) (_var) = (_val) |
| |
| #define HTT_RX_RING_CFG_LEN_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_LEN_M) >> HTT_RX_RING_CFG_LEN_S) |
| #define HTT_RX_RING_CFG_LEN_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_LEN, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_LEN_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_BUF_SZ_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_BUF_SZ_M) >> HTT_RX_RING_CFG_BUF_SZ_S) |
| #define HTT_RX_RING_CFG_BUF_SZ_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_BUF_SZ, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_BUF_SZ_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_IDX_INIT_VAL_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_IDX_INIT_VAL_M) >> \ |
| HTT_RX_RING_CFG_IDX_INIT_VAL_S) |
| #define HTT_RX_RING_CFG_IDX_INIT_VAL_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_IDX_INIT_VAL, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_IDX_INIT_VAL_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_802_11_HDR_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_802_11_HDR_S) |
| #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_802_11_HDR, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_802_11_HDR_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S) |
| #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_ENABLED_PPDU_START_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_START_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_PPDU_START_S) |
| #define HTT_RX_RING_CFG_ENABLED_PPDU_START_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_START, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_START_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_ENABLED_PPDU_END_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_END_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_PPDU_END_S) |
| #define HTT_RX_RING_CFG_ENABLED_PPDU_END_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_END, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_END_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_ENABLED_MPDU_START_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_START_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_MPDU_START_S) |
| #define HTT_RX_RING_CFG_ENABLED_MPDU_START_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_START, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_START_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_ENABLED_MPDU_END_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_END_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_MPDU_END_S) |
| #define HTT_RX_RING_CFG_ENABLED_MPDU_END_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_END, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_END_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_ENABLED_MSDU_START_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_START_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_MSDU_START_S) |
| #define HTT_RX_RING_CFG_ENABLED_MSDU_START_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_START, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_START_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_ENABLED_MSDU_END_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_END_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_MSDU_END_S) |
| #define HTT_RX_RING_CFG_ENABLED_MSDU_END_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_END, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_END_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_RX_ATTN_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_RX_ATTN_S) |
| #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_RX_ATTN, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_RX_ATTN_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_FRAG_INFO_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S) |
| #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_FRAG_INFO, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_ENABLED_UCAST_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_UCAST_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_UCAST_S) |
| #define HTT_RX_RING_CFG_ENABLED_UCAST_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_UCAST, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_UCAST_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_ENABLED_MCAST_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_MCAST_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_MCAST_S) |
| #define HTT_RX_RING_CFG_ENABLED_MCAST_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MCAST, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MCAST_S)); \ |
| } while (0) |
| #define HTT_RX_RING_CFG_ENABLED_CTRL_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_CTRL_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_CTRL_S) |
| #define HTT_RX_RING_CFG_ENABLED_CTRL_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_CTRL, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_CTRL_S)); \ |
| } while (0) |
| #define HTT_RX_RING_CFG_ENABLED_MGMT_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_MGMT_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_MGMT_S) |
| #define HTT_RX_RING_CFG_ENABLED_MGMT_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MGMT, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MGMT_S)); \ |
| } while (0) |
| #define HTT_RX_RING_CFG_ENABLED_NULL_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_NULL_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_NULL_S) |
| #define HTT_RX_RING_CFG_ENABLED_NULL_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_NULL, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_NULL_S)); \ |
| } while (0) |
| #define HTT_RX_RING_CFG_ENABLED_PHY_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_ENABLED_PHY_M) >> \ |
| HTT_RX_RING_CFG_ENABLED_PHY_S) |
| #define HTT_RX_RING_CFG_ENABLED_PHY_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PHY, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PHY_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_OFFSET_802_11_HDR_M) >> \ |
| HTT_RX_RING_CFG_OFFSET_802_11_HDR_S) |
| #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_802_11_HDR, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_802_11_HDR_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_M) >> \ |
| HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S) |
| #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_OFFSET_PPDU_START_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_START_M) >> \ |
| HTT_RX_RING_CFG_OFFSET_PPDU_START_S) |
| #define HTT_RX_RING_CFG_OFFSET_PPDU_START_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_START, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_START_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_OFFSET_PPDU_END_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_END_M) >> \ |
| HTT_RX_RING_CFG_OFFSET_PPDU_END_S) |
| #define HTT_RX_RING_CFG_OFFSET_PPDU_END_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_END, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_END_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_OFFSET_MPDU_START_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_START_M) >> \ |
| HTT_RX_RING_CFG_OFFSET_MPDU_START_S) |
| #define HTT_RX_RING_CFG_OFFSET_MPDU_START_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_START, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_START_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_OFFSET_MPDU_END_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_END_M) >> \ |
| HTT_RX_RING_CFG_OFFSET_MPDU_END_S) |
| #define HTT_RX_RING_CFG_OFFSET_MPDU_END_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_END, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_END_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_OFFSET_MSDU_START_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_START_M) >> \ |
| HTT_RX_RING_CFG_OFFSET_MSDU_START_S) |
| #define HTT_RX_RING_CFG_OFFSET_MSDU_START_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_START, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_START_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_OFFSET_MSDU_END_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_END_M) >> \ |
| HTT_RX_RING_CFG_OFFSET_MSDU_END_S) |
| #define HTT_RX_RING_CFG_OFFSET_MSDU_END_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_END, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_END_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_OFFSET_RX_ATTN_M) >> \ |
| HTT_RX_RING_CFG_OFFSET_RX_ATTN_S) |
| #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_RX_ATTN, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_RX_ATTN_S)); \ |
| } while (0) |
| |
| #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_GET(_var) \ |
| (((_var) & HTT_RX_RING_CFG_OFFSET_FRAG_INFO_M) >> \ |
| HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S) |
| #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_FRAG_INFO, _val); \ |
| ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S)); \ |
| } while (0) |
| |
| /** |
| * @brief host -> target FW statistics retrieve |
| * |
| * @details |
| * The following field definitions describe the format of the HTT host |
| * to target FW stats retrieve message. The message specifies the type of |
| * stats host wants to retrieve. |
| * |
| * |31 24|23 16|15 8|7 0| |
| * |-----------------------------------------------------------| |
| * | stats types request bitmask | msg type | |
| * |-----------------------------------------------------------| |
| * | stats types reset bitmask | reserved | |
| * |-----------------------------------------------------------| |
| * | stats type | config value | |
| * |-----------------------------------------------------------| |
| * | cookie LSBs | |
| * |-----------------------------------------------------------| |
| * | cookie MSBs | |
| * |-----------------------------------------------------------| |
| * Header fields: |
| * - MSG_TYPE |
| * Bits 7:0 |
| * Purpose: identifies this is a stats upload request message |
| * Value: 0x3 |
| * - UPLOAD_TYPES |
| * Bits 31:8 |
| * Purpose: identifies which types of FW statistics to upload |
| * Value: mask with bits set in positions defined by htt_dbg_stats_type |
| * - RESET_TYPES |
| * Bits 31:8 |
| * Purpose: identifies which types of FW statistics to reset |
| * Value: mask with bits set in positions defined by htt_dbg_stats_type |
| * - CFG_VAL |
| * Bits 23:0 |
| * Purpose: give an opaque configuration value to the specified stats type |
| * Value: stats-type specific configuration value |
| * if stats type == tx PPDU log, then CONFIG_VAL has the format: |
| * bits 7:0 - how many per-MPDU byte counts to include in a record |
| * bits 15:8 - how many per-MPDU MSDU counts to include in a record |
| * bits 23:16 - how many per-MSDU byte counts to include in a record |
| * - CFG_STAT_TYPE |
| * Bits 31:24 |
| * Purpose: specify which stats type (if any) the config value applies to |
| * Value: htt_dbg_stats_type value, or 0xff if the message doesn't have |
| * a valid configuration specification |
| * - COOKIE_LSBS |
| * Bits 31:0 |
| * Purpose: Provide a mechanism to match a target->host stats confirmation |
| * message with its preceding host->target stats request message. |
| * Value: LSBs of the opaque cookie specified by the host-side requestor |
| * - COOKIE_MSBS |
| * Bits 31:0 |
| * Purpose: Provide a mechanism to match a target->host stats confirmation |
| * message with its preceding host->target stats request message. |
| * Value: MSBs of the opaque cookie specified by the host-side requestor |
| */ |
| |
| #define HTT_H2T_STATS_REQ_MSG_SZ 20 /* bytes */ |
| |
| #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff |
| |
| #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_M 0xffffff00 |
| #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_S 8 |
| |
| #define HTT_H2T_STATS_REQ_RESET_TYPES_M 0xffffff00 |
| #define HTT_H2T_STATS_REQ_RESET_TYPES_S 8 |
| |
| #define HTT_H2T_STATS_REQ_CFG_VAL_M 0x00ffffff |
| #define HTT_H2T_STATS_REQ_CFG_VAL_S 0 |
| |
| #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_M 0xff000000 |
| #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S 24 |
| |
| #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_GET(_var) \ |
| (((_var) & HTT_H2T_STATS_REQ_UPLOAD_TYPES_M) >> \ |
| HTT_H2T_STATS_REQ_UPLOAD_TYPES_S) |
| #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_UPLOAD_TYPES, _val); \ |
| ((_var) |= ((_val) << HTT_H2T_STATS_REQ_UPLOAD_TYPES_S)); \ |
| } while (0) |
| |
| #define HTT_H2T_STATS_REQ_RESET_TYPES_GET(_var) \ |
| (((_var) & HTT_H2T_STATS_REQ_RESET_TYPES_M) >> \ |
| HTT_H2T_STATS_REQ_RESET_TYPES_S) |
| #define HTT_H2T_STATS_REQ_RESET_TYPES_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_RESET_TYPES, _val); \ |
| ((_var) |= ((_val) << HTT_H2T_STATS_REQ_RESET_TYPES_S)); \ |
| } while (0) |
| |
| #define HTT_H2T_STATS_REQ_CFG_VAL_GET(_var) \ |
| (((_var) & HTT_H2T_STATS_REQ_CFG_VAL_M) >> \ |
| HTT_H2T_STATS_REQ_CFG_VAL_S) |
| #define HTT_H2T_STATS_REQ_CFG_VAL_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_VAL, _val); \ |
| ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_VAL_S)); \ |
| } while (0) |
| |
| #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_GET(_var) \ |
| (((_var) & HTT_H2T_STATS_REQ_CFG_STAT_TYPE_M) >> \ |
| HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S) |
| #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_STAT_TYPE, _val); \ |
| ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S)); \ |
| } while (0) |
| |
| /** |
| * @brief host -> target HTT out-of-band sync request |
| * |
| * @details |
| * The HTT SYNC tells the target to suspend processing of subsequent |
| * HTT host-to-target messages until some other target agent locally |
| * informs the target HTT FW that the current sync counter is equal to |
| * or greater than (in a modulo sense) the sync counter specified in |
| * the SYNC message. |
| * This allows other host-target components to synchronize their operation |
| * with HTT, e.g. to ensure that tx frames don't get transmitted until a |
| * security key has been downloaded to and activated by the target. |
| * In the absence of any explicit synchronization counter value |
| * specification, the target HTT FW will use zero as the default current |
| * sync value. |
| * |
| * |31 24|23 16|15 8|7 0| |
| * |-----------------------------------------------------------| |
| * | reserved | sync count | msg type | |
| * |-----------------------------------------------------------| |
| * Header fields: |
| * - MSG_TYPE |
| * Bits 7:0 |
| * Purpose: identifies this as a sync message |
| * Value: 0x4 |
| * - SYNC_COUNT |
| * Bits 15:8 |
| * Purpose: specifies what sync value the HTT FW will wait for from |
| * an out-of-band specification to resume its operation |
| * Value: in-band sync counter value to compare against the out-of-band |
| * counter spec. |
| * The HTT target FW will suspend its host->target message processing |
| * as long as |
| * 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128 |
| */ |
| |
| #define HTT_H2T_SYNC_MSG_SZ 4 |
| |
| #define HTT_H2T_SYNC_COUNT_M 0x0000ff00 |
| #define HTT_H2T_SYNC_COUNT_S 8 |
| |
| #define HTT_H2T_SYNC_COUNT_GET(_var) \ |
| (((_var) & HTT_H2T_SYNC_COUNT_M) >> \ |
| HTT_H2T_SYNC_COUNT_S) |
| #define HTT_H2T_SYNC_COUNT_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_H2T_SYNC_COUNT, _val); \ |
| ((_var) |= ((_val) << HTT_H2T_SYNC_COUNT_S)); \ |
| } while (0) |
| |
| |
| /** |
| * @brief HTT aggregation configuration |
| */ |
| #define HTT_AGGR_CFG_MSG_SZ 4 |
| |
| #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_M 0xff00 |
| #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S 8 |
| #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_M 0x1f0000 |
| #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S 16 |
| |
| #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_GET(_var) \ |
| (((_var) & HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_M) >> \ |
| HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S) |
| #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM, _val); \ |
| ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S)); \ |
| } while (0) |
| |
| #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_GET(_var) \ |
| (((_var) & HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_M) >> \ |
| HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S) |
| #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM, _val); \ |
| ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S)); \ |
| } while (0) |
| |
| |
| /** |
| * @brief host -> target HTT configure max amsdu info per vdev |
| * |
| * @details |
| * The HTT AGGR CFG EX tells the target to configure max_amsdu info per vdev |
| * |
| * |31 21|20 16|15 8|7 0| |
| * |-----------------------------------------------------------| |
| * | reserved | vdev id | max amsdu | msg type | |
| * |-----------------------------------------------------------| |
| * Header fields: |
| * - MSG_TYPE |
| * Bits 7:0 |
| * Purpose: identifies this as a aggr cfg ex message |
| * Value: 0xa |
| * - MAX_NUM_AMSDU_SUBFRM |
| * Bits 15:8 |
| * Purpose: max MSDUs per A-MSDU |
| * - VDEV_ID |
| * Bits 20:16 |
| * Purpose: ID of the vdev to which this limit is applied |
| */ |
| #define HTT_AGGR_CFG_EX_MSG_SZ 4 |
| |
| #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_M 0xff00 |
| #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S 8 |
| #define HTT_AGGR_CFG_EX_VDEV_ID_M 0x1f0000 |
| #define HTT_AGGR_CFG_EX_VDEV_ID_S 16 |
| |
| #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_GET(_var) \ |
| (((_var) & HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_M) >> \ |
| HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S) |
| #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM, _val); \ |
| ((_var) |= ((_val) << HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S)); \ |
| } while (0) |
| |
| #define HTT_AGGR_CFG_EX_VDEV_ID_GET(_var) \ |
| (((_var) & HTT_AGGR_CFG_EX_VDEV_ID_M) >> \ |
| HTT_AGGR_CFG_EX_VDEV_ID_S) |
| #define HTT_AGGR_CFG_EX_VDEV_ID_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_VDEV_ID, _val); \ |
| ((_var) |= ((_val) << HTT_AGGR_CFG_EX_VDEV_ID_S)); \ |
| } while (0) |
| |
| /** |
| * @brief HTT WDI_IPA Config Message |
| * |
| * @details |
| * The HTT WDI_IPA config message is created/sent by host at driver |
| * init time. It contains information about data structures used on |
| * WDI_IPA TX and RX path. |
| * TX CE ring is used for pushing packet metadata from IPA uC |
| * to WLAN FW |
| * TX Completion ring is used for generating TX completions from |
| * WLAN FW to IPA uC |
| * RX Indication ring is used for indicating RX packets from FW |
| * to IPA uC |
| * RX Ring2 is used as either completion ring or as second |
| * indication ring. when Ring2 is used as completion ring, IPA uC |
| * puts completed RX packet meta data to Ring2. when Ring2 is used |
| * as second indication ring, RX packets for LTE-WLAN aggregation are |
| * indicated in Ring2, other RX packets (e.g. hotspot related) are |
| * indicated in RX Indication ring. Please see WDI_IPA specification |
| * for more details. |
| * |31 24|23 16|15 8|7 0| |
| * |----------------+----------------+----------------+----------------| |
| * | tx pkt pool size | Rsvd | msg_type | |
| * |-------------------------------------------------------------------| |
| * | tx comp ring base (bits 31:0) | |
| #if HTT_PADDR64 |
| * | tx comp ring base (bits 63:32) | |
| #endif |
| * |-------------------------------------------------------------------| |
| * | tx comp ring size | |
| * |-------------------------------------------------------------------| |
| * | tx comp WR_IDX physical address (bits 31:0) | |
| #if HTT_PADDR64 |
| * | tx comp WR_IDX physical address (bits 63:32) | |
| #endif |
| * |-------------------------------------------------------------------| |
| * | tx CE WR_IDX physical address (bits 31:0) | |
| #if HTT_PADDR64 |
| * | tx CE WR_IDX physical address (bits 63:32) | |
| #endif |
| * |-------------------------------------------------------------------| |
| * | rx indication ring base (bits 31:0) | |
| #if HTT_PADDR64 |
| * | rx indication ring base (bits 63:32) | |
| #endif |
| * |-------------------------------------------------------------------| |
| * | rx indication ring size | |
| * |-------------------------------------------------------------------| |
| * | rx ind RD_IDX physical address (bits 31:0) | |
| #if HTT_PADDR64 |
| * | rx ind RD_IDX physical address (bits 63:32) | |
| #endif |
| * |-------------------------------------------------------------------| |
| * | rx ind WR_IDX physical address (bits 31:0) | |
| #if HTT_PADDR64 |
| * | rx ind WR_IDX physical address (bits 63:32) | |
| #endif |
| * |-------------------------------------------------------------------| |
| * |-------------------------------------------------------------------| |
| * | rx ring2 base (bits 31:0) | |
| #if HTT_PADDR64 |
| * | rx ring2 base (bits 63:32) | |
| #endif |
| * |-------------------------------------------------------------------| |
| * | rx ring2 size | |
| * |-------------------------------------------------------------------| |
| * | rx ring2 RD_IDX physical address (bits 31:0) | |
| #if HTT_PADDR64 |
| * | rx ring2 RD_IDX physical address (bits 63:32) | |
| #endif |
| * |-------------------------------------------------------------------| |
| * | rx ring2 WR_IDX physical address (bits 31:0) | |
| #if HTT_PADDR64 |
| * | rx ring2 WR_IDX physical address (bits 63:32) | |
| #endif |
| * |-------------------------------------------------------------------| |
| * |
| * Header fields: |
| * Header fields: |
| * - MSG_TYPE |
| * Bits 7:0 |
| * Purpose: Identifies this as WDI_IPA config message |
| * value: = 0x8 |
| * - TX_PKT_POOL_SIZE |
| * Bits 15:0 |
| * Purpose: Total number of TX packet buffer pool allocated by Host for |
| * WDI_IPA TX path |
| * For systems using 32-bit format for bus addresses: |
| * - TX_COMP_RING_BASE_ADDR |
| * Bits 31:0 |
| * Purpose: TX Completion Ring base address in DDR |
| * - TX_COMP_RING_SIZE |
| * Bits 31:0 |
| * Purpose: TX Completion Ring size (must be power of 2) |
| * - TX_COMP_WR_IDX_ADDR |
| * Bits 31:0 |
| * Purpose: IPA doorbell register address OR DDR address where WIFI FW |
| * updates the Write Index for WDI_IPA TX completion ring |
| * - TX_CE_WR_IDX_ADDR |
| * Bits 31:0 |
| * Purpose: DDR address where IPA uC |
| * updates the WR Index for TX CE ring |
| * (needed for fusion platforms) |
| * - RX_IND_RING_BASE_ADDR |
| * Bits 31:0 |
| * Purpose: RX Indication Ring base address in DDR |
| * - RX_IND_RING_SIZE |
| * Bits 31:0 |
| * Purpose: RX Indication Ring size |
| * - RX_IND_RD_IDX_ADDR |
| * Bits 31:0 |
| * Purpose: DDR address where IPA uC updates the Read Index for WDI_IPA |
| * RX indication ring |
| * - RX_IND_WR_IDX_ADDR |
| * Bits 31:0 |
| * Purpose: IPA doorbell register address OR DDR address where WIFI FW |
| * updates the Write Index for WDI_IPA RX indication ring |
| * - RX_RING2_BASE_ADDR |
| * Bits 31:0 |
| * Purpose: Second RX Ring(Indication or completion)base address in DDR |
| * - RX_RING2_SIZE |
| * Bits 31:0 |
| * Purpose: Second RX Ring size (must be >= RX_IND_RING_SIZE) |
| * - RX_RING2_RD_IDX_ADDR |
| * Bits 31:0 |
| * Purpose: If Second RX ring is Indication ring, DDR address where |
| * IPA uC updates the Read Index for Ring2. |
| * If Second RX ring is completion ring, this is NOT used |
| * - RX_RING2_WR_IDX_ADDR |
| * Bits 31:0 |
| * Purpose: If Second RX ring is Indication ring, DDR address where |
| * WIFI FW updates the Write Index for WDI_IPA RX ring2 |
| * If second RX ring is completion ring, DDR address where |
| * IPA uC updates the Write Index for Ring 2. |
| * For systems using 64-bit format for bus addresses: |
| * - TX_COMP_RING_BASE_ADDR_LO |
| * Bits 31:0 |
| * Purpose: Lower 4 bytes of TX Completion Ring base physical address in DDR |
| * - TX_COMP_RING_BASE_ADDR_HI |
| * Bits 31:0 |
| * Purpose: Higher 4 bytes of TX Completion Ring base physical address in DDR |
| * - TX_COMP_RING_SIZE |
| * Bits 31:0 |
| * Purpose: TX Completion Ring size (must be power of 2) |
| * - TX_COMP_WR_IDX_ADDR_LO |
| * Bits 31:0 |
| * Purpose: Lower 4 bytes of IPA doorbell register address OR |
| * Lower 4 bytes of DDR address where WIFI FW |
| * updates the Write Index for WDI_IPA TX completion ring |
| * - TX_COMP_WR_IDX_ADDR_HI |
| * Bits 31:0 |
| * Purpose: Higher 4 bytes of IPA doorbell register address OR |
| * Higher 4 bytes of DDR address where WIFI FW |
| * updates the Write Index for WDI_IPA TX completion ring |
| * - TX_CE_WR_IDX_ADDR_LO |
| * Bits 31:0 |
| * Purpose: Lower 4 bytes of DDR address where IPA uC |
| * updates the WR Index for TX CE ring |
| * (needed for fusion platforms) |
| * - TX_CE_WR_IDX_ADDR_HI |
| * Bits 31:0 |
| * Purpose: Higher 4 bytes of DDR address where IPA uC |
| * updates the WR Index for TX CE ring |
| * (needed for fusion platforms) |
| * - RX_IND_RING_BASE_ADDR_LO |
| * Bits 31:0 |
| * Purpose: Lower 4 bytes of RX Indication Ring base address in DDR |
| * - RX_IND_RING_BASE_ADDR_HI |
| * Bits 31:0 |
| * Purpose: Higher 4 bytes of RX Indication Ring base address in DDR |
| * - RX_IND_RING_SIZE |
| * Bits 31:0 |
| * Purpose: RX Indication Ring size |
| * - RX_IND_RD_IDX_ADDR_LO |
| * Bits 31:0 |
| * Purpose: Lower 4 bytes of DDR address where IPA uC updates the Read Index |
| * for WDI_IPA RX indication ring |
| * - RX_IND_RD_IDX_ADDR_HI |
| * Bits 31:0 |
| * Purpose: Higher 4 bytes of DDR address where IPA uC updates the Read Index |
| * for WDI_IPA RX indication ring |
| * - RX_IND_WR_IDX_ADDR_LO |
| * Bits 31:0 |
| * Purpose: Lower 4 bytes of IPA doorbell register address OR |
| * Lower 4 bytes of DDR address where WIFI FW |
| * updates the Write Index for WDI_IPA RX indication ring |
| * - RX_IND_WR_IDX_ADDR_HI |
| * Bits 31:0 |
| * Purpose: Higher 4 bytes of IPA doorbell register address OR |
| * Higher 4 bytes of DDR address where WIFI FW |
| * updates the Write Index for WDI_IPA RX indication ring |
| * - RX_RING2_BASE_ADDR_LO |
| * Bits 31:0 |
| * Purpose: Lower 4 bytes of Second RX Ring(Indication OR completion)base address in DDR |
| * - RX_RING2_BASE_ADDR_HI |
| * Bits 31:0 |
| * Purpose: Higher 4 bytes of Second RX Ring(Indication OR completion)base address in DDR |
| * - RX_RING2_SIZE |
| * Bits 31:0 |
| * Purpose: Second RX Ring size (must be >= RX_IND_RING_SIZE) |
| * - RX_RING2_RD_IDX_ADDR_LO |
| * Bits 31:0 |
| * Purpose: If Second RX ring is Indication ring, lower 4 bytes of |
| * DDR address where IPA uC updates the Read Index for Ring2. |
| * If Second RX ring is completion ring, this is NOT used |
| * - RX_RING2_RD_IDX_ADDR_HI |
| * Bits 31:0 |
| * Purpose: If Second RX ring is Indication ring, higher 4 bytes of |
| * DDR address where IPA uC updates the Read Index for Ring2. |
| * If Second RX ring is completion ring, this is NOT used |
| * - RX_RING2_WR_IDX_ADDR_LO |
| * Bits 31:0 |
| * Purpose: If Second RX ring is Indication ring, lower 4 bytes of |
| * DDR address where WIFI FW updates the Write Index |
| * for WDI_IPA RX ring2 |
| * If second RX ring is completion ring, lower 4 bytes of |
| * DDR address where IPA uC updates the Write Index for Ring 2. |
| * - RX_RING2_WR_IDX_ADDR_HI |
| * Bits 31:0 |
| * Purpose: If Second RX ring is Indication ring, higher 4 bytes of |
| * DDR address where WIFI FW updates the Write Index |
| * for WDI_IPA RX ring2 |
| * If second RX ring is completion ring, higher 4 bytes of |
| * DDR address where IPA uC updates the Write Index for Ring 2. |
| */ |
| |
| #if HTT_PADDR64 |
| #define HTT_WDI_IPA_CFG_SZ 88 /* bytes */ |
| #else |
| #define HTT_WDI_IPA_CFG_SZ 52 /* bytes */ |
| #endif |
| |
| #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_M 0xffff0000 |
| #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S 16 |
| |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S 0 |
| |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S 0 |
| |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S 0 |
| |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S 0 |
| |
| #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S 0 |
| |
| #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S 0 |
| |
| #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S 0 |
| |
| #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S 0 |
| |
| #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S 0 |
| |
| #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S 0 |
| |
| #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_M 0xffffffff |
| #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S 0 |
| |
| #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_M) >> HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S) |
| #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S)); \ |
| } while (0) |
| |
| /* for systems using 32-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S) |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S) |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S) |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S)); \ |
| } while (0) |
| |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_M) >> HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S) |
| #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S)); \ |
| } while (0) |
| |
| /* for systems using 32-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S) |
| #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S) |
| #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S) |
| #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S)); \ |
| } while (0) |
| |
| |
| /* for systems using 32-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S) |
| #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S) |
| #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S) |
| #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S)); \ |
| } while (0) |
| |
| /* for systems using 32-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S) |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S) |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S) |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S)); \ |
| } while (0) |
| |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_M) >> HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S) |
| #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_SIZE, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S)); \ |
| } while (0) |
| |
| /* for systems using 32-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S) |
| #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S) |
| #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S) |
| #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S)); \ |
| } while (0) |
| |
| /* for systems using 32-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S) |
| #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S) |
| #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S) |
| #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S)); \ |
| } while (0) |
| |
| /* for systems using 32-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S) |
| #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S) |
| #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S) |
| #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S)); \ |
| } while (0) |
| |
| #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_RING2_SIZE_M) >> HTT_WDI_IPA_CFG_RX_RING2_SIZE_S) |
| #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_SIZE, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_SIZE_S)); \ |
| } while (0) |
| |
| /* for systems using 32-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S) |
| #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S) |
| #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S) |
| #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S)); \ |
| } while (0) |
| |
| /* for systems using 32-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S) |
| #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S) |
| #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S)); \ |
| } while (0) |
| |
| /* for systems using 64-bit format for bus addr */ |
| #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_M) >> HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S) |
| #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S)); \ |
| } while (0) |
| |
| /* |
| * TEMPLATE_HTT_WDI_IPA_CONFIG_T: |
| * This macro defines a htt_wdi_ipa_configXXX_t in which any physical |
| * addresses are stored in a XXX-bit field. |
| * This macro is used to define both htt_wdi_ipa_config32_t and |
| * htt_wdi_ipa_config64_t structs. |
| */ |
| #define TEMPLATE_HTT_WDI_IPA_CONFIG_T(_paddr_bits_, \ |
| _paddr__tx_comp_ring_base_addr_, \ |
| _paddr__tx_comp_wr_idx_addr_, \ |
| _paddr__tx_ce_wr_idx_addr_, \ |
| _paddr__rx_ind_ring_base_addr_, \ |
| _paddr__rx_ind_rd_idx_addr_, \ |
| _paddr__rx_ind_wr_idx_addr_, \ |
| _paddr__rx_ring2_base_addr_,\ |
| _paddr__rx_ring2_rd_idx_addr_,\ |
| _paddr__rx_ring2_wr_idx_addr_) \ |
| PREPACK struct htt_wdi_ipa_cfg ## _paddr_bits_ ## _t \ |
| { \ |
| /* DWORD 0: flags and meta-data */ \ |
| A_UINT32 \ |
| msg_type: 8, /* HTT_H2T_MSG_TYPE_WDI_IPA_CFG */ \ |
| reserved: 8, \ |
| tx_pkt_pool_size: 16;\ |
| /* DWORD 1 */\ |
| _paddr__tx_comp_ring_base_addr_;\ |
| /* DWORD 2 (or 3)*/\ |
| A_UINT32 tx_comp_ring_size;\ |
| /* DWORD 3 (or 4)*/\ |
| _paddr__tx_comp_wr_idx_addr_;\ |
| /* DWORD 4 (or 6)*/\ |
| _paddr__tx_ce_wr_idx_addr_;\ |
| /* DWORD 5 (or 8)*/\ |
| _paddr__rx_ind_ring_base_addr_;\ |
| /* DWORD 6 (or 10)*/\ |
| A_UINT32 rx_ind_ring_size;\ |
| /* DWORD 7 (or 11)*/\ |
| _paddr__rx_ind_rd_idx_addr_;\ |
| /* DWORD 8 (or 13)*/\ |
| _paddr__rx_ind_wr_idx_addr_;\ |
| /* DWORD 9 (or 15)*/\ |
| _paddr__rx_ring2_base_addr_;\ |
| /* DWORD 10 (or 17) */\ |
| A_UINT32 rx_ring2_size;\ |
| /* DWORD 11 (or 18) */\ |
| _paddr__rx_ring2_rd_idx_addr_;\ |
| /* DWORD 12 (or 20) */\ |
| _paddr__rx_ring2_wr_idx_addr_;\ |
| } POSTPACK |
| |
| /* define a htt_wdi_ipa_config32_t type */ |
| TEMPLATE_HTT_WDI_IPA_CONFIG_T(32, HTT_VAR_PADDR32(tx_comp_ring_base_addr), HTT_VAR_PADDR32(tx_comp_wr_idx_addr), HTT_VAR_PADDR32(tx_ce_wr_idx_addr), HTT_VAR_PADDR32(rx_ind_ring_base_addr), HTT_VAR_PADDR32(rx_ind_rd_idx_addr),HTT_VAR_PADDR32(rx_ind_wr_idx_addr), HTT_VAR_PADDR32(rx_ring2_base_addr), HTT_VAR_PADDR32(rx_ring2_rd_idx_addr), HTT_VAR_PADDR32(rx_ring2_wr_idx_addr)); |
| |
| /* define a htt_wdi_ipa_config64_t type */ |
| TEMPLATE_HTT_WDI_IPA_CONFIG_T(64, HTT_VAR_PADDR64_LE(tx_comp_ring_base_addr), HTT_VAR_PADDR64_LE(tx_comp_wr_idx_addr), HTT_VAR_PADDR64_LE(tx_ce_wr_idx_addr), HTT_VAR_PADDR64_LE(rx_ind_ring_base_addr), HTT_VAR_PADDR64_LE(rx_ind_rd_idx_addr), HTT_VAR_PADDR64_LE(rx_ind_wr_idx_addr), HTT_VAR_PADDR64_LE(rx_ring2_base_addr), HTT_VAR_PADDR64_LE(rx_ring2_rd_idx_addr), HTT_VAR_PADDR64_LE(rx_ring2_wr_idx_addr)); |
| |
| #if HTT_PADDR64 |
| #define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg64_t |
| #else |
| #define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg32_t |
| #endif |
| |
| enum htt_wdi_ipa_op_code { |
| HTT_WDI_IPA_OPCODE_TX_SUSPEND = 0, |
| HTT_WDI_IPA_OPCODE_TX_RESUME = 1, |
| HTT_WDI_IPA_OPCODE_RX_SUSPEND = 2, |
| HTT_WDI_IPA_OPCODE_RX_RESUME = 3, |
| HTT_WDI_IPA_OPCODE_DBG_STATS = 4, |
| /* keep this last */ |
| HTT_WDI_IPA_OPCODE_MAX |
| }; |
| |
| /** |
| * @brief HTT WDI_IPA Operation Request Message |
| * |
| * @details |
| * HTT WDI_IPA Operation Request message is sent by host |
| * to either suspend or resume WDI_IPA TX or RX path. |
| * |31 24|23 16|15 8|7 0| |
| * |----------------+----------------+----------------+----------------| |
| * | op_code | Rsvd | msg_type | |
| * |-------------------------------------------------------------------| |
| * |
| * Header fields: |
| * - MSG_TYPE |
| * Bits 7:0 |
| * Purpose: Identifies this as WDI_IPA Operation Request message |
| * value: = 0x9 |
| * - OP_CODE |
| * Bits 31:16 |
| * Purpose: Identifies operation host is requesting (e.g. TX suspend) |
| * value: = enum htt_wdi_ipa_op_code |
| */ |
| |
| PREPACK struct htt_wdi_ipa_op_request_t |
| { |
| /* DWORD 0: flags and meta-data */ |
| A_UINT32 |
| msg_type: 8, /* HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQUEST */ |
| reserved: 8, |
| op_code: 16; |
| } POSTPACK; |
| |
| #define HTT_WDI_IPA_OP_REQUEST_SZ 4 /* bytes */ |
| |
| #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_M 0xffff0000 |
| #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_S 16 |
| |
| #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_GET(_var) \ |
| (((_var) & HTT_WDI_IPA_OP_REQUEST_OP_CODE_M) >> HTT_WDI_IPA_OP_REQUEST_OP_CODE_S) |
| #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_REQUEST_OP_CODE, _val); \ |
| ((_var) |= ((_val) << HTT_WDI_IPA_OP_REQUEST_OP_CODE_S)); \ |
| } while (0) |
| |
| /* |
| * @brief host -> target HTT_SRING_SETUP message |
| * |
| * @details |
| * After target is booted up, Host can send SRING setup message for |
| * each host facing LMAC SRING. Target setups up HW registers based |
| * on setup message and confirms back to Host if response_required is set. |
| * Host should wait for confirmation message before sending new SRING |
| * setup message |
| * |
| * The message would appear as follows: |
| * |31 24|23 20|19|18 16|15|14 8|7 0| |
| * |--------------- +-----------------+----------------+------------------| |
| * | ring_type | ring_id | pdev_id | msg_type | |
| * |----------------------------------------------------------------------| |
| * | ring_base_addr_lo | |
| * |----------------------------------------------------------------------| |
| * | ring_base_addr_hi | |
| * |----------------------------------------------------------------------| |
| * |ring_misc_cfg_flag|ring_entry_size| ring_size | |
| * |----------------------------------------------------------------------| |
| * | ring_head_offset32_remote_addr_lo | |
| * |----------------------------------------------------------------------| |
| * | ring_head_offset32_remote_addr_hi | |
| * |----------------------------------------------------------------------| |
| * | ring_tail_offset32_remote_addr_lo | |
| * |----------------------------------------------------------------------| |
| * | ring_tail_offset32_remote_addr_hi | |
| * |----------------------------------------------------------------------| |
| * | ring_msi_addr_lo | |
| * |----------------------------------------------------------------------| |
| * | ring_msi_addr_hi | |
| * |----------------------------------------------------------------------| |
| * | ring_msi_data | |
| * |----------------------------------------------------------------------| |
| * | intr_timer_th |IM| intr_batch_counter_th | |
| * |----------------------------------------------------------------------| |
| * | reserved |RR|PTCF| intr_low_threshold | |
| * |----------------------------------------------------------------------| |
| * Where |
| * IM = sw_intr_mode |
| * RR = response_required |
| * PTCF = prefetch_timer_cfg |
| * |
| * The message is interpreted as follows: |
| * dword0 - b'0:7 - msg_type: This will be set to |
| * HTT_H2T_MSG_TYPE_SRING_SETUP |
| * b'8:15 - pdev_id: |
| * 0 (for rings at SOC/UMAC level), |
| * 1/2/3 mac id (for rings at LMAC level) |
| * b'16:23 - ring_id: identify which ring is to setup, |
| * more details can be got from enum htt_srng_ring_id |
| * b'24:31 - ring_type: identify type of host rings, |
| * more details can be got from enum htt_srng_ring_type |
| * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address |
| * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address |
| * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words |
| * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units |
| * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and |
| * SW_TO_HW_RING. |
| * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. |
| * dword4 - b'0:31 - ring_head_offset32_remote_addr_lo: |
| * Lower 32 bits of memory address of the remote variable |
| * storing the 4-byte word offset that identifies the head |
| * element within the ring. |
| * (The head offset variable has type A_UINT32.) |
| * Valid for HW_TO_SW and SW_TO_SW rings. |
| * dword5 - b'0:31 - ring_head_offset32_remote_addr_hi: |
| * Upper 32 bits of memory address of the remote variable |
| * storing the 4-byte word offset that identifies the head |
| * element within the ring. |
| * (The head offset variable has type A_UINT32.) |
| * Valid for HW_TO_SW and SW_TO_SW rings. |
| * dword6 - b'0:31 - ring_tail_offset32_remote_addr_lo: |
| * Lower 32 bits of memory address of the remote variable |
| * storing the 4-byte word offset that identifies the tail |
| * element within the ring. |
| * (The tail offset variable has type A_UINT32.) |
| * Valid for HW_TO_SW and SW_TO_SW rings. |
| * dword7 - b'0:31 - ring_tail_offset32_remote_addr_hi: |
| * Upper 32 bits of memory address of the remote variable |
| * storing the 4-byte word offset that identifies the tail |
| * element within the ring. |
| * (The tail offset variable has type A_UINT32.) |
| * Valid for HW_TO_SW and SW_TO_SW rings. |
| * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address |
| * valid only for HW_TO_SW_RING and SW_TO_HW_RING |
| * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address |
| * valid only for HW_TO_SW_RING and SW_TO_HW_RING |
| * dword10 - b'0:31 - ring_msi_data: MSI data |
| * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs |
| * valid only for HW_TO_SW_RING and SW_TO_HW_RING |
| * dword11 - b'0:14 - intr_batch_counter_th: |
| * batch counter threshold is in units of 4-byte words. |
| * HW internally maintains and increments batch count. |
| * (see SRING spec for detail description). |
| * When batch count reaches threshold value, an interrupt |
| * is generated by HW. |
| * b'15 - sw_intr_mode: |
| * This configuration shall be static. |
| * Only programmed at power up. |
| * 0: generate pulse style sw interrupts |
| * 1: generate level style sw interrupts |
| * b'16:31 - intr_timer_th: |
| * The timer init value when timer is idle or is |
| * initialized to start downcounting. |
| * In 8us units (to cover a range of 0 to 524 ms) |
| * dword12 - b'0:15 - intr_low_threshold: |
| * Used only by Consumer ring to generate ring_sw_int_p. |
| * Ring entries low threshold water mark, that is used |
| * in combination with the interrupt timer as well as |
| * the the clearing of the level interrupt. |
| * b'16:18 - prefetch_timer_cfg: |
| * Used only by Consumer ring to set timer mode to |
| * support Application prefetch handling. |
| * The external tail offset/pointer will be updated |
| * at following intervals: |
| * 3'b000: (Prefetch feature disabled; used only for debug) |
| * 3'b001: 1 usec |
| * 3'b010: 4 usec |
| * 3'b011: 8 usec (default) |
| * 3'b100: 16 usec |
| * Others: Reserverd |
| * b'19 - response_required: |
| * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response |
| * b'20:31 - reserved: reserved for future use |
| */ |
| PREPACK struct htt_sring_setup_t { |
| A_UINT32 msg_type: 8, |
| pdev_id: 8, |
| ring_id: 8, |
| ring_type: 8; |
| A_UINT32 ring_base_addr_lo; |
| A_UINT32 ring_base_addr_hi; |
| A_UINT32 ring_size: 16, |
| ring_entry_size: 8, |
| ring_misc_cfg_flag: 8; |
| A_UINT32 ring_head_offset32_remote_addr_lo; |
| A_UINT32 ring_head_offset32_remote_addr_hi; |
| A_UINT32 ring_tail_offset32_remote_addr_lo; |
| A_UINT32 ring_tail_offset32_remote_addr_hi; |
| A_UINT32 ring_msi_addr_lo; |
| A_UINT32 ring_msi_addr_hi; |
| A_UINT32 ring_msi_data; |
| A_UINT32 intr_batch_counter_th: 15, |
| sw_intr_mode: 1, |
| intr_timer_th: 16; |
| A_UINT32 intr_low_threshold: 16, |
| prefetch_timer_cfg: 3, |
| response_required: 1, |
| reserved1: 12; |
| } POSTPACK; |
| |
| enum htt_srng_ring_type { |
| HTT_HW_TO_SW_RING = 0, |
| HTT_SW_TO_HW_RING, |
| HTT_SW_TO_SW_RING, |
| /* Insert new ring types above this line */ |
| }; |
| |
| enum htt_srng_ring_id { |
| HTT_RXDMA_HOST_BUF_RING = 0, /* Used by FW to feed remote buffers and update remote packets */ |
| HTT_RXDMA_MONITOR_STATUS_RING, /* For getting all PPDU/MPDU/MSDU status deescriptors on host for monitor VAP or packet log purposes */ |
| HTT_RXDMA_MONITOR_BUF_RING, /* For feeding free host buffers to RxDMA for monitor traffic upload */ |
| HTT_RXDMA_MONITOR_DESC_RING, /* For providing free LINK_DESC to RXDMA for monitor traffic upload */ |
| HTT_RXDMA_MONITOR_DEST_RING, /* Per MPDU indication to host for monitor traffic upload */ |
| HTT_HOST1_TO_FW_RXBUF_RING, /* (mobile only) used by host to provide remote RX buffers */ |
| HTT_HOST2_TO_FW_RXBUF_RING, /* (mobile only) second ring used by host to provide remote RX buffers */ |
| /* Add Other SRING which can't be directly configured by host software above this line */ |
| }; |
| |
| #define HTT_SRING_SETUP_SZ (sizeof(struct htt_sring_setup_t)) |
| |
| #define HTT_SRING_SETUP_PDEV_ID_M 0x0000ff00 |
| #define HTT_SRING_SETUP_PDEV_ID_S 8 |
| #define HTT_SRING_SETUP_PDEV_ID_GET(_var) \ |
| (((_var) & HTT_SRING_SETUP_PDEV_ID_M) >> \ |
| HTT_SRING_SETUP_PDEV_ID_S) |
| #define HTT_SRING_SETUP_PDEV_ID_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_SRING_SETUP_PDEV_ID, _val); \ |
| ((_var) |= ((_val) << HTT_SRING_SETUP_PDEV_ID_S)); \ |
| } while (0) |
| |
| #define HTT_SRING_SETUP_RING_ID_M 0x00ff0000 |
| #define HTT_SRING_SETUP_RING_ID_S 16 |
| #define HTT_SRING_SETUP_RING_ID_GET(_var) \ |
| (((_var) & HTT_SRING_SETUP_RING_ID_M) >> \ |
| HTT_SRING_SETUP_RING_ID_S) |
| #define HTT_SRING_SETUP_RING_ID_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_ID, _val); \ |
| ((_var) |= ((_val) << HTT_SRING_SETUP_RING_ID_S)); \ |
| } while (0) |
| |
| #define HTT_SRING_SETUP_RING_TYPE_M 0xff000000 |
| #define HTT_SRING_SETUP_RING_TYPE_S 24 |
| #define HTT_SRING_SETUP_RING_TYPE_GET(_var) \ |
| (((_var) & HTT_SRING_SETUP_RING_TYPE_M) >> \ |
| HTT_SRING_SETUP_RING_TYPE_S) |
| #define HTT_SRING_SETUP_RING_TYPE_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_TYPE, _val); \ |
| ((_var) |= ((_val) << HTT_SRING_SETUP_RING_TYPE_S)); \ |
| } while (0) |
| |
| #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_M 0xffffffff |
| #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_S 0 |
| #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_GET(_var) \ |
| (((_var) & HTT_SRING_SETUP_RING_BASE_ADDR_LO_M) >> \ |
| HTT_SRING_SETUP_RING_BASE_ADDR_LO_S) |
| #define HTT_SRING_SETUP_RING_BASE_ADDR_LO_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_BASE_ADDR_LO, _val); \ |
| ((_var) |= ((_val) << HTT_SRING_SETUP_RING_BASE_ADDR_LO_S)); \ |
| } while (0) |
| |
| #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_M 0xffffffff |
| #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_S 0 |
| #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_GET(_var) \ |
| (((_var) & HTT_SRING_SETUP_RING_BASE_ADDR_HI_M) >> \ |
| HTT_SRING_SETUP_RING_BASE_ADDR_HI_S) |
| #define HTT_SRING_SETUP_RING_BASE_ADDR_HI_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_BASE_ADDR_HI, _val); \ |
| ((_var) |= ((_val) << HTT_SRING_SETUP_RING_BASE_ADDR_HI_S)); \ |
| } while (0) |
| |
| #define HTT_SRING_SETUP_RING_SIZE_M 0x0000ffff |
| #define HTT_SRING_SETUP_RING_SIZE_S 0 |
| #define HTT_SRING_SETUP_RING_SIZE_GET(_var) \ |
| (((_var) & HTT_SRING_SETUP_RING_SIZE_M) >> \ |
| HTT_SRING_SETUP_RING_SIZE_S) |
| #define HTT_SRING_SETUP_RING_SIZE_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_SIZE, _val); \ |
| ((_var) |= ((_val) << HTT_SRING_SETUP_RING_SIZE_S)); \ |
| } while (0) |
| |
| #define HTT_SRING_SETUP_ENTRY_SIZE_M 0x00ff00000 |
| #define HTT_SRING_SETUP_ENTRY_SIZE_S 16 |
| #define HTT_SRING_SETUP_ENTRY_SIZE_GET(_var) \ |
| (((_var) & HTT_SRING_SETUP_ENTRY_SIZE_M) >> \ |
| HTT_SRING_SETUP_ENTRY_SIZE_S) |
| #define HTT_SRING_SETUP_ENTRY_SIZE_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_SRING_SETUP_ENTRY_SIZE, _val); \ |
| ((_var) |= ((_val) << HTT_SRING_SETUP_ENTRY_SIZE_S)); \ |
| } while (0) |
| |
| #define HTT_SRING_SETUP_MISC_CFG_FLAG_M 0xff0000000 |
| #define HTT_SRING_SETUP_MISC_CFG_FLAG_S 24 |
| #define HTT_SRING_SETUP_MISC_CFG_FLAG_GET(_var) \ |
| (((_var) & HTT_SRING_SETUP_MISC_CFG_FLAG_M) >> \ |
| HTT_SRING_SETUP_MISC_CFG_FLAG_S) |
| #define HTT_SRING_SETUP_MISC_CFG_FLAG_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_SRING_SETUP_MISC_CFG_FLAG, _val); \ |
| ((_var) |= ((_val) << HTT_SRING_SETUP_MISC_CFG_FLAG_S)); \ |
| } while (0) |
| |
| #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_M 0xffffffff |
| #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S 0 |
| #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_GET(_var) \ |
| (((_var) & HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_M) >> \ |
| HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S) |
| #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO, _val); \ |
| ((_var) |= ((_val) << HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_LO_S)); \ |
| } while (0) |
| |
| #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_M 0xffffffff |
| #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S 0 |
| #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_GET(_var) \ |
| (((_var) & HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_M) >> \ |
| HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S) |
| #define HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI, _val); \ |
| ((_var) |= ((_val) << HTT_SRING_SETUP_HEAD_OFFSET32_REMOTE_BASE_ADDR_HI_S)); \ |
| } while (0) |
| |
| #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_M 0xffffffff |
| #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S 0 |
| #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_GET(_var) \ |
| (((_var) & HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_M) >> \ |
| HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S) |
| #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_SET(_var, _val) \ |
| do { \ |
| HTT_CHECK_SET_VAL(HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO, _val); \ |
| ((_var) |= ((_val) << HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_LO_S)); \ |
| } while (0) |
| |
| #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_M 0xffffffff |
| #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S 0 |
| #define HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_GET(_var) \ |
| (((_var) & HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_M) >> \ |
| HTT_SRING_SETUP_TAIL_OFFSET32_REMOTE_BASE_ADDR_HI_S) |
|