)]}' { "log": [ { "commit": "91af6468f66ad9b4219ad6333756015b54bdd109", "tree": "28d15ee27c22afe5d633c8e2cb30f23c595e5c70", "parents": [ "ce364eb942da52fdbd18b80ad34b4442a02e08b2" ], "author": { "name": "Peter Nordström", "email": "pnordstrom@google.com", "time": "Fri Nov 20 13:56:13 2020 -0800" }, "committer": { "name": "Peter Nordström", "email": "pnordstrom@google.com", "time": "Fri Nov 20 13:56:13 2020 -0800" }, "message": "Fix derating conflict issue\n\nApplying patch fix-derating-conflict-issue-L4.14.98_GA2.0.0.patch\nreceived from Frank at NXP on Nov 20, 2020.\n\nChange-Id: I518ca7563f5d724c2f6b86cedeb35507742df358\n" }, { "commit": "ce364eb942da52fdbd18b80ad34b4442a02e08b2", "tree": "9fdcdbe06130a460c63d322ce8890a27d16c3f56", "parents": [ "fa12a64db56a8b3101e78af6f9f19b71e14d5a48" ], "author": { "name": "Leonid Lobachev", "email": "leonidl@google.com", "time": "Mon Dec 16 16:49:31 2019 -0800" }, "committer": { "name": "Leonid Lobachev", "email": "leonidl@google.com", "time": "Mon Dec 16 16:49:31 2019 -0800" }, "message": "Remove unused line.\n\nChange-Id: Ib009e65265378c143dbf65866ad5392e38f3fc7c\n" }, { "commit": "fa12a64db56a8b3101e78af6f9f19b71e14d5a48", "tree": "802f21b2c2afa3d3e2504d0ed629df583b115d9d", "parents": [ "99958d81cc6e1031b1465d6ecae4af2cef2eec86" ], "author": { "name": "Leonid Lobachev", "email": "leonidl@google.com", "time": "Wed Nov 06 13:35:49 2019 -0800" }, "committer": { "name": "Leonid Lobachev", "email": "leonidl@google.com", "time": "Mon Dec 16 15:05:36 2019 -0800" }, "message": "Apply MLK-22578 from imx8mn to imx8mq code\n\nMLK-22578 plat: imx8mn: Fix the race condition during cpu hotplug\nCPU hotplug \u0026 cpuidle have some race condition when doing CPU hotplug\nstress test. different CPU cores have the chance to access the same\nGPC register(A53_AD), so lock is necessary to do exlusive access.\n\nChange-Id: I3ff5cbe6bf333c9555591a313c1a41dbdb688cee\nSigned-off-by: Leonid Lobachev \u003cleonidl@google.com\u003e\n" }, { "commit": "99958d81cc6e1031b1465d6ecae4af2cef2eec86", "tree": "1a5ac6237ab9891e1123330fa111f3d58978bdd2", "parents": [ "413e93e10ee4838e9a68b190f1468722f6385e0e" ], "author": { "name": "Leonid Lobachev", "email": "leonidl@google.com", "time": "Fri Oct 18 14:51:35 2019 -0700" }, "committer": { "name": "Leonid Lobachev", "email": "leonidl@google.com", "time": "Tue Oct 22 10:45:43 2019 -0700" }, "message": "plat: imx8mq: enable normal peripheral irq wake system\n\nChange-Id: I43767e534f70a5f2dc5975c3af9e8e4f8b41ae47\nSigned-off-by: Leonid Lobachev \u003cleonidl@google.com\u003e\n" }, { "commit": "413e93e10ee4838e9a68b190f1468722f6385e0e", "tree": "99378963dca68fae132a073cec96320c8f027f94", "parents": [ "6cebbc2f0d7078aa7ca772c8e86e058ea6e1ba18" ], "author": { "name": "Nitin Garg", "email": "nitin.garg@nxp.com", "time": "Wed Jul 17 09:29:32 2019 +0800" }, "committer": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Wed Jul 17 11:36:51 2019 +0800" }, "message": "Fix A72 L2 DATA latency settings.\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n(cherry picked from commit 91e7cb2b7be53a20b16ade22f954f3001574ffc8)\n" }, { "commit": "6cebbc2f0d7078aa7ca772c8e86e058ea6e1ba18", "tree": "4369784a44048f21b301596e69dfc902dff29d33", "parents": [ "c2eba347a9dbb6748afedf3c7acba9c30b91a45b" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jul 12 15:05:51 2019 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jul 12 15:33:04 2019 +0800" }, "message": "MLK-22207 plat: imx8m: Fix the data sync issue in dram dvfs flow\n\nExplict memory barrier(DSB) is necessary to make sure\nother cores observe the correct flags updated by the primary\ncore before the primary begins doing DRAM DVFS.\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\n(cherry picked from commit dac8d677447c153cd148fee9e35445c24162f190)\n" }, { "commit": "c2eba347a9dbb6748afedf3c7acba9c30b91a45b", "tree": "354f0efa4241b4c7d0ac5259f1f0e446bfc3cce5", "parents": [ "1ce3513172d711c416524d961b841e28cf337cec" ], "author": { "name": "Ji Luo", "email": "ji.luo@nxp.com", "time": "Mon Apr 01 13:54:45 2019 +0800" }, "committer": { "name": "Ji Luo", "email": "ji.luo@nxp.com", "time": "Mon Apr 01 14:07:55 2019 +0800" }, "message": "imx8mq: minor fix in gpio functions\n\nThis patch fix type mismatch and dead codes in gpio functions.\n\nTest: build and boot on AIY 1G DDR board.\n\nSigned-off-by: Ji Luo \u003cji.luo@nxp.com\u003e\n" }, { "commit": "1ce3513172d711c416524d961b841e28cf337cec", "tree": "1d5163bf8f2120a0bbd9bbdc459ddc99f6f0f8e8", "parents": [ "1cb68fa0a0dd8bc00b9871b51d4c4e1d0a827b2d" ], "author": { "name": "Ji Luo", "email": "ji.luo@nxp.com", "time": "Fri Mar 29 13:40:46 2019 +0800" }, "committer": { "name": "Ji Luo", "email": "ji.luo@nxp.com", "time": "Mon Apr 01 13:07:39 2019 +0800" }, "message": "imx8mq: Add support for AIY 1G ddr board\n\nTEE will be loaded to 0x7e000000 for AIY 1G ddr board,\ndistinguish different baseboard by the board id and set\ndifferent tee address accordingly.\n\nTest: build and boot ok for both AIY 1G and 3G ddr board.\n\nSigned-off-by: Ji Luo \u003cji.luo@nxp.com\u003e\n" }, { "commit": "1cb68fa0a0dd8bc00b9871b51d4c4e1d0a827b2d", "tree": "45d2453b75d38a96383d80f8112a2626055a702e", "parents": [ "4b273d520d4b25d0aae2aa37138dd06386d96872" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Thu Mar 21 20:06:17 2019 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Thu Mar 21 20:12:52 2019 +0800" }, "message": "MLK-21219 plat: imx8m: fix the ddr4 retention hang\n\nFix the ddr4 retention exit hang caused by improper\ninit flow.\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\n(cherry picked from commit ae126e71754c9c1ff758d2b12ff74e3d3f5680b9)\n" }, { "commit": "4b273d520d4b25d0aae2aa37138dd06386d96872", "tree": "2547ceb1b1a29c77459ae7dca6eaf78bc598a47c", "parents": [ "1cedd17dfe771ae5b247bc3e21df60fd5f77609b" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Thu Mar 14 17:34:01 2019 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Thu Mar 14 17:47:39 2019 +0800" }, "message": "plat: imx: fix the license issue for imx8m\n\nClean up \u0026 Fix the license issue\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 1a43400e8295d22851f96527beb0dd328fd687cf)\n" }, { "commit": "1cedd17dfe771ae5b247bc3e21df60fd5f77609b", "tree": "2ff72646322544e4a367171d29bcab617474de11", "parents": [ "ff7234ad125f913ed6e92bc770ecbc14206d7af8" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Wed Mar 13 17:03:30 2019 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Wed Mar 13 17:23:10 2019 +0800" }, "message": "MLK-21035 plat: imx: fix the license issue\n\nclean up \u0026 fix the license issue\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\n(cherry picked from commit ec9654ad35f560440a183771d0b802988971b7c7)\n" }, { "commit": "ff7234ad125f913ed6e92bc770ecbc14206d7af8", "tree": "fa91fa7a9f665bb44e01002b40f7a32c21b83741", "parents": [ "6bfe0c83527e2895e75bf72e48413c4a79ce6077" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Tue Mar 12 08:41:36 2019 +0800" }, "committer": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Wed Mar 13 08:13:47 2019 +0800" }, "message": "Revert \"imx: set CPU boot entry for partition reboot\"\n\nThis reverts commit d4a0970cfea5f0dd6f88a5c202b90ce31e6baecc.\n\nSCFW already supported OCRAM retention, so no need to change\nprimary CPU\u0027s entry.\n\n(cherry picked from commit 669492786bbb397252308d0005625176382caff3)\n" }, { "commit": "6bfe0c83527e2895e75bf72e48413c4a79ce6077", "tree": "285457cb356783eea9ebbc09ca99cb2c64bfc165", "parents": [ "68eebd8d804e4c626c2a2e42377bb49c3f4ddbf6" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Tue Mar 12 08:40:35 2019 +0800" }, "committer": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Wed Mar 13 08:13:47 2019 +0800" }, "message": "Revert \"imx: keep boot device info for partition reboot\"\n\nThis reverts commit 8673a8e5abfea5de60680823467ac224526b530f.\n\nSCFW already supported OCRAM retention, so no need to change\nprimary CPU\u0027s boot entry.\n\n(cherry picked from commit e49e1c05893f1d6394361761ce462094796c9044)\n" }, { "commit": "68eebd8d804e4c626c2a2e42377bb49c3f4ddbf6", "tree": "ac63f30a548ef1515441272d372f8ca784ea70dc", "parents": [ "d9591cd9d212afe94e3a488b4889e05be13c7999" ], "author": { "name": "Ji Luo", "email": "ji.luo@nxp.com", "time": "Thu Feb 28 19:39:28 2019 +0800" }, "committer": { "name": "Ji Luo", "email": "ji.luo@nxp.com", "time": "Tue Mar 05 16:21:01 2019 +0800" }, "message": "MA-14173-4 Enable trusty for imx8mq_aiy\n\nConfig the base address(0xfe00_0000) and size(0x200_0000)\nfor Trusty OS to enable it on AIY board.\n\nTest: Trusty OS boots up ok.\n\nChange-Id: Ia7ed33447fc7b84ba2005d332c1379564fc647c1\nSigned-off-by: Ji Luo \u003cji.luo@nxp.com\u003e\n" }, { "commit": "d9591cd9d212afe94e3a488b4889e05be13c7999", "tree": "6f873dc55ee556a6ae80b58499f1ada7fba48282", "parents": [ "1472bb775ebba53a6bf298638df2255645755b45" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Fri Mar 01 14:48:28 2019 +0800" }, "committer": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Mon Mar 04 09:08:34 2019 +0800" }, "message": "imx: initialize register value before writting MU_SR register\n\nMU_SR register bit[30] is cold boot flag passed from SCU,\nw0 is random value and would clear the flag incorrectly,\nand cause system partition reboot fail if Linux is in suspend.\nSo this patch initializes it to 0x80000000 which is exactly\nthe same with first time board power up before writting to MU_SR\nregister.\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n(cherry picked from commit 3bbb1bc8f15d56f0d071919fb80c778d5d67f969)\n" }, { "commit": "1472bb775ebba53a6bf298638df2255645755b45", "tree": "a3f07e9e33159680937f33b0a9f48c0699150d1e", "parents": [ "4245a8568555e97ecb55e1e3c547bddab843fe20" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Wed Feb 27 17:12:43 2019 +0800" }, "committer": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Wed Feb 27 17:16:22 2019 +0800" }, "message": "imx: keep boot device info for partition reboot\n\nThe boot device info should be kept during partition reboot,\nthe boot device ownership is changed after partition management\nin ATF, so calling sc_pm_set_boot_parm() with boot device\nparameter will fail in PSCI initialization phase, moving it\nto bl31_early_platform_setup2() can make it work, correct them.\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n(cherry picked from commit d0c4a4e2c2d2618bef7c469c11ebeeb98174630a)\n" }, { "commit": "4245a8568555e97ecb55e1e3c547bddab843fe20", "tree": "6894437495de80748095b0743d2612f70dbaf193", "parents": [ "b95e51978b68f8d31c64eb4431a1d0104cca23de" ], "author": { "name": "Ye Li", "email": "ye.li@nxp.com", "time": "Wed Feb 27 00:07:10 2019 -0800" }, "committer": { "name": "Ye Li", "email": "ye.li@nxp.com", "time": "Wed Feb 27 00:52:57 2019 -0800" }, "message": "MLK-20986 imx8: Not protect OCRAM for rev A\n\nOn iMX8 Rev A the OCRAM is used to pass over ROM info, and u-boot\nneeds to access it. So we can\u0027t assign the OCRAM to ATF partition.\nThis will cause boot hang.\n\nRev A does not support SPL, so it is ok to not protect the OCRAM.\n\nSigned-off-by: Ye Li \u003cye.li@nxp.com\u003e\nReviewed-by: Peng Fan \u003cpeng.fan@nxp.com\u003e\n(cherry picked from commit c9a168bfd16e06b4d6b9f94185910023e4923cf2)\n" }, { "commit": "b95e51978b68f8d31c64eb4431a1d0104cca23de", "tree": "0b861169fccf34ab8f50f5d807ba7fe9bb7bb576", "parents": [ "08c79a85d2493ac6d47475e4aa84a2f4111f91ec" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Wed Feb 27 14:43:14 2019 +0800" }, "committer": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Wed Feb 27 15:26:01 2019 +0800" }, "message": "imx: set CPU boot entry for partition reboot\n\nWith SPL running on OCRAM, when linux suspend, OCRAM\nwill lose power and if partition reboot is started from\nSPL, system will hang as the OCRAM data lost, so for\npartition reboot, the CPU boot entry can be set to\nbe from ATF BL31 entry directly, SCFW exposes such API\nfor this scenario.\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n(cherry picked from commit d4a0970cfea5f0dd6f88a5c202b90ce31e6baecc)\n" }, { "commit": "08c79a85d2493ac6d47475e4aa84a2f4111f91ec", "tree": "5e6b754e33c9452bc4bfbbaff091d7ae30bfd29c", "parents": [ "b770337f7ccf20fa207549fe68b1b832a397f37b" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Wed Feb 27 14:40:24 2019 +0800" }, "committer": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Wed Feb 27 15:26:01 2019 +0800" }, "message": "imx: update SCFW APIs\n\nUpdate SCFW APIs to SCFW commit:\ne7a99eb96207 (\"SCF-351: Add API to change boot parms.\")\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n(cherry picked from commit 22a97387c5450c14c9fb61b0a3ed184c06679694)\n" }, { "commit": "b770337f7ccf20fa207549fe68b1b832a397f37b", "tree": "66d3c43f440b48fba8815fcb60ed8f41eb29ce73", "parents": [ "881cbc02c3b56f1fc5dcca0814b0cd29915861c0" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Wed Feb 27 14:38:15 2019 +0800" }, "committer": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Wed Feb 27 15:26:01 2019 +0800" }, "message": "imx: fix partition reboot fail when debug console is enabled\n\nWith partition reboot enabled, console_list variable which is\nlocated in data section is NOT reset, system will be busy looping\nin early console operation of flush_loop() if console_list is\nNOT 0 while HW console is NOT initialized, so we have to clear\nthis variable to make partition reboot work.\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n(cherry picked from commit 8328fcf83527b2258c1a1b290efa737be7a63171)\n" }, { "commit": "881cbc02c3b56f1fc5dcca0814b0cd29915861c0", "tree": "18f13b048ce64ff0ac2b72df473feb86fd2c8e7c", "parents": [ "fc3c36f4bc8e7f9fdcf297845b1ae3527615ed75" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Wed Feb 27 14:33:29 2019 +0800" }, "committer": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Wed Feb 27 15:25:48 2019 +0800" }, "message": "console: aarch64: expose console_list for i.MX partition reboot\n\nFor i.MX SoCs with system controller inside, partition reboot\nis supported, and when reboot, CPU will be reset to ATF entry\ndirectly, the data section is NOT reset, console_list variable\nneeds to be initialized to 0 to make it work, otherwise, system\nwill be busy looping in flush_loop(). So expose console_list\nfor i.MX platforms to initialize this variable.\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n(cherry picked from commit 7802cd70d8670565612ba4c8fcfe0df84195f370)\n" }, { "commit": "fc3c36f4bc8e7f9fdcf297845b1ae3527615ed75", "tree": "c680e4111b4cd0c1510332b0b12bd58996eda657", "parents": [ "79e69389ab76a9d5f86795a631033eda26f8244a" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Tue Feb 26 10:12:35 2019 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Tue Feb 26 16:05:42 2019 +0800" }, "message": "plat: imx8mm: enlarge the max_xlat_table for debug build\n\ncurrently MAX_XLAT_TABLE size is not enough for debug build,\nso enlarge it to make it works.\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 95095ba95a70a3d2c2b0036dde655d6c2229299e)\n" }, { "commit": "79e69389ab76a9d5f86795a631033eda26f8244a", "tree": "023c5d145b39b25900497a31fa0e1df1edbd70fc", "parents": [ "b51b399aaed06fd40476b2f5af385127404ab2a1" ], "author": { "name": "Nitin Garg", "email": "nitin.garg@nxp.com", "time": "Thu Feb 14 21:48:32 2019 -0600" }, "committer": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Thu Feb 21 10:11:37 2019 +0800" }, "message": "imx8qm: turn off A53 cluster for cpu hotplug\n\nThe issue of A53 cluster runtime power ON/OFF has been\nidentified as fifo reset issue, and there is software\nworkaround to avoid such issue and A53 cluster now can\nbe turned OFF.\n\nSigned-off-by: Nitin Garg \u003cnitin.garg@nxp.com\u003e\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n(cherry picked from commit 77de1ee8108781ee373613606b94e6ad55ae8ccc)\n" }, { "commit": "b51b399aaed06fd40476b2f5af385127404ab2a1", "tree": "d270fe0f5c91301bcf6ced046e6429c7c53fbf8f", "parents": [ "e4a5b4a8d2fe31dca0c343e1a27e5ad33d0173a3" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Fri Feb 15 11:47:19 2019 +0800" }, "committer": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Fri Feb 15 16:34:44 2019 +0800" }, "message": "imx: update SCFW APIs\n\nUpdate SCFW APIs to SCFW commit:\n004247e14afc (\"SCF-341 Fix bug in setting large slice clock divider\")\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n(cherry picked from commit b6c41566e85ecb964522793d4005933695e6926b)\n" }, { "commit": "e4a5b4a8d2fe31dca0c343e1a27e5ad33d0173a3", "tree": "ab1dcb4ca3a4e9314463d4544ff7005666bda558", "parents": [ "e251ea3f6b2fa555aaad5e5a9af7b6fb4588e526" ], "author": { "name": "Haoran.Wang", "email": "elven.wang@nxp.com", "time": "Mon Oct 29 20:12:03 2018 +0800" }, "committer": { "name": "Ji Luo", "email": "ji.luo@nxp.com", "time": "Tue Feb 12 15:56:08 2019 +0800" }, "message": "MA-13239 imx8qm: Touch correct pad for UART0\n\nDue imx8qm_mek\u0027s UART0_RTS_B and UART0_CTS_0 pad\nreuse to be the UART2 for base bard which operated by\nM4_1, so don\u0027t touch these two pads in ATF.\n\nSigned-off-by: Haoran.Wang \u003celven.wang@nxp.com\u003e\nAcked-by: Pete Zhang \u003cpete.zhang@nxp.com\u003e\n" }, { "commit": "e251ea3f6b2fa555aaad5e5a9af7b6fb4588e526", "tree": "90df640ec814b16d6b7448983390c8a266fb10a9", "parents": [ "854729ba8d89dd4bcbd2c98d513416c318d8c121" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Tue Feb 12 14:58:34 2019 +0800" }, "committer": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Tue Feb 12 15:54:18 2019 +0800" }, "message": "gic: make sure ProcessorSleep bit clear successfully\n\nGICR_WAKER.ProcessorSleep can only be set to zero when:\n— GICR_WAKER.Sleep bit[0] \u003d\u003d 0.\n— GICR_WAKER.Quiescent bit[31] \u003d\u003d 0.\n\nOn some platforms, when system reboot with GIC in sleep\nmode but with power ON, such as on NXP\u0027s i.MX8QM, Linux\nkernel enters suspend but could be requested to reboot,\nand GIC is in sleep mode and it is inside a power domain\nwhich is ON in this scenario, when CPU reset, the GIC\ndriver trys to set CORE\u0027s redistributor interface to awake,\nwith GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31]\nboth set, the ProcessorSleep bit[1] will never be clear\nand cause system hang.\n\nThis patch makes sure GICR_WAKER.Sleep bit[0] and\nGICR_WAKER.Quiescent bit[31] are both zeor before clearing\nProcessorSleep bit[1].\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n(cherry picked from commit 4436f3a49a47a778d7a30afb6ef2b0ef3f1f21c5)\n" }, { "commit": "854729ba8d89dd4bcbd2c98d513416c318d8c121", "tree": "b5168da7959779a23afe9f52740947d568f8531e", "parents": [ "96d33120bb57895db73e669ef0aeccde0d4875d5" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Mon Feb 11 23:43:58 2019 +0800" }, "committer": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Mon Feb 11 23:43:58 2019 +0800" }, "message": "imx: enable IRQ steer wakeup source support\n\nEnable IRQ steer wakeup source support for Linux kernel\nwakeup sources like debug UART wakeup etc..\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n" }, { "commit": "96d33120bb57895db73e669ef0aeccde0d4875d5", "tree": "321077eb1cd70b7c3de5ffcde0629b98d3b48d51", "parents": [ "30b5a61f25e7a928046d593c5d631e5da70eebdf" ], "author": { "name": "Ye Li", "email": "ye.li@nxp.com", "time": "Wed Dec 26 04:59:56 2018 -0800" }, "committer": { "name": "Ye Li", "email": "ye.li@nxp.com", "time": "Sun Feb 10 23:08:46 2019 -0800" }, "message": "imx8qm/qxp: Protect the lower 96K ocram used for SPL\n\nBecause the partition reboot won\u0027t reload the first level bootloader (SPL),\nthe SPL won\u0027t be authenticated. Users can corrupt the SPL image to break\nthe boot trust chain in secure boot if we don\u0027t protect that OCRAM area.\n\nThis patch configures the memory area from 0x0 to 0x118000 only accessed by\nsecure partition (ATF and OPTEE). Non-secure partitions (u-boot and kernel)\ncan\u0027t access it.\n\nSigned-off-by: Ye Li \u003cye.li@nxp.com\u003e\n(cherry picked from commit 1eff7d3ef6f121782e56bb1807744ede48b8580b)\n" }, { "commit": "30b5a61f25e7a928046d593c5d631e5da70eebdf", "tree": "501d265472ebba8b3842c300fc7b442eee3d5bd7", "parents": [ "79017d7bcfa207f05794bdce3254b24cb4b5ccc7" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Sat Feb 09 21:00:54 2019 +0800" }, "committer": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Sun Feb 10 08:45:26 2019 +0800" }, "message": "imx: update SCFW APIs\n\nUpdate SCFW APIs to SCFW commit:\n5c03342369e8 (\"SCF-105: Change links in wiki index.\")\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n" }, { "commit": "79017d7bcfa207f05794bdce3254b24cb4b5ccc7", "tree": "2343f0c70a105bf24f4e5590ef9f11d07c83870d", "parents": [ "fca04f644081ee07bb04127f1bb10efcdf7f0f87" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Thu Nov 22 02:45:14 2018 +0100" }, "committer": { "name": "Franck LENORMAND", "email": "franck.lenormand@nxp.com", "time": "Thu Feb 07 16:54:44 2019 +0100" }, "message": "TEE-330-4: i.MX8QM: OP-TEE: Pass boot info to u-boot\n\nIf ATF loads OP-TEE, it will pass OP-TEE base\naddress and size to the u-boot through boot information.\nThis will help u-boot update device tree accordingly.\nNote that u-boot on i.MX 8QxP does not need this information\nto configure memory mapping. Query to the SC Firmware\nis used instead.\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\n(cherry picked from commit 70c1d422e520f8f1c201a7e4fe22870832240db7)\n" }, { "commit": "fca04f644081ee07bb04127f1bb10efcdf7f0f87", "tree": "6fbf4b5c7f73c79a8c8b5c3f3c03bf703dad9dcc", "parents": [ "6632b7a1078a50601225f5ba0c14b2cae57535ff" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Thu Nov 22 02:43:41 2018 +0100" }, "committer": { "name": "Franck LENORMAND", "email": "franck.lenormand@nxp.com", "time": "Thu Feb 07 16:54:44 2019 +0100" }, "message": "TEE-330-3: i.MX8QM: OP-TEE add share memory\n\nConfigure OP-TEE Share memory to be accessible by OS.\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\n(cherry picked from commit b2d0c8530c75bb77450372114229cadd8555780b)\n" }, { "commit": "6632b7a1078a50601225f5ba0c14b2cae57535ff", "tree": "eece206158144f05f1a960251cde6ab986e60eb4", "parents": [ "fb44dedd4f994770185b48af017582e44f45c685" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Thu Nov 22 02:41:09 2018 +0100" }, "committer": { "name": "Franck LENORMAND", "email": "franck.lenormand@nxp.com", "time": "Thu Feb 07 16:54:44 2019 +0100" }, "message": "TEE-330-2: i.MX8QM: TEE Fix BL32_SIZE\n\nFix size of BL32 (currently is 32MB).\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\n(cherry picked from commit 5087a9cda77b3c6a5566e4a9520ab476bfe9154a)\n" }, { "commit": "fb44dedd4f994770185b48af017582e44f45c685", "tree": "9f5233c886fa71aca9680957bf0d7e3ada03924f", "parents": [ "490b0dd6bac59338713a3df28678f1a6ad09f781" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Thu Nov 22 02:39:19 2018 +0100" }, "committer": { "name": "Franck LENORMAND", "email": "franck.lenormand@nxp.com", "time": "Thu Feb 07 16:54:44 2019 +0100" }, "message": "TEE-330-1: OP-TEE: Add support for i.MX 8QM\n\nReuse Trusty support for OP-TEE\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\n(cherry picked from commit a558c8fb87171f4ebcc44bb0b8aa699c989a2a7d)\n" }, { "commit": "490b0dd6bac59338713a3df28678f1a6ad09f781", "tree": "bfe993161b47c7dd2f5d38b894177e49220b8cd4", "parents": [ "7cb7adfa78f3dadc630cdffba6063a7973e95269" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Tue Nov 20 22:19:21 2018 +0100" }, "committer": { "name": "Franck LENORMAND", "email": "franck.lenormand@nxp.com", "time": "Thu Feb 07 16:54:44 2019 +0100" }, "message": "TEE-329-4: OP-TEE: Pass boot info to u-boot\n\nIf ATF loads OP-TEE, it will pass OP-TEE base\naddress and size to the u-boot through boot information.\nThis will help u-boot update device tree accordingly.\nNote that u-boot on i.MX 8QxP does not need this information\nto configure memory mapping. Query to the SC Firmware\nis used instead\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\n(cherry picked from commit e80fe229192578120a3ba98ae26fd3dbf121538f)\n" }, { "commit": "7cb7adfa78f3dadc630cdffba6063a7973e95269", "tree": "b3e153867fa80ff3562304c0344b8de6b74d7eec", "parents": [ "007d1272283c137cc4939adfbfc49531351ec299" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Mon Nov 19 17:58:06 2018 +0100" }, "committer": { "name": "Franck LENORMAND", "email": "franck.lenormand@nxp.com", "time": "Thu Feb 07 16:54:44 2019 +0100" }, "message": "TEE-329-3: OP-TEE add share memory\n\nconfigure OP-TEE Share memory to be accessible by OS.\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\n(cherry picked from commit 0b5eeb7e0dbe50ebd7f3d0ce66047569504e9d52)\n" }, { "commit": "007d1272283c137cc4939adfbfc49531351ec299", "tree": "a00a79bab1219db38925b098f04f486098df58b8", "parents": [ "b3ecd1ba4cf9aef7b996897259b01d5aa3a7f4ac" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Mon Nov 19 17:56:12 2018 +0100" }, "committer": { "name": "Franck LENORMAND", "email": "franck.lenormand@nxp.com", "time": "Thu Feb 07 16:54:44 2019 +0100" }, "message": "TEE-329-2: Fix BL32_SIZE\n\nfix size of BL32 (currently is 32MB)\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\n(cherry picked from commit f66251dedef31750ff7be4c0e404b77d0a8fb1c4)\n" }, { "commit": "b3ecd1ba4cf9aef7b996897259b01d5aa3a7f4ac", "tree": "41a4c9d9be052bf18aef3394272af8c202011a09", "parents": [ "d82c0e65e74ce8b650ea3237a02249246080840d" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Mon Nov 19 17:53:05 2018 +0100" }, "committer": { "name": "Franck LENORMAND", "email": "franck.lenormand@nxp.com", "time": "Thu Feb 07 16:54:44 2019 +0100" }, "message": "TEE-329-1: OP-TEE: Add support for i.MX 8QxP\n\nreuse Trusty support for OP-TEE\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\n(cherry picked from commit 6e2885a262b94bdeb8face851012f58ed32e86a9)\n" }, { "commit": "d82c0e65e74ce8b650ea3237a02249246080840d", "tree": "aa1d379e62bbd0d5f0290bb3a8e82ba2180f0897", "parents": [ "bfab3524bcd0367fd4873c7ed5b2eed62e561b03" ], "author": { "name": "Ji Luo", "email": "ji.luo@nxp.com", "time": "Fri Oct 26 17:26:31 2018 +0800" }, "committer": { "name": "Franck LENORMAND", "email": "franck.lenormand@nxp.com", "time": "Thu Feb 07 16:54:44 2019 +0100" }, "message": "imx8q: [trusty] Kick CAAM power\n\nJR0 and JR1 of CAAM are owned by SECO, only kick the power\nof JR2 and JR3 here and assign the resources to be accessed\nby secure world.\n\nSigned-off-by: Ji Luo \u003cji.luo@nxp.com\u003e\n(cherry picked from commit 4f00df596a80cb4b4539d228332d976cf38d4183)\n" }, { "commit": "bfab3524bcd0367fd4873c7ed5b2eed62e561b03", "tree": "6d692335b089540ab0bc5cee4f0e493e85a08a1d", "parents": [ "36ad60e46fd94eac7646218ae2b3e760bcfc33d6" ], "author": { "name": "Luo Ji", "email": "ji.luo@nxp.com", "time": "Thu Oct 18 21:08:38 2018 +0800" }, "committer": { "name": "Franck LENORMAND", "email": "franck.lenormand@nxp.com", "time": "Thu Feb 07 16:54:44 2019 +0100" }, "message": "iMX8Q: Don\u0027t copy tee after fit is enabled\n\nTee(Trusty Os) will be stored in fit for Android and Android Auto\nso we don\u0027t need to copy it anymore, this will save some boot time.\n\nSigned-off-by: Luo Ji \u003cji.luo@nxp.com\u003e\n(cherry picked from commit 4cb7c6fbd251ae2603f470fb23c526f73acbf7f9)\n" }, { "commit": "36ad60e46fd94eac7646218ae2b3e760bcfc33d6", "tree": "6c6f8df8c416aaeb2bc7a71f1dcba2ef05a4e7cb", "parents": [ "da4daa49a6c8d0d4b845e396ee92e5f09e1ebae5" ], "author": { "name": "Haoran.Wang", "email": "elven.wang@nxp.com", "time": "Mon Sep 10 11:03:26 2018 +0800" }, "committer": { "name": "Franck LENORMAND", "email": "franck.lenormand@nxp.com", "time": "Thu Feb 07 16:54:44 2019 +0100" }, "message": "MA-11015 Support Trusty OS on imx8qm/qxp\n\nThe Trusty OS binary will be installed into\ncontainer.img and loaded into 0x84000000.\n\nDue Trusty OS addresss is in 0xfe000000 which\nROM cannot reach, so use ATF to copy it into\nthe target address.\nMapped the BL32 code into MMU due the Trusty\nSPD need to check the code status and decide\nthe CPU executing mode.\n\nTo reserve and protect the memory for secure\nworld, modify the partition code to keep\nBL32 spaces in secure_part.\n\nSigned-off-by: Haoran.Wang \u003celven.wang@nxp.com\u003e\nReviewed-by: Ye Li \u003cye.li@nxp.com\u003e\n(cherry picked from commit d305ece47bf3e90b5008bf5932583ee2a772650b)\n" }, { "commit": "da4daa49a6c8d0d4b845e396ee92e5f09e1ebae5", "tree": "b66a74339ea27ab3cff3d0cd9627972e9418c9b9", "parents": [ "bdac7abf2d9350b9dec79ab33650699fb718d0a4" ], "author": { "name": "Peng Fan", "email": "peng.fan@nxp.com", "time": "Tue Jun 26 20:33:01 2018 +0800" }, "committer": { "name": "Franck LENORMAND", "email": "franck.lenormand@nxp.com", "time": "Thu Feb 07 16:54:44 2019 +0100" }, "message": "imx8: postpone moving resources to non-secure partition\n\nWith flash_uboot_cm4ddr in imx-mkimage, the m4 code will access ddr.\nHowever after m4 core moved to non-secure partition, the ddr memory\nis still in secure partition. Then m4 core will fault.\n\nSo postpone moving resources including m4 core, until other resources,\nsuch as memory/pin moved to non-secure partition.\n\nSigned-off-by: Peng Fan \u003cpeng.fan@nxp.com\u003e\n(cherry picked from commit 1c8ce0ad5f583ec41026d4ab5bef622f1b45aecd)\n(cherry picked from commit 5b026e05b8f71b3d86da0953c5ca196d5ba5cc66)\n" }, { "commit": "bdac7abf2d9350b9dec79ab33650699fb718d0a4", "tree": "7e1eeaa2b404889dd850c07b89b88278443efb4c", "parents": [ "d84270b8d0c6f17a5b0853f33f5895c97ef2f443" ], "author": { "name": "Peng Fan", "email": "peng.fan@nxp.com", "time": "Thu May 31 13:51:23 2018 +0800" }, "committer": { "name": "Franck LENORMAND", "email": "franck.lenormand@nxp.com", "time": "Thu Feb 07 16:54:44 2019 +0100" }, "message": "imx8qxp: move M4 to OS part at last\n\nWith default configuration, M4 and A35 in one partition, M4 is loaded by ROM.\n\"err \u003d sc_rm_move_all(ipc_handle, secure_part, os_part, true, true);\"\nM4 core will first be moved to non-secure OS part, then the resource used\nby M4 will be moved to non-secure OS part later. But before the resource be\nmoved to non-secure OS part, M4 core is still running, so a non-secure M4\ncore access a secure resource will trigger error in M4 side.\n\nFirst mark M4 core as non-movable, after all other resoures moved to OS\npart, move M4 to OS part. No need to check whether M4 is created a new\npartition by SCFW, if a partition already created, the call to mark\nM4 as non-removable will fail, because it M4 is in its own partition.\n\nSigned-off-by: Peng Fan \u003cpeng.fan@nxp.com\u003e\n(cherry picked from commit 44e209cb87f078abc78839c5e138aae5122ddd78)\n" }, { "commit": "d84270b8d0c6f17a5b0853f33f5895c97ef2f443", "tree": "6d0c3e639f78bd23e0822921514aecce1adf1c09", "parents": [ "d6f509e8b2e20279f6420b395636dffe110765c0" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 18 15:26:58 2019 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx8m: Add dram pll lock check before retention exit\n\nAdd the dram pll lock check to make the pll is already\nlocked bofore dram exit from retention mode.\n\naddtionally, the DDR4 reset flow need some change to\nmake sure DRAM exit retention safely.\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 858e2141138d87fe6072f8ba0321b3963ae9630c)\n" }, { "commit": "d6f509e8b2e20279f6420b395636dffe110765c0", "tree": "495bc7a5a4f1e4869e7b096c500f73ea13106ed2", "parents": [ "5b2e43658b4acaa74ab16419a4b3d436a08c222c" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 18 15:21:11 2019 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx8mm: update the stby_count setting\n\nThe reset value of the STBY_COUNT is 0x0, so\nit means GPC will wait for 4 ckil(32K) clock cycle\nbefore checking the PMIC ready signal. increase\nthis value to 0x5, 128 ckil to make sure PMIC\noutput voltage is stable before GPC continue\nto finish the DSM exit flow.\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 94f65be918f91df676f0e61c4fef97dfd31e168f)\n" }, { "commit": "5b2e43658b4acaa74ab16419a4b3d436a08c222c", "tree": "3c61b8c486dcf4e1958560d086be8c8fc921c06e", "parents": [ "60750a1fca91721e11234580b5b9f5d1bdd7dfcb" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 18 14:34:45 2019 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx8mm: update the cpu core and plat domain power up timming\n\nupdate the cpu core\u0026plat pup sw\u0026sw2iso timing to improve\nthe domain power up latency. set the SW\u003d0x1 and SW2ISO\nby default. this value van be changed as needed.\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 1c2c988727e736a17b69c90eebd0cd05b8b63f72)\n" }, { "commit": "60750a1fca91721e11234580b5b9f5d1bdd7dfcb", "tree": "94b0cbcff44f5cfea5cece099d3d289925e0b6c6", "parents": [ "28d3f0fa26ff11efb98281ed603b6f44cea3c6c5" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Thu Dec 13 14:40:20 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx8mm: enable rbc by default for LPM mode\n\nwhen PLAT(SCU) domain power down is enabled in\nWAIT or STOP mode. enable RBC by default to make\nsure SCU can be power down successfully even if\nthe wakeup ITQ is pending.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 5cf4479384ba41a01c7f8c63a245215213b11701)\n" }, { "commit": "28d3f0fa26ff11efb98281ed603b6f44cea3c6c5", "tree": "e7a6372bb6e0a3459004c200503dd7292bc9296c", "parents": [ "6f353c76b9273c55eb48768dcfc4ab725731b307" ], "author": { "name": "Haoran.Wang", "email": "elven.wang@nxp.com", "time": "Wed Dec 12 14:36:32 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "MA-13758 Enable Trusty OS on imx8mm\n\nUse SPD_trusty macro for Trusty OS specific\nconfiguration for imx8mm.\n\nTrusty OS will be loaded on 0xbe000000 and have 32M size\nmemory space.\n\nSigned-off-by: Haoran.Wang \u003celven.wang@nxp.com\u003e\n(cherry picked from commit c929b657f541a233d0bddf162096d0ba36d69599)\n" }, { "commit": "6f353c76b9273c55eb48768dcfc4ab725731b307", "tree": "7a4bdd68b3f31af494ab8ceb035f9e1b6fa90d0b", "parents": [ "b917e33ea9ebb359fbf5a4c39db6bdf4dab21b43" ], "author": { "name": "Olivier Masse", "email": "olivier.masse@nxp.com", "time": "Wed Oct 24 16:32:27 2018 +0200" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "MMIOT-180: ddr address is 33bit width, but rdc memory region register is 32bit. So we use [32:1] as the configuration value\n\nSigned-off-by: Olivier Masse \u003colivier.masse@nxp.com\u003e\n(cherry picked from commit a15779ce1b5c5b1213f8ff2978cdae7729c8c5c8)\n" }, { "commit": "b917e33ea9ebb359fbf5a4c39db6bdf4dab21b43", "tree": "29ba7c17bd6b90f92995cd11c5c12130ee7d0b11", "parents": [ "7fa4c205164ffb2603e27db82b0a67a59ede40ad" ], "author": { "name": "Olivier Masse", "email": "olivier.masse@nxp.com", "time": "Fri Oct 05 11:03:18 2018 +0200" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "MMIOT-152 + MMIOT-157 : move specific RDC configuration from driver to board setup\n\nSigned-off-by: Olivier Masse \u003colivier.masse@nxp.com\u003e\n(cherry picked from commit 1e61b6e298e14e0bb00854ab0240752ad6989c79)\n" }, { "commit": "7fa4c205164ffb2603e27db82b0a67a59ede40ad", "tree": "ffd1083560a17ba4a18ea62f2146abea35a96cf6", "parents": [ "68e590f2e26e78c079bde23dd365642291e62486" ], "author": { "name": "Olivier Masse", "email": "olivier.masse@nxp.com", "time": "Tue Sep 25 15:59:35 2018 +0200" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "MMIOT-152 Rebase on imx_1.5.y + imx8mm : DRM RDC config added\n\nSigned-off-by: Olivier Masse \u003colivier.masse@nxp.com\u003e\n(cherry picked from commit ac0b499ff6618e0bb4d0cdb55009f75c914d4fe7)\n" }, { "commit": "68e590f2e26e78c079bde23dd365642291e62486", "tree": "50ded29ff5c9ec74fdd5fa96a561192b2df5e349", "parents": [ "400df64914bc90a6c28d14cd39cbffeddcf7c543" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Tue Nov 13 10:36:29 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "MLK-20238-01 plat: imx: fix uninitialized value using\n\nfix Coverity: CID 5243766: Uninitialized scalar variable (UNINIT)\nissue.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 9fe5f166ab303f125975482a0ed0b7d96cbccd67)\n" }, { "commit": "400df64914bc90a6c28d14cd39cbffeddcf7c543", "tree": "c6be69d2ea7d1b09b472a2df4d509320ffa5fc82", "parents": [ "59e8d373dc8ea7da94913728229cabf64961025a" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Sat Nov 03 22:17:07 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx8mq: fix boot hang if no valid dram info\n\nIf no valid dram info to copy from DRAM, skip\ncopy the dram info.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit bbc3e45463808a8d2f69c2fd95fe46c4078f6d2e)\n" }, { "commit": "59e8d373dc8ea7da94913728229cabf64961025a", "tree": "b1c40502ffc622898b99c14b6184382102c88f20", "parents": [ "172e52d965f01b983f90fce39fe77729e6c58ffe" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Fri Nov 02 19:19:02 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx8mq: remove unused files on imx8mq\n\nremove unused files on i.MX8MQ.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit cdaae0eed8e74c49f917c88f77567b5b342004d6)\n" }, { "commit": "172e52d965f01b983f90fce39fe77729e6c58ffe", "tree": "522231b837c6faaf23e538f99ce2dfca1fcf643c", "parents": [ "2db7e17e775875f0e106afc7a11147dc4879a0bd" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Mon Oct 29 18:33:58 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx8mq: refact the dram low power code\n\nrefact the dram low power related code to make it more\nfriendly for different dram config or different board.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit c290a9e1664628a13a5e75e2400c5cc17882fbba)\n\nConflicts:\n\tplat/imx/imx8mq/sip_svc.c\n" }, { "commit": "2db7e17e775875f0e106afc7a11147dc4879a0bd", "tree": "3d224d468aec757ad4e7bb05377b3f143ad6466e", "parents": [ "eef90116aba5fa6826f19f05312f7a60f9672126" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Mon Oct 29 13:28:58 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx: Add sw workaround for the VPU\u0026GPU reset\n\nERR050044: GPU/VPU power domain on/off stress test leads\nto unexpected GPU interrupts and hang.\n\nhis is caused by no dedicated HW resets for GPU2D/3D.\nThere is one reset for whole GPUmix and GPU2D/3D has their\nown SW reset signals. The SW reset cannot be asserted while\nGPU2D/3D is in power off status. So if only GPU2D or GPU3D\nhas to be powered off and on, unknown status leads to the problem.\n\nVPU has similiar issue. So we need to assert the SW reset before\npower up the power domain.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit b6e9e2d823b1ff5f4e83fa34541003df0e70e1c9)\n" }, { "commit": "eef90116aba5fa6826f19f05312f7a60f9672126", "tree": "a6e9aa3378b731f3a75e8aee784d0e1c262dd790", "parents": [ "83453300ae9da3bc1950af087655bff5eb1d7274" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Wed Oct 24 17:51:13 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "MLK-20044 plat: imx8m: fix ddr4 dvfs hang after retention\n\nThe RFSHCTL3.refresh_mode should be set normal mode if we\nwant to disable auto refresh mode.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 7a2af8801053c087cd0f3a29ac505f4b482933a4)\n" }, { "commit": "83453300ae9da3bc1950af087655bff5eb1d7274", "tree": "40d3dc99a839b16f322ec8a2dc76bb6a3d8bf9c7", "parents": [ "53f179cdc0004cb54d03e0e95e7570fd8bbf39d9" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Fri Oct 12 16:09:50 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx8m: update the DVFS flow for DDR4\n\nUpdate the DDR4 DVFS flow\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 9aa39de9f366046a363a6754b40e9f277e73adbd)\n" }, { "commit": "53f179cdc0004cb54d03e0e95e7570fd8bbf39d9", "tree": "3d43538c722375ad4b888912abd75ccc3a8d9944", "parents": [ "80044abfcafe3cda15408d2a406d713d3845df1c" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Fri Sep 28 14:55:31 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "imx8m: Add DDR4 DVFS support\n\nAdd DDR4 DVFS support for i.MX8M. Currently, only tested on i.MX8MM.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 058a759ffed26797314bc0a52db3c440240fa6a5)\n" }, { "commit": "80044abfcafe3cda15408d2a406d713d3845df1c", "tree": "96eb2c38058d07723bdecd4f03424f2c00f0fff0", "parents": [ "38add83af4a373f934ce9337514b36db1e6f24b2" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Wed Sep 26 16:34:20 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "imx8mm: Add ddr4 retention support for imx8m\n\nAdd ddr4 retention flow for imx8m.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit e6db8a671bf8bbc107925243e394b6c5eb609fe2)\n" }, { "commit": "38add83af4a373f934ce9337514b36db1e6f24b2", "tree": "b6038b0675eda2240c0aa9910c9c4ba0c09077e3", "parents": [ "4314d4103c5288bf289e487c3ca1aefb0844b53d" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Mon Sep 17 15:48:06 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx8mq: add 100us delay after USB OTG SRC bit 0 clear\n\nAfter the SRC bit clear, we must wait for a while to make sure\nthe operation is finished.\n\nfor USB OTG, the limitations are:\n1. before system clock configuration. ipg clock runs at 12.5MHz.\n delay time should longer than 82us.\n\n2. after system clock configuration. ipg clock runs at 66.5MHz.\n delay time should longer than 15.3us.\n\nso add udelay 100 to safely clear the SRC bit 0.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 7a50e0e390349738b8987b49cc05edeadaeaddbc)\n" }, { "commit": "4314d4103c5288bf289e487c3ca1aefb0844b53d", "tree": "20d1db6a964996a13cf63a521a8fc4ec7c0e28e8", "parents": [ "f564016f9cecb33b0e51b9a4b5ecdb5ed739ea1c" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Fri Aug 10 17:49:00 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx8mm: Add support for imx8mm lpa\n\nFor i.MX8MM low power audio playback, when Linux suspend,\nM4 still needs to be active for audio playback, so system\ncan NOT enter DSM mode but only force A core platform into\nSTOP mode, PLLs/NoC/DRAM need to be active as well and MU\ninterrupt wakeup needs to be enabled for waking up Linux\nby MU message sent by M4.\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 7b60954d68e074d6d0d1a6f828f4392cf7c7137d)\n" }, { "commit": "f564016f9cecb33b0e51b9a4b5ecdb5ed739ea1c", "tree": "49a8bd20f6f79a95702f162f1b3852fa7a787435", "parents": [ "4970f87f8046c35894b6071b4492e692b5360e6d" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Thu Sep 13 13:56:41 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "imx8mq: fix soc_id issue\n\nThe chip revision should ONLY overwrite the lower 16 bits of\nsoc_id, otherwise, the cpu_is_imx8mq() API in Linux kernel\nwill be incorrect.\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n(cherry picked from commit ca98a9fca54b491755e515ca0f0d7f53a19ad74f)\n" }, { "commit": "4970f87f8046c35894b6071b4492e692b5360e6d", "tree": "b8c1ac048fb53f0ce129b5d23e3a9630ef53085b", "parents": [ "d6c6291e2356d69cd69d8b78b1c4c8ba04c4636e" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Mon Sep 10 17:34:07 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx8mm: fix the gpumix vpumix power down\n\nthe GPU/VPU mix power off is skip in previous code,\nso correct to make sure GPU/VPU mix is actually power\noff.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 102d081b3f9ac569cdff760ac7c7f7c402c3f5fe)\n" }, { "commit": "d6c6291e2356d69cd69d8b78b1c4c8ba04c4636e", "tree": "36804fe8c72d9706ff69316a38f11ffcf0931765", "parents": [ "bf8d6028959cb7aa4647a6f455f82b2187d0348e" ], "author": { "name": "Oliver Chen", "email": "Oliver.Chen@nxp.com", "time": "Wed Aug 22 15:22:04 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx8mm: Read mode register setting from ddrc\n\nRead the mode register setting from the DDRC, then we can\nmake the DVFS flow more indepent from the actual DDR config.\n\nSigned-off-by: Oliver Chen \u003cOliver.Chen@nxp.com\u003e\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 68983a41738a153a91376a7b6913ac4e87b7f57a)\n" }, { "commit": "bf8d6028959cb7aa4647a6f455f82b2187d0348e", "tree": "57a16ae90b9b529c932026262ada75d744cf9110", "parents": [ "d39a0ceaa1eddfdbe0b97942cc29b52e419d0fd4" ], "author": { "name": "Ye Li", "email": "ye.li@nxp.com", "time": "Thu Sep 06 00:06:42 2018 -0700" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "MLK-19465 imx8mq: Fix cpu rev issue on B0.1 chip\n\nOn B0.1 chip, the value is 0x1020 not 0x20, due to minor version updated.\nSo if reading the word and comparing with 0x20, the result is wrong.\n\nFix the issue by only reading low major version byte for ROM version\n\nSigned-off-by: Ye Li \u003cye.li@nxp.com\u003e\n(cherry picked from commit d4d5b6545bdd099d4d6d04c63c5035b23eda583a)\n" }, { "commit": "d39a0ceaa1eddfdbe0b97942cc29b52e419d0fd4", "tree": "146d592a023381ca959c5043df9c09b49560ae68", "parents": [ "16ff6645a7bfa280424a13367609371a04c99d50" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Mon Sep 03 14:15:27 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "imx8mq: update chip revision method for B1\n\ni.MX8MQ B1\u0027s chip revision is identified by reading\nOCOTP offset 0x40, the magic number 0xff0055aa is\nfor B1.\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n(cherry picked from commit 701e7961dfe568d724343c4e2897907cb34cc276)\n" }, { "commit": "16ff6645a7bfa280424a13367609371a04c99d50", "tree": "04c4f424dac3116a4e1c56006c8d142097653146", "parents": [ "5401ff2cb69952f05ceca11b6c4e4c48ef64c40d" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Fri Aug 31 15:47:39 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx8mq: update the ddr controller perf QoS setting\n\nupdate the ddr controller perf QoS setting on i.MX8MQ.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 7b62aea017c0366b5132dedfe9711cd094cd5cc3)\n" }, { "commit": "5401ff2cb69952f05ceca11b6c4e4c48ef64c40d", "tree": "52ff5fdf47ec722ee7df6d0e410a2dc3542a5024", "parents": [ "e52d7148fb24ee46566d28221456a360194876bc" ], "author": { "name": "Franck LENORMAND", "email": "franck.lenormand@nxp.com", "time": "Thu Aug 23 09:35:23 2018 +0200" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "MLK-18619: [MX8MM-EVK]CSU_RDC: enable csu_rdc test in ATF make the board crash\n\ncsu_rdc test in ATF makes use of GPIO 4 and 5. Unfortunatly GPIO5 is\nbeing used by u-boot. This is why u-boot crashes.\nChanging the peripherals to protect, instead of gpio4 and 5, use csu\nand rdc registers instead.\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\nSigned-off-by: Franck LENORMAND \u003cfranck.lenormand@nxp.com\u003e\n(cherry picked from commit fe1cd0abc6c57cc59312ab751dd015cb149d7100)\n" }, { "commit": "e52d7148fb24ee46566d28221456a360194876bc", "tree": "a16ffb7ead7706b90dce038b8883d008ca6bada4", "parents": [ "583c56f32da4e64a9d7874c5964f85034865b350" ], "author": { "name": "Zhang Bo", "email": "bo.zhang@nxp.com", "time": "Tue Aug 14 19:53:15 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "imx8mq:plat: add noc priority configuration entry\n\nAdd NOC configuration entry for all the module.\nKernel can configure the noc priority through this entry.\n\nSigned-off-by: Zhang Bo \u003cbo.zhang@nxp.com\u003e\n(cherry picked from commit c9638440c0899fcd0ab714520f1b4b5e4ee2fbb1)\n" }, { "commit": "583c56f32da4e64a9d7874c5964f85034865b350", "tree": "afff904b621c38ecbfe0cddb6760efa8e2160cdd", "parents": [ "fe18c14fb3cd2808110f6a4241952c9bd00890a7" ], "author": { "name": "Ye Li", "email": "ye.li@nxp.com", "time": "Sun Aug 19 23:38:04 2018 -0700" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "MLK-19263 imx8m: hab: Add check target and failsafe sip call\n\nimx_v2018.03 u-boot uses ROM\u0027s APIs: check_target and failsafe. So for iMX8M\nplatforms, we have to implement the sip calls and use ATF to call them when\nu-boot running at non-secure world.\n\nSigned-off-by: Ye Li \u003cye.li@nxp.com\u003e\n(cherry picked from commit 3f6f4d802aba3853eb6f7d96246213d6d8ba9db7)\n" }, { "commit": "fe18c14fb3cd2808110f6a4241952c9bd00890a7", "tree": "4056e8420dceb76d4c513d0e0ee284d4ff85bfc9", "parents": [ "dfa779b1e5c844fcf77f6fe0b8c4cffe5d8a2552" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Tue Aug 21 12:45:00 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx8mm: fix system resume hang when tz380 is enabled\n\nIf NOC is power down in DSM mode, the tz380 register config\nwill be lost, so we must re-init the tz380 after system resume.\nthe tz380 initialization must be done after DRAM has been out\nof retention.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 218a3b4ed269cbe5fc932767e6077d158761fc29)\n" }, { "commit": "dfa779b1e5c844fcf77f6fe0b8c4cffe5d8a2552", "tree": "e01e53746a8350773e0a534f706f1c7365fe78fc", "parents": [ "e4cc6e1ed6cb770fc4c854b527c5f917e42a1626" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Mon Aug 20 17:32:21 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "MLK-19256 plat: imx8mm: correct dram apb clock rate dvfs\n\nThe DRAM APB bus clock rate is wrong before and after DVFS.\nThe register offset for APB bus clock is wrong, so fix it.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 079eebba34b09d6f9ffeb70d999fb4a065008b1c)\n" }, { "commit": "e4cc6e1ed6cb770fc4c854b527c5f917e42a1626", "tree": "b7bd3c708cf9f7caa9cc46372766bce1c5ad0236", "parents": [ "2afb32912f11d04a4ee438d059b05272a26350f8" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Thu Aug 02 16:07:37 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:17 2019 +0800" }, "message": "plat: imx8mm: enable noc power down support\n\nenable NOC power down in DSM mode.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 4f9398bda8c43df6db3297fd8413bb5c4bac179e)\n" }, { "commit": "2afb32912f11d04a4ee438d059b05272a26350f8", "tree": "b50339d5d11dafde685275f45e9b25dadf55ff05", "parents": [ "77f7c8a06b6c9c8d5450aa97cc4d9ed172d2b45b" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Tue Jun 19 13:11:13 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx8mm: enable power domain support\n\nEnable the power domain support on imx8mm.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 1541d8a9e3c7704b6ca0aa66f6dacf6e10b70bb6)\n" }, { "commit": "77f7c8a06b6c9c8d5450aa97cc4d9ed172d2b45b", "tree": "bf6f1b67a96792e286a49ccad24867d47ea4d287", "parents": [ "dfa6a19c2d44de65e6c03b73124f8b0d4ab81eac" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Mon Jul 16 14:30:45 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx8mm: Add lpddr4 dvfs support\n\nadd LPDDR4 DVFS support on imx8mm.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 249d90ab990f152efd899dfc51dc755fde4b7d49)\n" }, { "commit": "dfa6a19c2d44de65e6c03b73124f8b0d4ab81eac", "tree": "59156cb6a1bda21ddf28fa09dce51368a7241118", "parents": [ "8209e4ef6f9d9086e4aac6afd4eeb5367ee0870b" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Wed Jul 11 16:23:08 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx: refact the dram retention flow on imx8mm\n\nAll the DRAM timing related config is saved by SPL in OCRAM_S,\nso no need to do save for these configs in ATF anymore.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit f0893b1f52303ba5604480db71efe605161666eb)\n" }, { "commit": "8209e4ef6f9d9086e4aac6afd4eeb5367ee0870b", "tree": "acdd798b6422d931224e2f54ffce7777ac604831", "parents": [ "7f992a2ffa2da82ac5094639351e5a5d5a4b4291" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Thu Jul 05 13:54:50 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "imx8mq/imx8mm: make sure no overlap during memory map\n\nThe debug version of TF-A has below assert, fix\nit by making sure no memory map overlap.\n\nASSERT: lib/xlat_tables/xlat_tables_common.c:129\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n(cherry picked from commit a8950cc0c6e08bd399d492c5925f0d9464369ccd)\n" }, { "commit": "7f992a2ffa2da82ac5094639351e5a5d5a4b4291", "tree": "080bb6ed2bed5888592d81a54e84971e8a5f9895", "parents": [ "26fa8c05fe481462d822dba722c8552e02d1dd26" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Thu Jul 05 13:37:11 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "imx8mq/imx8mm: switch to MULTI_CONSOLE_API for debug uart support\n\nSwitch to MULTI_CONSOLE_API to make debug UART work.\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n(cherry picked from commit b9355f548ba6f1d969c4ad9c4b4a0c71f94c43db)\n" }, { "commit": "26fa8c05fe481462d822dba722c8552e02d1dd26", "tree": "2550f1e8c363d687444f0abf7e151279dd7bc1fa", "parents": [ "68164d88545509007669d307c88d5f166dca8c66" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Wed Jul 04 17:16:14 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx: fix boot hang on imx8mm ddr4 board\n\nskip init the dram info if the ddr type is DDR4,\nsupport for it will be added later.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit e88e844028da9805c8de695ef2371090e44ccfe2)\n" }, { "commit": "68164d88545509007669d307c88d5f166dca8c66", "tree": "f8f55495423e6d71c10ec668bb1ceb2110d53d9d", "parents": [ "2509fe1d2d190e6aecf6cbf01fef8958e45f1ac1" ], "author": { "name": "Anson Huang", "email": "Anson.Huang@nxp.com", "time": "Thu Jun 21 13:11:36 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "imx: enable necessary erratas for A53 r0p4\n\nThis patch enables necessary erratas for A53 r0p4\naccording to docs/cpu-specific-build-macros.rst.\n\nSigned-off-by: Anson Huang \u003cAnson.Huang@nxp.com\u003e\n(cherry picked from commit 8592b0e37db6fe21d0fc5baa74614c78098f6d59)\n" }, { "commit": "2509fe1d2d190e6aecf6cbf01fef8958e45f1ac1", "tree": "5a1bfad76655763ec771e8ca1d13caaef759ef27", "parents": [ "1f0acfee3ef10a10d0ee3731ad2ad59f303dc024" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Mon Jun 11 13:19:20 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx8mm: mask the non-wakeup irq in low power mode\n\nOnly enable the wakeup irq when system enter DSM mode.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 7b9b62cff3816e2196d1d9c94d8c95eedda96dec)\n" }, { "commit": "1f0acfee3ef10a10d0ee3731ad2ad59f303dc024", "tree": "681e8481f6ab8f41112254ad30655e4d0930965d", "parents": [ "661956194c7b6a92fe11ed70797164e842ee5aa1" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Mon Jun 11 10:05:54 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx8mm: use ARRAY_SIZE instead of magic number\n\nuse ARRAY_SIZE to get the array size.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit aaa49f3b45d7cea0790c2856c750d6f9934e2e7d)\n" }, { "commit": "661956194c7b6a92fe11ed70797164e842ee5aa1", "tree": "444d2ab238eccc040b300398508c9d4edadf2973", "parents": [ "0995afdda32015e0d3717b57b31acca1efcdd733" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Sun Jun 10 21:21:43 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx8mm: enable DSM mode support on imx8mm\n\nenable DSM mode on i.MX8MM.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 4f20d50af59f5a941aa47918fc6cf7731055562d)\n" }, { "commit": "0995afdda32015e0d3717b57b31acca1efcdd733", "tree": "d4c567887bcef5208a82454cb2ae73a3b93a6032", "parents": [ "82d9eb65b11e5692522c13c495ee3c9d8dbe99b4" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Sun Jun 10 20:22:45 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx8m: add a common dram PM code for imx8m soc\n\nre-design the dram power management code to make it more\ncommon for all i.MX8M SOCs. code need to refact and optimize\nto make more better. Using this common code on i.MX8MM first,\nfor i.MX8MQ, will move to this later.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 8b2305c1464839bdf2683f8ece9482c52cd30720)\n" }, { "commit": "82d9eb65b11e5692522c13c495ee3c9d8dbe99b4", "tree": "581d8c6194923e6ad698eccbb07f982534638116", "parents": [ "7e2fc4ae2549bae052e2349e465e73f8f9da810f" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Fri Jun 08 18:21:33 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx8mm: switch the CKIL clock source to 32K OSC\n\nSwitch the CKIL clock source to 32K OSC. On i.MX8MM,\nafter SOC PoR, the default clock source for CKIL is from\ndivided 24MHz OSC, as 24MHz OSC will be power down when\nsystem enters DSM mdoe. So it is better to use 32K OSC\nas the default clock source after system bootup.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit ede5b2ccebd7b5e22d38304def6d449aaa8096d3)\n" }, { "commit": "7e2fc4ae2549bae052e2349e465e73f8f9da810f", "tree": "a71dfbdbefdeb42597dbf83f69381fddbb1e6db2", "parents": [ "0e843a4d3550cd804affab1932468f62c3c5b63f" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Thu Jun 07 18:29:29 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx8mm: enable PU domains\u0027 clocks before power up\n\nVPU, GPU and PCIE\u0027s clock need to be on before power on\nthese power domains.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit ee094d86280c0e3d899d973db24b4b9b563944da)\n" }, { "commit": "0e843a4d3550cd804affab1932468f62c3c5b63f", "tree": "289b8d059969a15e1b24a90ecfc3729f38bcb507", "parents": [ "9316fff25206693c3d3dab64ed2c259b4a895ab2" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Tue Jun 05 13:07:38 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "MLK-18502-02 plat: imx8mm: keep L2 cache memory power in WAIT mode\n\nWhen system enter deepest cpuilde(WAIT mode), the L2 cache memory\ncan be on for retention to increase the system performance. So\nthe WAIT mode with cluster power down should be defined as\nrentention power state in PSCI. changing the WAIT_OFF_STATE to\nWAIT_RET_STATE to make sure the l2 cache memory is not\nclean \u0026 invalidate.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 7f83fd077208220c57a389871abb987d371ca50c)\n" }, { "commit": "9316fff25206693c3d3dab64ed2c259b4a895ab2", "tree": "7051259ae64ebc44ae3790a18041fb1c355f11de", "parents": [ "41262dc9e61f2134b64ed563eb283128507124d8" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Tue Jun 05 10:58:39 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "MLK-18502-01 plat: imx8mm: fix audio fifo underrun issue\n\nA53 WAIT mode is specific for OS cpuilde. The MASTER1 \u0026 MASTER2\nmapping in A53 domain should be clear, otherwise the \u0027noc2supermix\u0027\nand \u0027supermix2noc\u0027 ADB400 async port will be power down when A53\nenters WAIT mode.If the ADB400 is power down in WAIT mode, all the bus\nrequest from supermix to noc wrapper will be blocked.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 21fa6238d98517739e9e65cd6431a1e5a0880a52)\n" }, { "commit": "41262dc9e61f2134b64ed563eb283128507124d8", "tree": "3f8505845f77a7bc6349492d17023ab698ae1ac9", "parents": [ "ba66c22e0f79e324902090ca8633776fb321a910" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Fri May 18 08:52:28 2018 +0200" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "MLK-18343-3: plat: imx8mm: add CAAM support\n\n- configure Secure memory partition\n- allocate all CAAM JR to Linux\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\nReviewed-by: Aymen Sghaier \u003caymen.sghaier@nxp.com\u003e\n(cherry picked from commit 6a64d1c6421cb862c28c1e948da071e3443f94bd)\n" }, { "commit": "ba66c22e0f79e324902090ca8633776fb321a910", "tree": "d77d2c98d46510aa572ffea720e719ff784b8bfb", "parents": [ "4152ed1c9dbf06f36173e190fcf7fb61ef2e437c" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Thu May 17 17:32:10 2018 +0200" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "MLK-18343-2: plat: imx8mm: add support for RDC and CSU\n\nmove CSU and RDC driver to common/i.mx8m folder\nand enable the driver for i.mx8mm\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\nReviewed-by: Aymen Sghaier \u003caymen.sghaier@nxp.com\u003e\n(cherry picked from commit 7dd1b741efdc60ca6b5eaafc9d863744beb7064e)\n\nConflicts:\n" }, { "commit": "4152ed1c9dbf06f36173e190fcf7fb61ef2e437c", "tree": "1bd4f0848cd46ff81247ebbdf32781af42099562", "parents": [ "075c82120804d358e8d49429d217de84d7db7971" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Thu May 17 17:09:29 2018 +0200" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "MLK-18343-1: plat: imx8mm: add BL32 support\n\nfix entry point for the OP-TEE\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\nReviewed-by: Aymen Sghaier \u003caymen.sghaier@nxp.com\u003e\n(cherry picked from commit ddac82579f52819dc24e6bf5eb23f9fd354844fb)\n" }, { "commit": "075c82120804d358e8d49429d217de84d7db7971", "tree": "09d927643c8b85de014895ad31573f7bf9946e3f", "parents": [ "1959fcad91ca96b0e8b6cb2c1221f23974c06802" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Tue May 22 14:58:10 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx8mm: enable the wait mode support on imx8mm\n\nEnable the WAIT mode support in cpuilde to save power.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit e57c29571ea864871bdd91f364b6c77d5de5f671)\n" }, { "commit": "1959fcad91ca96b0e8b6cb2c1221f23974c06802", "tree": "624e2128c7d6e7b83df2f60c51137bb2697e4e3b", "parents": [ "8344f72182aa7dc72dc2bb0d5aafa5ae2af3f45d" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Fri May 18 11:02:47 2018 +0200" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx8mm: cleanup platform.mk\n\ncleanup XLAT and STACK defines\nthe OCRAM size for ATF is big enough for i.MX 8mm\nthere is no need to move code to OCRAM_S\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\nAcked-by: Jacky Bai \u003cping.bai@nxp.com\u003e\n(cherry picked from commit b21783f0968e2c17de59956d8bb59dd7ca133b7c)\n" }, { "commit": "8344f72182aa7dc72dc2bb0d5aafa5ae2af3f45d", "tree": "5486c5517ae8479223ea79049a727c5993549704", "parents": [ "7171c1a4c6b5bd3c804d57aa884528e7ccfc5320" ], "author": { "name": "Ye Li", "email": "ye.li@nxp.com", "time": "Tue May 15 23:50:21 2018 -0700" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "imx8mm: add HAB support\n\nSimilar to imx8mq, the U-boot calls SIP call for HAB interfaces, and trap to ATF\nto run the HAB.\n\nSince HAB codes locates in ROM, and need to access OCRAM, CAAM RAM and DDR to\nauthenticate image. Add these relevant memory region to MMU. Also extend the\nstack size of each core to avoid stack overflow, and extend the BL31 limit\nto OCRAM end 0x940000.\n\nSigned-off-by: Ye Li \u003cye.li@nxp.com\u003e\n(cherry picked from commit d5158f18b0b6e13760eb92afeff0a4129f63de4b)\n" }, { "commit": "7171c1a4c6b5bd3c804d57aa884528e7ccfc5320", "tree": "ba066cae84478ccdc4c534b8c6b18afe21fc7bf9", "parents": [ "3b80c4d503767822ce54b15213aa6ee3839f0eea" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Fri May 11 13:58:31 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx8mm: add basic imx8mm support\n\ni.MX8MM is a new soc of the i.MX8M family, this patch\nadd the basic support for i.MX8MM. further code optimization\nneeded. WAIT mode support is currently disabled, will be enabled\nlater.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 6aafe1fcd7296eded1163d919b6ce018487e8645)\n\nConflicts:\n\tplat/imx/imx8mq/sip_svc.c\n" }, { "commit": "3b80c4d503767822ce54b15213aa6ee3839f0eea", "tree": "cbb6c7e3ae9118897684f34d939741c7b6909692", "parents": [ "22e135b549b2874a07966e8e0a282ad9b3826a93" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Fri May 11 17:11:39 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx8m: move hab file to common dir of imx8m\n\nAs the i.MX8MM and i.MX8MQ share the same hab file, move it\nto common/imx8m, make it reusable for all i.MX8M SOCs.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit a15a09e462c9a24e42084e3043aa992c59875d86)\n" }, { "commit": "22e135b549b2874a07966e8e0a282ad9b3826a93", "tree": "80819f4de8112fdb1c16106fd3091d4efa5677fc", "parents": [ "e2584c3bd06633f509b69fa8d7bb0c48d436175c" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Thu May 10 15:53:11 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx8mq: rename files for imx8mq\n\nFor the i.MX8 media processor, we have i.MX8MQ and i.MX8MM etc.\nso rename the file name of imx8m_bl31_setup.c and imx8m_psci.c\nto imx8mq_xxx to make it more clear that these file is specific\nto i.MX8MQ.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit 146f4caf3c60fb323db12a4ff3c960c8f08d6f17)\n\nConflicts:\n\tplat/imx/imx8mq/platform.mk\n" }, { "commit": "e2584c3bd06633f509b69fa8d7bb0c48d436175c", "tree": "b4b927822201cfd51256edfdf85f40e7a2200b21", "parents": [ "509893844ef5ea68009cd4273c9fe22b2b1c82c6" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Fri Mar 09 19:18:14 2018 +0100" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "MLK-17591-2: CSU/RDC Add testing capability\n\nthis patch adds some configuration to test CSU and RDC feature\nby default this is disable. to enable it add\n$(eval $(call add_define,CSU_RDC_TEST)) to the platform.mk file\nunder plat/freescale/imx8mq/include\n\nthis patch configure\n- CSU for GPIO5 to be secure only\n- RDC for Cortex A to be Domain ID 0\n- GPIO4 to be rw by domain ID 2\n\nto test, stops boot at uboot and run following command:\n\nu-boot\u003d\u003e md 0x3024000\n03024000:\"Synchronous Abort\" handler, esr 0x96000210\nELR: 40257504\nLR: 402574c0\nx0 : 0000000000000009 x1 : 00000000308600b4\nx2 : 00000000fdf28804 x3 : 0000000000000000\nx4 : 0000000003024000 x5 : 00000000fdf73ad0\nx6 : 0000000000000004 x7 : 000000000000000f\nx8 : 00000000fc8ff7e0 x9 : 0000000000000000\nx10: 00000000fc8ff049 x11: 0000000000000021\nx12: 0000000000000008 x13: 00000000ffffffff\nx14: 00000000fc8ffb1c x15: 00000000fc8ffc40\nx16: 0000000000000000 x17: 0000000000000000\nx18: 00000000fc907da0 x19: 0000000000000040\nx20: 0000000000000004 x21: 0000000003024000\nx22: 0000000003024000 x23: 00000000fdf7348d\nx24: 0000000000000008 x25: 0000000000000009\nx26: 0000000000000004 x27: 0000000000000004\nx28: 00000000fc8ff928 x29: 00000000fc8ff8a0\n\nResetting CPU ...\n\nresetting ...\n\nCPU tried to acces GPIO 5 registers and crashes\n\nu-boot\u003d\u003e md 0x30230000\n30230000:\"Synchronous Abort\" handler, esr 0x96000210\nELR: 40257504\nLR: 402574c0\nx0 : 0000000000000009 x1 : 00000000308600b4\nx2 : 00000000fdf28804 x3 : 0000000000000000\nx4 : 0000000030230000 x5 : 00000000fdf73ad0\nx6 : 0000000000000004 x7 : 000000000000000f\nx8 : 00000000fc8ff7e0 x9 : 0000000000000000\nx10: 00000000fc8ff049 x11: 0000000000000021\nx12: 0000000000000008 x13: 00000000ffffffff\nx14: 00000000fc8ffb1c x15: 00000000fc8ffc40\nx16: 0000000000000000 x17: 0000000000000000\nx18: 00000000fc907da0 x19: 0000000000000040\nx20: 0000000000000004 x21: 0000000030230000\nx22: 0000000030230000 x23: 00000000fdf7348d\nx24: 0000000000000008 x25: 0000000000000009\nx26: 0000000000000004 x27: 0000000000000004\nx28: 00000000fc8ff928 x29: 00000000fc8ff8a0\n\nResetting CPU ...\n\nresetting ...\n\nCPU tried to acces GPIO 4 registers and crashes\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\nReviewed-by: Peng Fan \u003cpeng.fan@nxp.com\u003e\n(cherry picked from commit b71c6248fe7499b8a19d10c811814e2b33b1b022)\n" }, { "commit": "509893844ef5ea68009cd4273c9fe22b2b1c82c6", "tree": "8af53fab943f8e862bbe6ce3256e68c657e33903", "parents": [ "6ee2c9f688664cb08c8ac0f24c3142c4b30075bf" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Fri Mar 09 19:13:44 2018 +0100" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "MLK-17591-1: CSU Fix Slave configuration\n\nthere is a bug in the CSL assignment.\nthe CSL(n) and CSL(n+1) configuration were reversed.\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\nReviewed-by: Peng Fan \u003cpeng.fan@nxp.com\u003e\n(cherry picked from commit f8b639ddea3be778b006d1a5397d21e2ca6ae7c8)\n" }, { "commit": "6ee2c9f688664cb08c8ac0f24c3142c4b30075bf", "tree": "1ca4e759fdaec08175fd019a6000039897c32bbe", "parents": [ "c28d4d36b68da4b76148638299d3a3ad7a05d0b7" ], "author": { "name": "Bai Ping", "email": "ping.bai@nxp.com", "time": "Wed Mar 07 16:09:41 2018 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Jan 25 18:51:16 2019 +0800" }, "message": "plat: imx8mq: correct the reg offset of ddr type register\n\ncorrect the ddr type register\u0027s offset.\n\nSigned-off-by: Bai Ping \u003cping.bai@nxp.com\u003e\n(cherry picked from commit fccb3083469a33173b3d455b396875b50e667d85)\n" } ], "next": "c28d4d36b68da4b76148638299d3a3ad7a05d0b7" }