commit 10b2dc9ae97b3f92a44c4ab9ee17ba65f0eedac0
author Leonid Lobachev <leonidl@google.com> Fri Oct 18 14:51:35 2019 -0700
committer June Tate-Gans <jtgans@google.com> Tue Oct 22 15:57:54 2019 -0500
tree 1a5ac6237ab9891e1123330fa111f3d58978bdd2
parent 413e93e10ee4838e9a68b190f1468722f6385e0e

plat: imx8mq: enable normal peripheral irq wake system

Change-Id: I43767e534f70a5f2dc5975c3af9e8e4f8b41ae47
Signed-off-by: Leonid Lobachev <leonidl@google.com>

plat/imx/imx8mq/gpc.c

diff --git a/plat/imx/imx8mq/gpc.c b/plat/imx/imx8mq/gpc.c
index 6b8e341..89e9352 100644
--- a/plat/imx/imx8mq/gpc.c
+++ b/plat/imx/imx8mq/gpc.c
@@ -27,7 +27,7 @@
 #define GPC_IMR2_CORE1_A53	0x44
 #define GPC_IMR3_CORE1_A53	0x48
 #define GPC_IMR4_CORE1_A53	0x4c
-#define GPC_IMR1_CORE0_M4		0x50
+#define GPC_IMR1_CORE0_M4	0x50
 #define GPC_IMR1_CORE2_A53	0x1c0
 #define GPC_IMR2_CORE2_A53	0x1c4
 #define GPC_IMR3_CORE2_A53	0x1c8
@@ -318,13 +318,13 @@
 		 * disable in LPM mode.
 		 */
 		val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
-		val |= 0xa; /* enable the C0~1 LPM */
+		val |= 0x5; /* enable the C0~1 LPM */
 		val &= ~(1 << 14); /* disable cpu clock in LPM */
 		mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
 
 		/* enable C2-3's LPM */
 		val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC2);
-		val |= 0xa;
+		val |= 0x5;
 		mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC2, val);
 
 		/* enable PLAT/SCU power down */
@@ -357,12 +357,12 @@
 
 		/* reverse the cluster level setting */
 		val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
-		val &= ~0xa; /* clear the C0~1 LPM */
+		val &= ~0x5; /* clear the C0~1 LPM */
 		val |= (1 << 14); /* disable cpu clock in LPM */
 		mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
 
 		val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC2);
-		val &= ~0xa;
+		val &= ~0x5;
 		mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC2, val);
 
 		/* clear PLAT/SCU power down */
@@ -388,13 +388,7 @@
 
 	if (retention) {
 		val |= (SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS |
-			 SLPCR_BYPASS_PMIC_READY | SLPCR_RBC_EN);
-
-		/* DDR enter retention */
-		dram_enter_retention();
-	} else {
-		/* DDR exit retention */
-		dram_exit_retention();
+			 SLPCR_BYPASS_PMIC_READY | SLPCR_RBC_EN | SLPCR_A53_FASTWUP_WAIT);
 	}
 
 	mmio_write_32(IMX_GPC_BASE + 0x14, val);
@@ -420,6 +414,7 @@
 }
 void imx_anamix_pre_suspend()
 {
+#if 0
 	/* override PLL/OSC to let ccm control them */
 	mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_AUDIO_PLL1_CFG0,
 		mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_AUDIO_PLL1_CFG0) | 0x140000);
@@ -445,10 +440,12 @@
 		mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_DRAM_PLL_CFG0) | 0x140);
 	mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_ANAMIX_MISC_CFG,
 		mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_ANAMIX_MISC_CFG) | 0xa);
+#endif
 }
 
 void imx_anamix_post_resume(void)
 {
+#if 0
 	/* clear override of PLL/OSC */
 	mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_AUDIO_PLL1_CFG0,
 		mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_AUDIO_PLL1_CFG0) & ~0x140000);
@@ -474,6 +471,7 @@
 		mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_DRAM_PLL_CFG0) & ~0x140);
 	mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_HW_ANAMIX_MISC_CFG,
 		mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_HW_ANAMIX_MISC_CFG) & ~0xa);
+#endif
 }
 
 static void imx_gpc_hwirq_mask(unsigned int hwirq)