MLK-17591-2: CSU/RDC Add testing capability
this patch adds some configuration to test CSU and RDC feature
by default this is disable. to enable it add
$(eval $(call add_define,CSU_RDC_TEST)) to the platform.mk file
under plat/freescale/imx8mq/include
this patch configure
- CSU for GPIO5 to be secure only
- RDC for Cortex A to be Domain ID 0
- GPIO4 to be rw by domain ID 2
to test, stops boot at uboot and run following command:
u-boot=> md 0x3024000
03024000:"Synchronous Abort" handler, esr 0x96000210
ELR: 40257504
LR: 402574c0
x0 : 0000000000000009 x1 : 00000000308600b4
x2 : 00000000fdf28804 x3 : 0000000000000000
x4 : 0000000003024000 x5 : 00000000fdf73ad0
x6 : 0000000000000004 x7 : 000000000000000f
x8 : 00000000fc8ff7e0 x9 : 0000000000000000
x10: 00000000fc8ff049 x11: 0000000000000021
x12: 0000000000000008 x13: 00000000ffffffff
x14: 00000000fc8ffb1c x15: 00000000fc8ffc40
x16: 0000000000000000 x17: 0000000000000000
x18: 00000000fc907da0 x19: 0000000000000040
x20: 0000000000000004 x21: 0000000003024000
x22: 0000000003024000 x23: 00000000fdf7348d
x24: 0000000000000008 x25: 0000000000000009
x26: 0000000000000004 x27: 0000000000000004
x28: 00000000fc8ff928 x29: 00000000fc8ff8a0
Resetting CPU ...
resetting ...
CPU tried to acces GPIO 5 registers and crashes
u-boot=> md 0x30230000
30230000:"Synchronous Abort" handler, esr 0x96000210
ELR: 40257504
LR: 402574c0
x0 : 0000000000000009 x1 : 00000000308600b4
x2 : 00000000fdf28804 x3 : 0000000000000000
x4 : 0000000030230000 x5 : 00000000fdf73ad0
x6 : 0000000000000004 x7 : 000000000000000f
x8 : 00000000fc8ff7e0 x9 : 0000000000000000
x10: 00000000fc8ff049 x11: 0000000000000021
x12: 0000000000000008 x13: 00000000ffffffff
x14: 00000000fc8ffb1c x15: 00000000fc8ffc40
x16: 0000000000000000 x17: 0000000000000000
x18: 00000000fc907da0 x19: 0000000000000040
x20: 0000000000000004 x21: 0000000030230000
x22: 0000000030230000 x23: 00000000fdf7348d
x24: 0000000000000008 x25: 0000000000000009
x26: 0000000000000004 x27: 0000000000000004
x28: 00000000fc8ff928 x29: 00000000fc8ff8a0
Resetting CPU ...
resetting ...
CPU tried to acces GPIO 4 registers and crashes
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 5e238f92d85d4fedc33d13605a2056d1a95291bf)
5 files changed