diff --git a/plat/imx/imx8mq/gpc.c b/plat/imx/imx8mq/gpc.c
index 89e9352..b37550b 100644
--- a/plat/imx/imx8mq/gpc.c
+++ b/plat/imx/imx8mq/gpc.c
@@ -16,6 +16,7 @@
 #include <platform_def.h>
 #include <imx_sip.h>
 #include <soc.h>
+#include <bakery_lock.h>
 
 #define GPC_MST_CPU_MAPPING	0x18
 #define GPC_PGC_ACK_SEL_A53	0x24
@@ -92,6 +93,10 @@
 	0xec0, 0xf00, 0xf40,
 };
 
+spinlock_t gpc_imr_lock[4];
+
+DEFINE_BAKERY_LOCK(gpc_lock);
+
 void imx_gpc_set_m_core_pgc(unsigned int offset, bool pdn)
 {
 	uintptr_t val;
@@ -122,12 +127,16 @@
 {
 	uint32_t val;
 
+	bakery_lock_get(&gpc_lock);
+
 	/* enable the wfi power down of the core */
 	val = mmio_read_32(IMX_GPC_BASE + 0x4);
 	val |= (1 << (core_id < 2 ? core_id * 2 : (core_id - 2) * 2 + 16));
 	val |= 1 << (core_id + 20);
 	mmio_write_32(IMX_GPC_BASE + 0x4, val);
 
+	bakery_lock_release(&gpc_lock);
+
 	/* assert the pcg pcr bit of the core */
 	val = mmio_read_32(IMX_GPC_BASE + 0x800 + 0x40 * core_id);
 	val |= (1 << 0);
@@ -139,11 +148,15 @@
 {
 	uint32_t val;
 
+	bakery_lock_get(&gpc_lock);
+
 	/* clear the wfi power down bit of the core */
 	val = mmio_read_32(IMX_GPC_BASE + 0x4);
 	val &= ~(1 << (core_id < 2 ? core_id * 2 : (core_id - 2) * 2 + 16));
 	mmio_write_32(IMX_GPC_BASE + 0x4, val);
 
+	bakery_lock_release(&gpc_lock);
+
 	/* assert the ncpuporeset */
 	val = mmio_read_32(IMX_SRC_BASE + 0x8);
 	val &= ~(1 << core_id);
@@ -179,6 +192,8 @@
 {
 	uint32_t val;
 
+	bakery_lock_get(&gpc_lock);
+
 	if (pdn) {
 		val = mmio_read_32(IMX_GPC_BASE + 0x4);
 		/* enable the core WFI power down */
@@ -204,6 +219,8 @@
 		val &= ~(1 << 0);
 		mmio_write_32(IMX_GPC_BASE + 0x800 + 0x40 * core_id, val);
 	}
+
+	bakery_lock_release(&gpc_lock);
 }
 
 /*