commit dbde65334c329b406fcb71f765b8fe0d2cce8f14
author Anson Huang <Anson.Huang@nxp.com> Sat Sep 02 00:54:06 2017 +0800
committer Jacky Bai <ping.bai@nxp.com> Fri Jan 25 18:51:15 2019 +0800
tree 59e71a35fbc5a79d1601859775747091c23590d1
parent b614207f267b44333d4a9864949daca6d2cad93c

imx8mq: gpc: correct ARM power down request register offset

The GPC_CPU_PGC_SW_PDN_REQ offset should be 0xfc, previous
offset is incorrect, so actually ARM core is NOT powered
down and the power leakage is very high.

With this fix, each ARM core's leakage is about 25mA@0.9V.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit a9795cd37bcece4cc4b559e4fa0a5f4af088a8c1)

plat/imx/imx8mq/gpc.c

diff --git a/plat/imx/imx8mq/gpc.c b/plat/imx/imx8mq/gpc.c
index 8bce39f..b630faa 100644
--- a/plat/imx/imx8mq/gpc.c
+++ b/plat/imx/imx8mq/gpc.c
@@ -93,7 +93,7 @@
 #define SLPCR_A53_FASTWUP_WAIT		(1 << 16)
 
 #define GPC_CPU_PGC_SW_PUP_REQ		0xf0
-#define GPC_CPU_PGC_SW_PDN_REQ		0xf4
+#define GPC_CPU_PGC_SW_PDN_REQ		0xfc
 #define BM_CPU_PGC_SW_PDN_PUP_REQ 	0x1
 
 #define GPC_ARM_PGC		0x800