diff --git a/plat/imx/common/imx8m/ddr4_retention.c b/plat/imx/common/imx8m/ddr4_retention.c
index ee2e6b6..9f90238 100644
--- a/plat/imx/common/imx8m/ddr4_retention.c
+++ b/plat/imx/common/imx8m/ddr4_retention.c
@@ -107,6 +107,8 @@
 	/* assert all reset */
 	mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F00003F);
 
+	mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F00000F); /* release [4]src_system_rst_b! */
+
 	mmio_write_32(CCM_CCGR(5), 2);
 	mmio_write_32(CCM_SRC_CTRL(15), 2);
 	printf("C: enable all DRAM clocks \n");
@@ -114,13 +116,16 @@
 	mmio_write_32(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
 	mmio_setbits_32(0x303A00F8, (1 << 5));
 
-	mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F00000F); /* release [4]src_system_rst_b! */
 	mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F000006); /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */
 	/* RESET: <core_ddrc_rstn> ASSERTED (ACTIVE LOW) */
 	/* RESET: <presetn> ASSERTED (ACTIVE LOW) */
 	/* RESET: <aresetn> for Port 0  ASSERTED (ACTIVE LOW) */
 	/* RESET: <presetn> DEASSERTED */
 
+	/* wait dram pll locked */
+	while(!(mmio_read_32(DRAM_PLL_CTRL) & (1 << 31)))
+		;
+
 	mmio_write_32(DDRC_DBG1(0), 0x00000001);
 	mmio_write_32(DDRC_PWRCTL(0), 0x00000001);
 	while (0 != (0x7 & mmio_read_32(DDRC_STAT(0))))
diff --git a/plat/imx/common/imx8m/lpddr4_retention.c b/plat/imx/common/imx8m/lpddr4_retention.c
index 205dbbf..8cc44c8 100644
--- a/plat/imx/common/imx8m/lpddr4_retention.c
+++ b/plat/imx/common/imx8m/lpddr4_retention.c
@@ -163,6 +163,10 @@
 
 	mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F000006); // release [0]ddr1_preset_n,  [3]ddr1_phy_pwrokin_n
 
+	/* wait dram pll locked */
+	while(!(mmio_read_32(DRAM_PLL_CTRL) & (1 << 31)))
+		;
+
 	/* ddrc re-init */
 	dram_umctl2_init();
 
diff --git a/plat/imx/imx8mm/include/platform_def.h b/plat/imx/imx8mm/include/platform_def.h
index dea9b61..3e26158 100644
--- a/plat/imx/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8mm/include/platform_def.h
@@ -88,6 +88,8 @@
 #define IMX_DDR_IPS_BASE		0x3d000000
 #define IMX_ROM_BASE			0x0
 
+#define DRAM_PLL_CTRL			(IMX_ANAMIX_BASE + 0x50)
+
 #define OCRAM_S_BASE			0x00180000
 #define OCRAM_S_SIZE			0x8000
 #define OCRAM_S_LIMIT			(OCRAM_S_BASE + OCRAM_S_SIZE)
diff --git a/plat/imx/imx8mq/include/platform_def.h b/plat/imx/imx8mq/include/platform_def.h
index 822d95a..31ce296 100644
--- a/plat/imx/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8mq/include/platform_def.h
@@ -75,6 +75,7 @@
 #define HW_DRAM_PLL_CFG0		(IMX_ANAMIX_BASE + 0x60)
 #define HW_DRAM_PLL_CFG1		(IMX_ANAMIX_BASE + 0x64)
 #define HW_DRAM_PLL_CFG2		(IMX_ANAMIX_BASE + 0x68)
+#define DRAM_PLL_CTRL			HW_DRAM_PLL_CFG0
 
 #define OCRAM_S_BASE			0x00180000
 #define OCRAM_S_SIZE			0x8000