imx8q: [trusty] Kick CAAM power

JR0 and JR1 of CAAM are owned by SECO, only kick the power
of JR2 and JR3 here and assign the resources to be accessed
by secure world.

Signed-off-by: Ji Luo <ji.luo@nxp.com>
(cherry picked from commit 4f00df596a80cb4b4539d228332d976cf38d4183)
diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c
index b592ea8..8757431 100644
--- a/plat/imx/imx8qm/imx8qm_bl31_setup.c
+++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c
@@ -391,6 +391,7 @@
 
 	/* turn on MU1 for non-secure OS/Hypervisor */
 	sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON);
+
 	/* Turn on GPT_0's power & clock for non-secure OS/Hypervisor */
 	sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON);
 	sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0);
@@ -402,6 +403,13 @@
 	 */
 	mx8_partition_resources();
 
+#ifdef SPD_trusty
+	sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR2, SC_PM_PW_MODE_ON);
+	sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR2_OUT, SC_PM_PW_MODE_ON);
+	sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR3, SC_PM_PW_MODE_ON);
+	sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR3_OUT, SC_PM_PW_MODE_ON);
+#endif
+
 	bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
 	bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
 #ifdef SPD_trusty
diff --git a/plat/imx/imx8qm/include/sec_rsrc.h b/plat/imx/imx8qm/include/sec_rsrc.h
index 3a0be73..f6a1bac 100644
--- a/plat/imx/imx8qm/include/sec_rsrc.h
+++ b/plat/imx/imx8qm/include/sec_rsrc.h
@@ -20,6 +20,12 @@
 	SC_R_CCI,
 	SC_R_SYSTEM,
 	SC_R_GPT_0,
+#ifdef SPD_trusty
+	SC_R_CAAM_JR2,
+	SC_R_CAAM_JR2_OUT,
+	SC_R_CAAM_JR3,
+	SC_R_CAAM_JR3_OUT,
+#endif
 	SC_R_IRQSTR_SCU2
 };
 
diff --git a/plat/imx/imx8qx/imx8qx_bl31_setup.c b/plat/imx/imx8qx/imx8qx_bl31_setup.c
index ca3c245..7f15a4a 100644
--- a/plat/imx/imx8qx/imx8qx_bl31_setup.c
+++ b/plat/imx/imx8qx/imx8qx_bl31_setup.c
@@ -378,6 +378,13 @@
 	 */
 	imx8_partition_resources();
 
+#ifdef SPD_trusty
+	sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR2, SC_PM_PW_MODE_ON);
+	sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR2_OUT, SC_PM_PW_MODE_ON);
+	sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR3, SC_PM_PW_MODE_ON);
+	sc_pm_set_resource_power_mode(ipc_handle, SC_R_CAAM_JR3_OUT, SC_PM_PW_MODE_ON);
+#endif
+
 	bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
 	bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
 #ifdef SPD_trusty
diff --git a/plat/imx/imx8qx/include/sec_rsrc.h b/plat/imx/imx8qx/include/sec_rsrc.h
index 33bcc06..c3a952a 100644
--- a/plat/imx/imx8qx/include/sec_rsrc.h
+++ b/plat/imx/imx8qx/include/sec_rsrc.h
@@ -15,6 +15,12 @@
 	SC_R_GIC,
 	SC_R_SYSTEM,
 	SC_R_GPT_0,
+#ifdef SPD_trusty
+	SC_R_CAAM_JR2,
+	SC_R_CAAM_JR2_OUT,
+	SC_R_CAAM_JR3,
+	SC_R_CAAM_JR3_OUT,
+#endif
 	SC_R_IRQSTR_SCU2
 };