plat: imx8mm: update the stby_count setting
The reset value of the STBY_COUNT is 0x0, so
it means GPC will wait for 4 ckil(32K) clock cycle
before checking the PMIC ready signal. increase
this value to 0x5, 128 ckil to make sure PMIC
output voltage is stable before GPC continue
to finish the DSM exit flow.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 94f65be918f91df676f0e61c4fef97dfd31e168f)
diff --git a/plat/imx/imx8mm/gpc.c b/plat/imx/imx8mm/gpc.c
index ee233cf..4c434c4 100644
--- a/plat/imx/imx8mm/gpc.c
+++ b/plat/imx/imx8mm/gpc.c
@@ -51,6 +51,7 @@
#define A53_LPM_STOP 0xa
#define A53_CLK_ON_LPM (1 << 14)
#define SLPCR_RBC_SHIFT 24
+#define SLPCR_STBY_COUNT_SHFT 3
#define MST_CPU_MAPPING 0x18
@@ -1001,7 +1002,9 @@
val |= SLPCR_A53_FASTWUP_WAIT;
/* clear the RBC */
val &= ~(0x3f << SLPCR_RBC_SHIFT);
- /* TODO if M4 is not enabled, clear more SLPCR bits */
+ /* set the STBY_COUNT to 0x5, (128 * 30)us*/
+ val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT);
+ val |= (0x5 << SLPCR_STBY_COUNT_SHFT);
mmio_write_32(IMX_GPC_BASE + SLPCR, val);
/*
