diff --git a/plat/imx/common/include/fsl_sip.h b/plat/imx/common/include/fsl_sip.h
index 4f0cec0..fac31bb 100644
--- a/plat/imx/common/include/fsl_sip.h
+++ b/plat/imx/common/include/fsl_sip.h
@@ -47,6 +47,12 @@
 
 #define FSL_SIP_NOC			0xc2000008
 #define FSL_SIP_NOC_LCDIF		0x0
+#define FSL_SIP_NOC_PRIORITY		0x1
+#define NOC_GPU_PRIORITY		0x10
+#define NOC_DCSS_PRIORITY		0x11
+#define NOC_VPU_PRIORITY		0x12
+#define NOC_CPU_PRIORITY		0x13
+#define NOC_MIX_PRIORITY		0x14
 
 #define FSL_SIP_WAKEUP_SRC		0xc2000009
 #define FSL_SIP_WAKEUP_SRC_SCU		0x1
diff --git a/plat/imx/imx8mq/src.c b/plat/imx/imx8mq/src.c
index abaf054..eb36c23 100644
--- a/plat/imx/imx8mq/src.c
+++ b/plat/imx/imx8mq/src.c
@@ -71,8 +71,7 @@
 int imx_noc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
 		    u_register_t x3)
 {
-	switch(x1) {
-	case FSL_SIP_NOC_LCDIF:
+	if (FSL_SIP_NOC_LCDIF == x1) {
 		/* config NOC for VPU */
 		mmio_write_32(IMX_NOC_BASE + 0x108, 0x34);
 		mmio_write_32(IMX_NOC_BASE + 0x10c, 0x1);
@@ -83,10 +82,29 @@
 		mmio_write_32(IMX_NOC_BASE + 0x18c, 0x1);
 		mmio_write_32(IMX_NOC_BASE + 0x190, 0x500);
 		mmio_write_32(IMX_NOC_BASE + 0x194, 0x30);
-		break;
-	default:
+	} else if (FSL_SIP_NOC_PRIORITY == x1) {
+		switch(x2) {
+		case NOC_GPU_PRIORITY:
+			mmio_write_32(IMX_NOC_BASE + 0x008, x3);
+			break;
+		case NOC_DCSS_PRIORITY:
+			mmio_write_32(IMX_NOC_BASE + 0x088, x3);
+			break;
+		case NOC_VPU_PRIORITY:
+			mmio_write_32(IMX_NOC_BASE + 0x108, x3);
+			break;
+		case NOC_CPU_PRIORITY:
+			mmio_write_32(IMX_NOC_BASE + 0x188, x3);
+			break;
+		case NOC_MIX_PRIORITY:
+			mmio_write_32(IMX_NOC_BASE + 0x288, x3);
+			break;
+		default:
+			return SMC_UNK;
+		};
+	} else {
 		return SMC_UNK;
-	};
+	}
 
 	return 0;
 }