commit 6f353c76b9273c55eb48768dcfc4ab725731b307
author Olivier Masse <olivier.masse@nxp.com> Wed Oct 24 16:32:27 2018 +0200
committer Jacky Bai <ping.bai@nxp.com> Fri Jan 25 18:51:17 2019 +0800
tree 7a4bdd68b3f31af494ab8ceb035f9e1b6fa90d0b
parent b917e33ea9ebb359fbf5a4c39db6bdf4dab21b43

MMIOT-180: ddr address is 33bit width, but rdc memory region register is 32bit. So we use [32:1] as the configuration value

Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
(cherry picked from commit a15779ce1b5c5b1213f8ff2978cdae7729c8c5c8)

plat/imx/imx8mm/imx8mm_bl31_setup.c

diff --git a/plat/imx/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8mm/imx8mm_bl31_setup.c
index 1fc7faf..867985d 100644
--- a/plat/imx/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8mm/imx8mm_bl31_setup.c
@@ -97,7 +97,7 @@
 	/* Domain 2 no write access to memory region below decrypted video */
 	/* Prevent VPU to decode outside secure decoded buffer */
 	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[2].mrsa), 0);
-	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[2].mrea), DECRYPTED_BUFFER_START - IMX_DDR_BASE);
+	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[2].mrea), (DECRYPTED_BUFFER_START - IMX_DDR_BASE) >> 1);
 	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[2].mrc), 0xC00000AF);
 #endif // DECRYPTED_BUFFER_START
 
@@ -105,23 +105,23 @@
 	NOTICE("RDC setup memory_region[0] decrypted buffer DID0 W DID2 R/W\n");
 	/* Domain 0 memory region W decrypted video */
 	/* Domain 2 memory region R decrypted video */
-	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[0].mrsa), DECRYPTED_BUFFER_START - IMX_DDR_BASE);
-	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[0].mrea), DECRYPTED_BUFFER_END - IMX_DDR_BASE);
+	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[0].mrsa), (DECRYPTED_BUFFER_START - IMX_DDR_BASE) >> 1);
+	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[0].mrea), (DECRYPTED_BUFFER_END - IMX_DDR_BASE) >> 1);
 	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[0].mrc), 0xC0000061);
 #endif // DECRYPTED_BUFFER_END
 
 #ifdef DECODED_BUFFER_END
 	NOTICE("RDC setup memory_region[1] decoded buffer DID2 R/W DID3 R/W\n");
 	/* Domain 1+2 memory region R/W decoded video */
-	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[1].mrsa), DECODED_BUFFER_START - IMX_DDR_BASE);
-	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[1].mrea), DECODED_BUFFER_END - IMX_DDR_BASE); 
+	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[1].mrsa), (DECODED_BUFFER_START - IMX_DDR_BASE) >> 1);
+	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[1].mrea), (DECODED_BUFFER_END - IMX_DDR_BASE) >> 1);
 	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[1].mrc), 0xC000003D);
 
 	/* Domain 1+2+3 no access to memory region above decoded video */
 	/* Only CPU in secure mode can access TEE memory region (cf TZASC configuration) */
-	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[3].mrsa), DECODED_BUFFER_END - IMX_DDR_BASE);
-	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[3].mrea), 0xC0000000 - IMX_DDR_BASE);
-	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[3].mrc), 0xC0000003);
+	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[3].mrsa), (DECODED_BUFFER_END - IMX_DDR_BASE) >> 1);
+	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[3].mrea), (0xC0000000 - IMX_DDR_BASE) >> 1);
+	mmio_write_32((uintptr_t)&(imx_rdc->mem_region[3].mrc), 0xC00000C3);
 #endif // DECODED_BUFFER_END
 
 #endif // RDC_DISABLED