plat: imx8mm: enable rbc by default for LPM mode
when PLAT(SCU) domain power down is enabled in
WAIT or STOP mode. enable RBC by default to make
sure SCU can be power down successfully even if
the wakeup ITQ is pending.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 5cf4479384ba41a01c7f8c63a245215213b11701)
diff --git a/plat/imx/imx8mm/gpc.c b/plat/imx/imx8mm/gpc.c
index d3d43c9..8c6e3c1 100644
--- a/plat/imx/imx8mm/gpc.c
+++ b/plat/imx/imx8mm/gpc.c
@@ -50,6 +50,7 @@
#define A53_LPM_WAIT 0x5
#define A53_LPM_STOP 0xa
#define A53_CLK_ON_LPM (1 << 14)
+#define SLPCR_RBC_SHIFT 24
#define MST_CPU_MAPPING 0x18
@@ -498,7 +499,8 @@
uint32_t val;
val = mmio_read_32(IMX_GPC_BASE + SLPCR);
- val |= (0x3f << 24);
+ val |= SLPCR_RBC_EN;
+ val |= (0x8 << SLPCR_RBC_SHIFT);
mmio_write_32(IMX_GPC_BASE + SLPCR, val);
}
@@ -507,7 +509,8 @@
uint32_t val;
val = mmio_read_32(IMX_GPC_BASE + SLPCR);
- val &= ~(0x3f << 24);
+ val &= ~(SLPCR_RBC_EN);
+ val &= ~(0x3f << SLPCR_RBC_SHIFT);
mmio_write_32(IMX_GPC_BASE + SLPCR, val);
}
@@ -985,6 +988,8 @@
val &= ~SLPCR_EN_DSM;
/* enable the fast wakeup wait mode */
val |= SLPCR_A53_FASTWUP_WAIT;
+ /* clear the RBC */
+ val &= ~(0x3f << SLPCR_RBC_SHIFT);
/* TODO if M4 is not enabled, clear more SLPCR bits */
mmio_write_32(IMX_GPC_BASE + SLPCR, val);
diff --git a/plat/imx/imx8mm/imx8mm_psci.c b/plat/imx/imx8mm/imx8mm_psci.c
index e967476..8a8cd95 100644
--- a/plat/imx/imx8mm/imx8mm_psci.c
+++ b/plat/imx/imx8mm/imx8mm_psci.c
@@ -7,6 +7,7 @@
#include <arch.h>
#include <arch_helpers.h>
#include <debug.h>
+#include <delay_timer.h>
#include <stdbool.h>
#include <dram.h>
#include <plat_imx8.h>
@@ -143,15 +144,16 @@
/* clear the system wakeup setting */
imx_set_sys_wakeup(core_id, false);
imx_anamix_post_resume();
- imx_clear_rbc_count();
if (!imx_is_m4_enabled() || !imx_m4_lpa_active())
dram_exit_retention();
noc_wrapper_post_resume(core_id);
}
/* check the cluster level power status */
- if (!is_local_state_run(CLUSTER_PWR_STATE(target_state)))
+ if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) {
+ imx_clear_rbc_count();
imx_set_cluster_powerdown(core_id, PSCI_LOCAL_STATE_RUN);
+ }
/* check the core level power status */
if (is_local_state_off(CORE_PWR_STATE(target_state))) {
@@ -207,10 +209,17 @@
void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
{
- if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) {
+ /*
+ * before enter WAIT or STOP mode with PLAT(SCU) power down,
+ * rbc count need to be enabled to make sure PLAT is
+ * power down successfully even if the the wakeup IRQ is pending
+ * early before the power down sequence. the RBC counter is
+ * drived by the 32K OSC, so delay 30us to make sure the counter
+ * is really running.
+ */
+ if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) {
imx_set_rbc_count();
-
- /* TODO need to workaround the PLL disable glitch */
+ udelay(30);
}
while (1)
