MLK-18619: [MX8MM-EVK]CSU_RDC: enable csu_rdc test in ATF make the board crash
csu_rdc test in ATF makes use of GPIO 4 and 5. Unfortunatly GPIO5 is
being used by u-boot. This is why u-boot crashes.
Changing the peripherals to protect, instead of gpio4 and 5, use csu
and rdc registers instead.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
(cherry picked from commit fe1cd0abc6c57cc59312ab751dd015cb149d7100)
diff --git a/plat/imx/common/imx8m/imx_csu.c b/plat/imx/common/imx8m/imx_csu.c
index 85c1caf..1bb89d7 100644
--- a/plat/imx/common/imx8m/imx_csu.c
+++ b/plat/imx/common/imx8m/imx_csu.c
@@ -25,11 +25,7 @@
{CSU_CSLn_GPIO2, CSU_RW, 0},
{CSU_CSLn_GPIO3, CSU_RW, 0},
{CSU_CSLn_GPIO4, CSU_RW, 0},
-#if defined (CSU_RDC_TEST)
- {CSU_CSLn_GPIO5, CSU_SSRW, 0},
-#else
{CSU_CSLn_GPIO5, CSU_RW, 0},
-#endif
{CSU_CSLn_Reserved1, CSU_RW, 0},
{CSU_CSLn_ANA_TSENSOR, CSU_RW, 0},
{CSU_CSLn_ANA_OSC, CSU_RW, 0},
@@ -52,7 +48,11 @@
{CSU_CSLn_GPC, CSU_RW, 0},
{CSU_CSLn_SEMAPHORE1, CSU_RW, 0},
{CSU_CSLn_SEMAPHORE2, CSU_RW, 0},
+#if defined(CSU_RDC_TEST)
+ {CSU_CSLn_RDC, CSU_SSRW, 0},
+#else
{CSU_CSLn_RDC, CSU_RW, 0},
+#endif
{CSU_CSLn_CSU, CSU_RW, 0},
{CSU_CSLn_MST0, CSU_RW, 0},
{CSU_CSLn_MST1, CSU_RW, 0},
diff --git a/plat/imx/common/imx8m/imx_rdc.c b/plat/imx/common/imx8m/imx_rdc.c
index 1929c99..337db73 100644
--- a/plat/imx/common/imx8m/imx_rdc.c
+++ b/plat/imx/common/imx8m/imx_rdc.c
@@ -145,7 +145,7 @@
#if defined (CSU_RDC_TEST)
/* Default peripherals settings as an example */
static struct rdc_pdap_conf periph_config[] = {
- {RDC_PDAP_GPIO4, 0x30, 0},
+ {RDC_PDAP_CSU, 0x30, 0},
};
diff --git a/plat/imx/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8mm/imx8mm_bl31_setup.c
index 1820c4b..0729501 100644
--- a/plat/imx/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8mm/imx8mm_bl31_setup.c
@@ -187,13 +187,12 @@
static console_uart_t console;
#endif
-#if !defined (CSU_RDC_TEST)
int i;
/* enable CSU NS access permission */
for (i = 0; i < 64; i++) {
- mmio_write_32(0x303e0000 + i * 4, 0xffffffff);
+ mmio_write_32(0x303e0000 + i * 4, 0x00ff00ff);
}
-#endif
+
/* config the aips access permission */
imx8mm_aips_config();
