tree b6038b0675eda2240c0aa9910c9c4ba0c09077e3
parent 4314d4103c5288bf289e487c3ca1aefb0844b53d
author Bai Ping <ping.bai@nxp.com> 1537170486 +0800
committer Jacky Bai <ping.bai@nxp.com> 1548413477 +0800

plat: imx8mq: add 100us delay after USB OTG SRC bit 0 clear

After the SRC bit clear, we must wait for a while to make sure
the operation is finished.

for USB OTG, the limitations are:
1. before system clock configuration. ipg clock runs at 12.5MHz.
   delay time should longer than 82us.

2. after system clock configuration. ipg clock runs at 66.5MHz.
   delay time should longer than 15.3us.

so add udelay 100 to safely clear the SRC bit 0.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 7a50e0e390349738b8987b49cc05edeadaeaddbc)