diff --git a/plat/imx/common/include/imx8qm_pads.h b/plat/imx/common/include/imx8qm_pads.h
index 6107bd9..bf77cf8 100644
--- a/plat/imx/common/include/imx8qm_pads.h
+++ b/plat/imx/common/include/imx8qm_pads.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,275 +20,276 @@
  * @name Pad Definitions
  */
 /*@{*/
-#define SC_P_SIM0_CLK                            0	/* DMA.SIM0.CLK, LSIO.GPIO0.IO00 */
-#define SC_P_SIM0_RST                            1	/* DMA.SIM0.RST, LSIO.GPIO0.IO01 */
-#define SC_P_SIM0_IO                             2	/* DMA.SIM0.IO, LSIO.GPIO0.IO02 */
-#define SC_P_SIM0_PD                             3	/* DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */
-#define SC_P_SIM0_POWER_EN                       4	/* DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */
-#define SC_P_SIM0_GPIO0_00                       5	/* DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM           6	/*  */
-#define SC_P_M40_I2C0_SCL                        7	/* M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */
-#define SC_P_M40_I2C0_SDA                        8	/* M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */
-#define SC_P_M40_GPIO0_00                        9	/* M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */
-#define SC_P_M40_GPIO0_01                        10	/* M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */
-#define SC_P_M41_I2C0_SCL                        11	/* M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */
-#define SC_P_M41_I2C0_SDA                        12	/* M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */
-#define SC_P_M41_GPIO0_00                        13	/* M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */
-#define SC_P_M41_GPIO0_01                        14	/* M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */
-#define SC_P_GPT0_CLK                            15	/* LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */
-#define SC_P_GPT0_CAPTURE                        16	/* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */
-#define SC_P_GPT0_COMPARE                        17	/* LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */
-#define SC_P_GPT1_CLK                            18	/* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
-#define SC_P_GPT1_CAPTURE                        19	/* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */
-#define SC_P_GPT1_COMPARE                        20	/* LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
-#define SC_P_UART0_RX                            21	/* DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */
-#define SC_P_UART0_TX                            22	/* DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */
-#define SC_P_UART0_RTS_B                         23	/* DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */
-#define SC_P_UART0_CTS_B                         24	/* DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */
-#define SC_P_UART1_TX                            25	/* DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */
-#define SC_P_UART1_RX                            26	/* DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */
-#define SC_P_UART1_RTS_B                         27	/* DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */
-#define SC_P_UART1_CTS_B                         28	/* DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH        29	/*  */
-#define SC_P_SCU_PMIC_MEMC_ON                    30	/* SCU.GPIO0.IOXX_PMIC_MEMC_ON */
-#define SC_P_SCU_WDOG_OUT                        31	/* SCU.WDOG0.WDOG_OUT */
-#define SC_P_PMIC_I2C_SDA                        32	/* SCU.PMIC_I2C.SDA */
-#define SC_P_PMIC_I2C_SCL                        33	/* SCU.PMIC_I2C.SCL */
-#define SC_P_PMIC_EARLY_WARNING                  34	/* SCU.PMIC_EARLY_WARNING */
-#define SC_P_PMIC_INT_B                          35	/* SCU.DSC.PMIC_INT_B */
-#define SC_P_SCU_GPIO0_00                        36	/* SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */
-#define SC_P_SCU_GPIO0_01                        37	/* SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */
-#define SC_P_SCU_GPIO0_02                        38	/* SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */
-#define SC_P_SCU_GPIO0_03                        39	/* SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */
-#define SC_P_SCU_GPIO0_04                        40	/* SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */
-#define SC_P_SCU_GPIO0_05                        41	/* SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */
-#define SC_P_SCU_GPIO0_06                        42	/* SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */
-#define SC_P_SCU_GPIO0_07                        43	/* SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */
-#define SC_P_SCU_BOOT_MODE0                      44	/* SCU.DSC.BOOT_MODE0 */
-#define SC_P_SCU_BOOT_MODE1                      45	/* SCU.DSC.BOOT_MODE1 */
-#define SC_P_SCU_BOOT_MODE2                      46	/* SCU.DSC.BOOT_MODE2 */
-#define SC_P_SCU_BOOT_MODE3                      47	/* SCU.DSC.BOOT_MODE3 */
-#define SC_P_SCU_BOOT_MODE4                      48	/* SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
-#define SC_P_SCU_BOOT_MODE5                      49	/* SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
-#define SC_P_LVDS0_GPIO00                        50	/* LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
-#define SC_P_LVDS0_GPIO01                        51	/* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
-#define SC_P_LVDS0_I2C0_SCL                      52	/* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
-#define SC_P_LVDS0_I2C0_SDA                      53	/* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
-#define SC_P_LVDS0_I2C1_SCL                      54	/* LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
-#define SC_P_LVDS0_I2C1_SDA                      55	/* LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
-#define SC_P_LVDS1_GPIO00                        56	/* LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
-#define SC_P_LVDS1_GPIO01                        57	/* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
-#define SC_P_LVDS1_I2C0_SCL                      58	/* LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
-#define SC_P_LVDS1_I2C0_SDA                      59	/* LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
-#define SC_P_LVDS1_I2C1_SCL                      60	/* LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
-#define SC_P_LVDS1_I2C1_SDA                      61	/* LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO      62	/*  */
-#define SC_P_MIPI_DSI0_I2C0_SCL                  63	/* MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
-#define SC_P_MIPI_DSI0_I2C0_SDA                  64	/* MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
-#define SC_P_MIPI_DSI0_GPIO0_00                  65	/* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */
-#define SC_P_MIPI_DSI0_GPIO0_01                  66	/* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
-#define SC_P_MIPI_DSI1_I2C0_SCL                  67	/* MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
-#define SC_P_MIPI_DSI1_I2C0_SDA                  68	/* MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
-#define SC_P_MIPI_DSI1_GPIO0_00                  69	/* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */
-#define SC_P_MIPI_DSI1_GPIO0_01                  70	/* MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO   71	/*  */
-#define SC_P_MIPI_CSI0_MCLK_OUT                  72	/* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
-#define SC_P_MIPI_CSI0_I2C0_SCL                  73	/* MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */
-#define SC_P_MIPI_CSI0_I2C0_SDA                  74	/* MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */
-#define SC_P_MIPI_CSI0_GPIO0_00                  75	/* MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */
-#define SC_P_MIPI_CSI0_GPIO0_01                  76	/* MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */
-#define SC_P_MIPI_CSI1_MCLK_OUT                  77	/* MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
-#define SC_P_MIPI_CSI1_GPIO0_00                  78	/* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
-#define SC_P_MIPI_CSI1_GPIO0_01                  79	/* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
-#define SC_P_MIPI_CSI1_I2C0_SCL                  80	/* MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
-#define SC_P_MIPI_CSI1_I2C0_SDA                  81	/* MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
-#define SC_P_HDMI_TX0_TS_SCL                     82	/* HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
-#define SC_P_HDMI_TX0_TS_SDA                     83	/* HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
-#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO          84	/*  */
-#define SC_P_ESAI1_FSR                           85	/* AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
-#define SC_P_ESAI1_FST                           86	/* AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */
-#define SC_P_ESAI1_SCKR                          87	/* AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
-#define SC_P_ESAI1_SCKT                          88	/* AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */
-#define SC_P_ESAI1_TX0                           89	/* AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */
-#define SC_P_ESAI1_TX1                           90	/* AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */
-#define SC_P_ESAI1_TX2_RX3                       91	/* AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */
-#define SC_P_ESAI1_TX3_RX2                       92	/* AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */
-#define SC_P_ESAI1_TX4_RX1                       93	/* AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */
-#define SC_P_ESAI1_TX5_RX0                       94	/* AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */
-#define SC_P_SPDIF0_RX                           95	/* AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */
-#define SC_P_SPDIF0_TX                           96	/* AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */
-#define SC_P_SPDIF0_EXT_CLK                      97	/* AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */
-#define SC_P_SPI3_SCK                            98	/* DMA.SPI3.SCK, LSIO.GPIO2.IO17 */
-#define SC_P_SPI3_SDO                            99	/* DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */
-#define SC_P_SPI3_SDI                            100	/* DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */
-#define SC_P_SPI3_CS0                            101	/* DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */
-#define SC_P_SPI3_CS1                            102	/* DMA.SPI3.CS1, LSIO.GPIO2.IO21 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB       103	/*  */
-#define SC_P_ESAI0_FSR                           104	/* AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */
-#define SC_P_ESAI0_FST                           105	/* AUD.ESAI0.FST, LSIO.GPIO2.IO23 */
-#define SC_P_ESAI0_SCKR                          106	/* AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */
-#define SC_P_ESAI0_SCKT                          107	/* AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */
-#define SC_P_ESAI0_TX0                           108	/* AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */
-#define SC_P_ESAI0_TX1                           109	/* AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */
-#define SC_P_ESAI0_TX2_RX3                       110	/* AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */
-#define SC_P_ESAI0_TX3_RX2                       111	/* AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */
-#define SC_P_ESAI0_TX4_RX1                       112	/* AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */
-#define SC_P_ESAI0_TX5_RX0                       113	/* AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */
-#define SC_P_MCLK_IN0                            114	/* AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */
-#define SC_P_MCLK_OUT0                           115	/* AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC       116	/*  */
-#define SC_P_SPI0_SCK                            117	/* DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */
-#define SC_P_SPI0_SDO                            118	/* DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */
-#define SC_P_SPI0_SDI                            119	/* DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */
-#define SC_P_SPI0_CS0                            120	/* DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */
-#define SC_P_SPI0_CS1                            121	/* DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */
-#define SC_P_SPI2_SCK                            122	/* DMA.SPI2.SCK, LSIO.GPIO3.IO07 */
-#define SC_P_SPI2_SDO                            123	/* DMA.SPI2.SDO, LSIO.GPIO3.IO08 */
-#define SC_P_SPI2_SDI                            124	/* DMA.SPI2.SDI, LSIO.GPIO3.IO09 */
-#define SC_P_SPI2_CS0                            125	/* DMA.SPI2.CS0, LSIO.GPIO3.IO10 */
-#define SC_P_SPI2_CS1                            126	/* DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */
-#define SC_P_SAI1_RXC                            127	/* AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */
-#define SC_P_SAI1_RXD                            128	/* AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */
-#define SC_P_SAI1_RXFS                           129	/* AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */
-#define SC_P_SAI1_TXC                            130	/* AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */
-#define SC_P_SAI1_TXD                            131	/* AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */
-#define SC_P_SAI1_TXFS                           132	/* AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT       133	/*  */
-#define SC_P_ADC_IN7                             134	/* DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */
-#define SC_P_ADC_IN6                             135	/* DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */
-#define SC_P_ADC_IN5                             136	/* DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */
-#define SC_P_ADC_IN4                             137	/* DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */
-#define SC_P_ADC_IN3                             138	/* DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */
-#define SC_P_ADC_IN2                             139	/* DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */
-#define SC_P_ADC_IN1                             140	/* DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */
-#define SC_P_ADC_IN0                             141	/* DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */
-#define SC_P_MLB_SIG                             142	/* CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */
-#define SC_P_MLB_CLK                             143	/* CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */
-#define SC_P_MLB_DATA                            144	/* CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT       145	/*  */
-#define SC_P_FLEXCAN0_RX                         146	/* DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */
-#define SC_P_FLEXCAN0_TX                         147	/* DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */
-#define SC_P_FLEXCAN1_RX                         148	/* DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */
-#define SC_P_FLEXCAN1_TX                         149	/* DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */
-#define SC_P_FLEXCAN2_RX                         150	/* DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */
-#define SC_P_FLEXCAN2_TX                         151	/* DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR       152	/*  */
-#define SC_P_USB_SS3_TC0                         153	/* DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */
-#define SC_P_USB_SS3_TC1                         154	/* DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
-#define SC_P_USB_SS3_TC2                         155	/* DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */
-#define SC_P_USB_SS3_TC3                         156	/* DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
-#define SC_P_COMP_CTL_GPIO_3V3_USB3IO            157	/*  */
-#define SC_P_USDHC1_RESET_B                      158	/* CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */
-#define SC_P_USDHC1_VSELECT                      159	/* CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */
-#define SC_P_USDHC2_RESET_B                      160	/* CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */
-#define SC_P_USDHC2_VSELECT                      161	/* CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */
-#define SC_P_USDHC2_WP                           162	/* CONN.USDHC2.WP, LSIO.GPIO4.IO11 */
-#define SC_P_USDHC2_CD_B                         163	/* CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP       164	/*  */
-#define SC_P_ENET0_MDIO                          165	/* CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */
-#define SC_P_ENET0_MDC                           166	/* CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */
-#define SC_P_ENET0_REFCLK_125M_25M               167	/* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */
-#define SC_P_ENET1_REFCLK_125M_25M               168	/* CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */
-#define SC_P_ENET1_MDIO                          169	/* CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */
-#define SC_P_ENET1_MDC                           170	/* CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT        171	/*  */
-#define SC_P_QSPI1A_SS0_B                        172	/* LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */
-#define SC_P_QSPI1A_SS1_B                        173	/* LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */
-#define SC_P_QSPI1A_SCLK                         174	/* LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */
-#define SC_P_QSPI1A_DQS                          175	/* LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */
-#define SC_P_QSPI1A_DATA3                        176	/* LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */
-#define SC_P_QSPI1A_DATA2                        177	/* LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */
-#define SC_P_QSPI1A_DATA1                        178	/* LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */
-#define SC_P_QSPI1A_DATA0                        179	/* LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1         180	/*  */
-#define SC_P_QSPI0A_DATA0                        181	/* LSIO.QSPI0A.DATA0 */
-#define SC_P_QSPI0A_DATA1                        182	/* LSIO.QSPI0A.DATA1 */
-#define SC_P_QSPI0A_DATA2                        183	/* LSIO.QSPI0A.DATA2 */
-#define SC_P_QSPI0A_DATA3                        184	/* LSIO.QSPI0A.DATA3 */
-#define SC_P_QSPI0A_DQS                          185	/* LSIO.QSPI0A.DQS */
-#define SC_P_QSPI0A_SS0_B                        186	/* LSIO.QSPI0A.SS0_B */
-#define SC_P_QSPI0A_SS1_B                        187	/* LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */
-#define SC_P_QSPI0A_SCLK                         188	/* LSIO.QSPI0A.SCLK */
-#define SC_P_QSPI0B_SCLK                         189	/* LSIO.QSPI0B.SCLK */
-#define SC_P_QSPI0B_DATA0                        190	/* LSIO.QSPI0B.DATA0 */
-#define SC_P_QSPI0B_DATA1                        191	/* LSIO.QSPI0B.DATA1 */
-#define SC_P_QSPI0B_DATA2                        192	/* LSIO.QSPI0B.DATA2 */
-#define SC_P_QSPI0B_DATA3                        193	/* LSIO.QSPI0B.DATA3 */
-#define SC_P_QSPI0B_DQS                          194	/* LSIO.QSPI0B.DQS */
-#define SC_P_QSPI0B_SS0_B                        195	/* LSIO.QSPI0B.SS0_B */
-#define SC_P_QSPI0B_SS1_B                        196	/* LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0         197	/*  */
-#define SC_P_PCIE_CTRL0_CLKREQ_B                 198	/* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */
-#define SC_P_PCIE_CTRL0_WAKE_B                   199	/* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */
-#define SC_P_PCIE_CTRL0_PERST_B                  200	/* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */
-#define SC_P_PCIE_CTRL1_CLKREQ_B                 201	/* HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */
-#define SC_P_PCIE_CTRL1_WAKE_B                   202	/* HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */
-#define SC_P_PCIE_CTRL1_PERST_B                  203	/* HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP       204	/*  */
-#define SC_P_USB_HSIC0_DATA                      205	/* CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */
-#define SC_P_USB_HSIC0_STROBE                    206	/* CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */
-#define SC_P_CALIBRATION_0_HSIC                  207	/*  */
-#define SC_P_CALIBRATION_1_HSIC                  208	/*  */
-#define SC_P_EMMC0_CLK                           209	/* CONN.EMMC0.CLK, CONN.NAND.READY_B */
-#define SC_P_EMMC0_CMD                           210	/* CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */
-#define SC_P_EMMC0_DATA0                         211	/* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */
-#define SC_P_EMMC0_DATA1                         212	/* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */
-#define SC_P_EMMC0_DATA2                         213	/* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */
-#define SC_P_EMMC0_DATA3                         214	/* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */
-#define SC_P_EMMC0_DATA4                         215	/* CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */
-#define SC_P_EMMC0_DATA5                         216	/* CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */
-#define SC_P_EMMC0_DATA6                         217	/* CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */
-#define SC_P_EMMC0_DATA7                         218	/* CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */
-#define SC_P_EMMC0_STROBE                        219	/* CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */
-#define SC_P_EMMC0_RESET_B                       220	/* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX        221	/*  */
-#define SC_P_USDHC1_CLK                          222	/* CONN.USDHC1.CLK, AUD.MQS.R */
-#define SC_P_USDHC1_CMD                          223	/* CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */
-#define SC_P_USDHC1_DATA0                        224	/* CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */
-#define SC_P_USDHC1_DATA1                        225	/* CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */
-#define SC_P_CTL_NAND_RE_P_N                     226	/*  */
-#define SC_P_USDHC1_DATA2                        227	/* CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
-#define SC_P_USDHC1_DATA3                        228	/* CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
-#define SC_P_CTL_NAND_DQS_P_N                    229	/*  */
-#define SC_P_USDHC1_DATA4                        230	/* CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */
-#define SC_P_USDHC1_DATA5                        231	/* CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */
-#define SC_P_USDHC1_DATA6                        232	/* CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
-#define SC_P_USDHC1_DATA7                        233	/* CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */
-#define SC_P_USDHC1_STROBE                       234	/* CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2         235	/*  */
-#define SC_P_USDHC2_CLK                          236	/* CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */
-#define SC_P_USDHC2_CMD                          237	/* CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */
-#define SC_P_USDHC2_DATA0                        238	/* CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */
-#define SC_P_USDHC2_DATA1                        239	/* CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */
-#define SC_P_USDHC2_DATA2                        240	/* CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */
-#define SC_P_USDHC2_DATA3                        241	/* CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3         242	/*  */
-#define SC_P_ENET0_RGMII_TXC                     243	/* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */
-#define SC_P_ENET0_RGMII_TX_CTL                  244	/* CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */
-#define SC_P_ENET0_RGMII_TXD0                    245	/* CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */
-#define SC_P_ENET0_RGMII_TXD1                    246	/* CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */
-#define SC_P_ENET0_RGMII_TXD2                    247	/* CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */
-#define SC_P_ENET0_RGMII_TXD3                    248	/* CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */
-#define SC_P_ENET0_RGMII_RXC                     249	/* CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */
-#define SC_P_ENET0_RGMII_RX_CTL                  250	/* CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */
-#define SC_P_ENET0_RGMII_RXD0                    251	/* CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */
-#define SC_P_ENET0_RGMII_RXD1                    252	/* CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */
-#define SC_P_ENET0_RGMII_RXD2                    253	/* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */
-#define SC_P_ENET0_RGMII_RXD3                    254	/* CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB    255	/*  */
-#define SC_P_ENET1_RGMII_TXC                     256	/* CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */
-#define SC_P_ENET1_RGMII_TX_CTL                  257	/* CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */
-#define SC_P_ENET1_RGMII_TXD0                    258	/* CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */
-#define SC_P_ENET1_RGMII_TXD1                    259	/* CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */
-#define SC_P_ENET1_RGMII_TXD2                    260	/* CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */
-#define SC_P_ENET1_RGMII_TXD3                    261	/* CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */
-#define SC_P_ENET1_RGMII_RXC                     262	/* CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */
-#define SC_P_ENET1_RGMII_RX_CTL                  263	/* CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */
-#define SC_P_ENET1_RGMII_RXD0                    264	/* CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
-#define SC_P_ENET1_RGMII_RXD1                    265	/* CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
-#define SC_P_ENET1_RGMII_RXD2                    266	/* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
-#define SC_P_ENET1_RGMII_RXD3                    267	/* CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA    268	/*  */
+#define SC_P_SIM0_CLK                            0    /* DMA.SIM0.CLK, LSIO.GPIO0.IO00 */
+#define SC_P_SIM0_RST                            1    /* DMA.SIM0.RST, LSIO.GPIO0.IO01 */
+#define SC_P_SIM0_IO                             2    /* DMA.SIM0.IO, LSIO.GPIO0.IO02 */
+#define SC_P_SIM0_PD                             3    /* DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */
+#define SC_P_SIM0_POWER_EN                       4    /* DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */
+#define SC_P_SIM0_GPIO0_00                       5    /* DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM           6    /*  */
+#define SC_P_M40_I2C0_SCL                        7    /* M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */
+#define SC_P_M40_I2C0_SDA                        8    /* M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */
+#define SC_P_M40_GPIO0_00                        9    /* M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */
+#define SC_P_M40_GPIO0_01                        10   /* M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */
+#define SC_P_M41_I2C0_SCL                        11   /* M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */
+#define SC_P_M41_I2C0_SDA                        12   /* M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */
+#define SC_P_M41_GPIO0_00                        13   /* M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */
+#define SC_P_M41_GPIO0_01                        14   /* M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */
+#define SC_P_GPT0_CLK                            15   /* LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */
+#define SC_P_GPT0_CAPTURE                        16   /* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */
+#define SC_P_GPT0_COMPARE                        17   /* LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */
+#define SC_P_GPT1_CLK                            18   /* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
+#define SC_P_GPT1_CAPTURE                        19   /* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */
+#define SC_P_GPT1_COMPARE                        20   /* LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
+#define SC_P_UART0_RX                            21   /* DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */
+#define SC_P_UART0_TX                            22   /* DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */
+#define SC_P_UART0_RTS_B                         23   /* DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */
+#define SC_P_UART0_CTS_B                         24   /* DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */
+#define SC_P_UART1_TX                            25   /* DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */
+#define SC_P_UART1_RX                            26   /* DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */
+#define SC_P_UART1_RTS_B                         27   /* DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */
+#define SC_P_UART1_CTS_B                         28   /* DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH        29   /*  */
+#define SC_P_SCU_PMIC_MEMC_ON                    30   /* SCU.GPIO0.IOXX_PMIC_MEMC_ON */
+#define SC_P_SCU_WDOG_OUT                        31   /* SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SDA                        32   /* SCU.PMIC_I2C.SDA */
+#define SC_P_PMIC_I2C_SCL                        33   /* SCU.PMIC_I2C.SCL */
+#define SC_P_PMIC_EARLY_WARNING                  34   /* SCU.PMIC_EARLY_WARNING */
+#define SC_P_PMIC_INT_B                          35   /* SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00                        36   /* SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */
+#define SC_P_SCU_GPIO0_01                        37   /* SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */
+#define SC_P_SCU_GPIO0_02                        38   /* SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */
+#define SC_P_SCU_GPIO0_03                        39   /* SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */
+#define SC_P_SCU_GPIO0_04                        40   /* SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */
+#define SC_P_SCU_GPIO0_05                        41   /* SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */
+#define SC_P_SCU_GPIO0_06                        42   /* SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */
+#define SC_P_SCU_GPIO0_07                        43   /* SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */
+#define SC_P_SCU_BOOT_MODE0                      44   /* SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE1                      45   /* SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE2                      46   /* SCU.DSC.BOOT_MODE2 */
+#define SC_P_SCU_BOOT_MODE3                      47   /* SCU.DSC.BOOT_MODE3 */
+#define SC_P_SCU_BOOT_MODE4                      48   /* SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
+#define SC_P_SCU_BOOT_MODE5                      49   /* SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
+#define SC_P_LVDS0_GPIO00                        50   /* LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
+#define SC_P_LVDS0_GPIO01                        51   /* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
+#define SC_P_LVDS0_I2C0_SCL                      52   /* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
+#define SC_P_LVDS0_I2C0_SDA                      53   /* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
+#define SC_P_LVDS0_I2C1_SCL                      54   /* LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
+#define SC_P_LVDS0_I2C1_SDA                      55   /* LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
+#define SC_P_LVDS1_GPIO00                        56   /* LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
+#define SC_P_LVDS1_GPIO01                        57   /* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
+#define SC_P_LVDS1_I2C0_SCL                      58   /* LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
+#define SC_P_LVDS1_I2C0_SDA                      59   /* LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
+#define SC_P_LVDS1_I2C1_SCL                      60   /* LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
+#define SC_P_LVDS1_I2C1_SDA                      61   /* LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO      62   /*  */
+#define SC_P_MIPI_DSI0_I2C0_SCL                  63   /* MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
+#define SC_P_MIPI_DSI0_I2C0_SDA                  64   /* MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
+#define SC_P_MIPI_DSI0_GPIO0_00                  65   /* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */
+#define SC_P_MIPI_DSI0_GPIO0_01                  66   /* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
+#define SC_P_MIPI_DSI1_I2C0_SCL                  67   /* MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
+#define SC_P_MIPI_DSI1_I2C0_SDA                  68   /* MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
+#define SC_P_MIPI_DSI1_GPIO0_00                  69   /* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */
+#define SC_P_MIPI_DSI1_GPIO0_01                  70   /* MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO   71   /*  */
+#define SC_P_MIPI_CSI0_MCLK_OUT                  72   /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
+#define SC_P_MIPI_CSI0_I2C0_SCL                  73   /* MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */
+#define SC_P_MIPI_CSI0_I2C0_SDA                  74   /* MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */
+#define SC_P_MIPI_CSI0_GPIO0_00                  75   /* MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_CSI0_GPIO0_01                  76   /* MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_CSI1_MCLK_OUT                  77   /* MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
+#define SC_P_MIPI_CSI1_GPIO0_00                  78   /* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
+#define SC_P_MIPI_CSI1_GPIO0_01                  79   /* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
+#define SC_P_MIPI_CSI1_I2C0_SCL                  80   /* MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
+#define SC_P_MIPI_CSI1_I2C0_SDA                  81   /* MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
+#define SC_P_HDMI_TX0_TS_SCL                     82   /* HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
+#define SC_P_HDMI_TX0_TS_SDA                     83   /* HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
+#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO          84   /*  */
+#define SC_P_ESAI1_FSR                           85   /* AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
+#define SC_P_ESAI1_FST                           86   /* AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */
+#define SC_P_ESAI1_SCKR                          87   /* AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
+#define SC_P_ESAI1_SCKT                          88   /* AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */
+#define SC_P_ESAI1_TX0                           89   /* AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */
+#define SC_P_ESAI1_TX1                           90   /* AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */
+#define SC_P_ESAI1_TX2_RX3                       91   /* AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */
+#define SC_P_ESAI1_TX3_RX2                       92   /* AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */
+#define SC_P_ESAI1_TX4_RX1                       93   /* AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */
+#define SC_P_ESAI1_TX5_RX0                       94   /* AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */
+#define SC_P_SPDIF0_RX                           95   /* AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */
+#define SC_P_SPDIF0_TX                           96   /* AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */
+#define SC_P_SPDIF0_EXT_CLK                      97   /* AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */
+#define SC_P_SPI3_SCK                            98   /* DMA.SPI3.SCK, LSIO.GPIO2.IO17 */
+#define SC_P_SPI3_SDO                            99   /* DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */
+#define SC_P_SPI3_SDI                            100  /* DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */
+#define SC_P_SPI3_CS0                            101  /* DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */
+#define SC_P_SPI3_CS1                            102  /* DMA.SPI3.CS1, LSIO.GPIO2.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB       103  /*  */
+#define SC_P_ESAI0_FSR                           104  /* AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */
+#define SC_P_ESAI0_FST                           105  /* AUD.ESAI0.FST, LSIO.GPIO2.IO23 */
+#define SC_P_ESAI0_SCKR                          106  /* AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */
+#define SC_P_ESAI0_SCKT                          107  /* AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */
+#define SC_P_ESAI0_TX0                           108  /* AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */
+#define SC_P_ESAI0_TX1                           109  /* AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */
+#define SC_P_ESAI0_TX2_RX3                       110  /* AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */
+#define SC_P_ESAI0_TX3_RX2                       111  /* AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */
+#define SC_P_ESAI0_TX4_RX1                       112  /* AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */
+#define SC_P_ESAI0_TX5_RX0                       113  /* AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */
+#define SC_P_MCLK_IN0                            114  /* AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */
+#define SC_P_MCLK_OUT0                           115  /* AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC       116  /*  */
+#define SC_P_SPI0_SCK                            117  /* DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */
+#define SC_P_SPI0_SDO                            118  /* DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */
+#define SC_P_SPI0_SDI                            119  /* DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */
+#define SC_P_SPI0_CS0                            120  /* DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */
+#define SC_P_SPI0_CS1                            121  /* DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */
+#define SC_P_SPI2_SCK                            122  /* DMA.SPI2.SCK, LSIO.GPIO3.IO07 */
+#define SC_P_SPI2_SDO                            123  /* DMA.SPI2.SDO, LSIO.GPIO3.IO08 */
+#define SC_P_SPI2_SDI                            124  /* DMA.SPI2.SDI, LSIO.GPIO3.IO09 */
+#define SC_P_SPI2_CS0                            125  /* DMA.SPI2.CS0, LSIO.GPIO3.IO10 */
+#define SC_P_SPI2_CS1                            126  /* DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */
+#define SC_P_SAI1_RXC                            127  /* AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */
+#define SC_P_SAI1_RXD                            128  /* AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */
+#define SC_P_SAI1_RXFS                           129  /* AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */
+#define SC_P_SAI1_TXC                            130  /* AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */
+#define SC_P_SAI1_TXD                            131  /* AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */
+#define SC_P_SAI1_TXFS                           132  /* AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT       133  /*  */
+#define SC_P_ADC_IN7                             134  /* DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */
+#define SC_P_ADC_IN6                             135  /* DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */
+#define SC_P_ADC_IN5                             136  /* DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */
+#define SC_P_ADC_IN4                             137  /* DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */
+#define SC_P_ADC_IN3                             138  /* DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */
+#define SC_P_ADC_IN2                             139  /* DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */
+#define SC_P_ADC_IN1                             140  /* DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */
+#define SC_P_ADC_IN0                             141  /* DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */
+#define SC_P_MLB_SIG                             142  /* CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */
+#define SC_P_MLB_CLK                             143  /* CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */
+#define SC_P_MLB_DATA                            144  /* CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT       145  /*  */
+#define SC_P_FLEXCAN0_RX                         146  /* DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */
+#define SC_P_FLEXCAN0_TX                         147  /* DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */
+#define SC_P_FLEXCAN1_RX                         148  /* DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */
+#define SC_P_FLEXCAN1_TX                         149  /* DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */
+#define SC_P_FLEXCAN2_RX                         150  /* DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */
+#define SC_P_FLEXCAN2_TX                         151  /* DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR       152  /*  */
+#define SC_P_USB_SS3_TC0                         153  /* DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */
+#define SC_P_USB_SS3_TC1                         154  /* DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
+#define SC_P_USB_SS3_TC2                         155  /* DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */
+#define SC_P_USB_SS3_TC3                         156  /* DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO            157  /*  */
+#define SC_P_USDHC1_RESET_B                      158  /* CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */
+#define SC_P_USDHC1_VSELECT                      159  /* CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */
+#define SC_P_USDHC2_RESET_B                      160  /* CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */
+#define SC_P_USDHC2_VSELECT                      161  /* CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */
+#define SC_P_USDHC2_WP                           162  /* CONN.USDHC2.WP, LSIO.GPIO4.IO11 */
+#define SC_P_USDHC2_CD_B                         163  /* CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP       164  /*  */
+#define SC_P_ENET0_MDIO                          165  /* CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */
+#define SC_P_ENET0_MDC                           166  /* CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */
+#define SC_P_ENET0_REFCLK_125M_25M               167  /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */
+#define SC_P_ENET1_REFCLK_125M_25M               168  /* CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */
+#define SC_P_ENET1_MDIO                          169  /* CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */
+#define SC_P_ENET1_MDC                           170  /* CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT        171  /*  */
+#define SC_P_QSPI1A_SS0_B                        172  /* LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */
+#define SC_P_QSPI1A_SS1_B                        173  /* LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */
+#define SC_P_QSPI1A_SCLK                         174  /* LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */
+#define SC_P_QSPI1A_DQS                          175  /* LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */
+#define SC_P_QSPI1A_DATA3                        176  /* LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */
+#define SC_P_QSPI1A_DATA2                        177  /* LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */
+#define SC_P_QSPI1A_DATA1                        178  /* LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */
+#define SC_P_QSPI1A_DATA0                        179  /* LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1         180  /*  */
+#define SC_P_QSPI0A_DATA0                        181  /* LSIO.QSPI0A.DATA0 */
+#define SC_P_QSPI0A_DATA1                        182  /* LSIO.QSPI0A.DATA1 */
+#define SC_P_QSPI0A_DATA2                        183  /* LSIO.QSPI0A.DATA2 */
+#define SC_P_QSPI0A_DATA3                        184  /* LSIO.QSPI0A.DATA3 */
+#define SC_P_QSPI0A_DQS                          185  /* LSIO.QSPI0A.DQS */
+#define SC_P_QSPI0A_SS0_B                        186  /* LSIO.QSPI0A.SS0_B */
+#define SC_P_QSPI0A_SS1_B                        187  /* LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */
+#define SC_P_QSPI0A_SCLK                         188  /* LSIO.QSPI0A.SCLK */
+#define SC_P_QSPI0B_SCLK                         189  /* LSIO.QSPI0B.SCLK */
+#define SC_P_QSPI0B_DATA0                        190  /* LSIO.QSPI0B.DATA0 */
+#define SC_P_QSPI0B_DATA1                        191  /* LSIO.QSPI0B.DATA1 */
+#define SC_P_QSPI0B_DATA2                        192  /* LSIO.QSPI0B.DATA2 */
+#define SC_P_QSPI0B_DATA3                        193  /* LSIO.QSPI0B.DATA3 */
+#define SC_P_QSPI0B_DQS                          194  /* LSIO.QSPI0B.DQS */
+#define SC_P_QSPI0B_SS0_B                        195  /* LSIO.QSPI0B.SS0_B */
+#define SC_P_QSPI0B_SS1_B                        196  /* LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0         197  /*  */
+#define SC_P_PCIE_CTRL0_CLKREQ_B                 198  /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */
+#define SC_P_PCIE_CTRL0_WAKE_B                   199  /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */
+#define SC_P_PCIE_CTRL0_PERST_B                  200  /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */
+#define SC_P_PCIE_CTRL1_CLKREQ_B                 201  /* HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */
+#define SC_P_PCIE_CTRL1_WAKE_B                   202  /* HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */
+#define SC_P_PCIE_CTRL1_PERST_B                  203  /* HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP       204  /*  */
+#define SC_P_USB_HSIC0_DATA                      205  /* CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */
+#define SC_P_USB_HSIC0_STROBE                    206  /* CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */
+#define SC_P_CALIBRATION_0_HSIC                  207  /*  */
+#define SC_P_CALIBRATION_1_HSIC                  208  /*  */
+#define SC_P_EMMC0_CLK                           209  /* CONN.EMMC0.CLK, CONN.NAND.READY_B */
+#define SC_P_EMMC0_CMD                           210  /* CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */
+#define SC_P_EMMC0_DATA0                         211  /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */
+#define SC_P_EMMC0_DATA1                         212  /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */
+#define SC_P_EMMC0_DATA2                         213  /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */
+#define SC_P_EMMC0_DATA3                         214  /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */
+#define SC_P_EMMC0_DATA4                         215  /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */
+#define SC_P_EMMC0_DATA5                         216  /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */
+#define SC_P_EMMC0_DATA6                         217  /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */
+#define SC_P_EMMC0_DATA7                         218  /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */
+#define SC_P_EMMC0_STROBE                        219  /* CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */
+#define SC_P_EMMC0_RESET_B                       220  /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX        221  /*  */
+#define SC_P_USDHC1_CLK                          222  /* CONN.USDHC1.CLK, AUD.MQS.R */
+#define SC_P_USDHC1_CMD                          223  /* CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */
+#define SC_P_USDHC1_DATA0                        224  /* CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */
+#define SC_P_USDHC1_DATA1                        225  /* CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */
+#define SC_P_CTL_NAND_RE_P_N                     226  /*  */
+#define SC_P_USDHC1_DATA2                        227  /* CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
+#define SC_P_USDHC1_DATA3                        228  /* CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
+#define SC_P_CTL_NAND_DQS_P_N                    229  /*  */
+#define SC_P_USDHC1_DATA4                        230  /* CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */
+#define SC_P_USDHC1_DATA5                        231  /* CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */
+#define SC_P_USDHC1_DATA6                        232  /* CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
+#define SC_P_USDHC1_DATA7                        233  /* CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */
+#define SC_P_USDHC1_STROBE                       234  /* CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2         235  /*  */
+#define SC_P_USDHC2_CLK                          236  /* CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */
+#define SC_P_USDHC2_CMD                          237  /* CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */
+#define SC_P_USDHC2_DATA0                        238  /* CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */
+#define SC_P_USDHC2_DATA1                        239  /* CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */
+#define SC_P_USDHC2_DATA2                        240  /* CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */
+#define SC_P_USDHC2_DATA3                        241  /* CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3         242  /*  */
+#define SC_P_ENET0_RGMII_TXC                     243  /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */
+#define SC_P_ENET0_RGMII_TX_CTL                  244  /* CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */
+#define SC_P_ENET0_RGMII_TXD0                    245  /* CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */
+#define SC_P_ENET0_RGMII_TXD1                    246  /* CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */
+#define SC_P_ENET0_RGMII_TXD2                    247  /* CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */
+#define SC_P_ENET0_RGMII_TXD3                    248  /* CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */
+#define SC_P_ENET0_RGMII_RXC                     249  /* CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */
+#define SC_P_ENET0_RGMII_RX_CTL                  250  /* CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */
+#define SC_P_ENET0_RGMII_RXD0                    251  /* CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */
+#define SC_P_ENET0_RGMII_RXD1                    252  /* CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */
+#define SC_P_ENET0_RGMII_RXD2                    253  /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */
+#define SC_P_ENET0_RGMII_RXD3                    254  /* CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB    255  /*  */
+#define SC_P_ENET1_RGMII_TXC                     256  /* CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */
+#define SC_P_ENET1_RGMII_TX_CTL                  257  /* CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */
+#define SC_P_ENET1_RGMII_TXD0                    258  /* CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */
+#define SC_P_ENET1_RGMII_TXD1                    259  /* CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */
+#define SC_P_ENET1_RGMII_TXD2                    260  /* CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */
+#define SC_P_ENET1_RGMII_TXD3                    261  /* CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */
+#define SC_P_ENET1_RGMII_RXC                     262  /* CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */
+#define SC_P_ENET1_RGMII_RX_CTL                  263  /* CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */
+#define SC_P_ENET1_RGMII_RXD0                    264  /* CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
+#define SC_P_ENET1_RGMII_RXD1                    265  /* CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
+#define SC_P_ENET1_RGMII_RXD2                    266  /* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
+#define SC_P_ENET1_RGMII_RXD3                    267  /* CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA    268  /*  */
 /*@}*/
 
-#endif				/* SC_PADS_H */
+#endif /* SC_PADS_H */
+
diff --git a/plat/imx/common/include/imx8qx_pads.h b/plat/imx/common/include/imx8qx_pads.h
index 0e153bb..453911d 100644
--- a/plat/imx/common/include/imx8qx_pads.h
+++ b/plat/imx/common/include/imx8qx_pads.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,180 +20,181 @@
  * @name Pad Definitions
  */
 /*@{*/
-#define SC_P_PCIE_CTRL0_PERST_B                  0	/* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
-#define SC_P_PCIE_CTRL0_CLKREQ_B                 1	/* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
-#define SC_P_PCIE_CTRL0_WAKE_B                   2	/* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP       3	/*  */
-#define SC_P_USB_SS3_TC0                         4	/* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */
-#define SC_P_USB_SS3_TC1                         5	/* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
-#define SC_P_USB_SS3_TC2                         6	/* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */
-#define SC_P_USB_SS3_TC3                         7	/* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
-#define SC_P_COMP_CTL_GPIO_3V3_USB3IO            8	/*  */
-#define SC_P_EMMC0_CLK                           9	/* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
-#define SC_P_EMMC0_CMD                           10	/* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
-#define SC_P_EMMC0_DATA0                         11	/* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
-#define SC_P_EMMC0_DATA1                         12	/* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
-#define SC_P_EMMC0_DATA2                         13	/* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
-#define SC_P_EMMC0_DATA3                         14	/* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0       15	/*  */
-#define SC_P_EMMC0_DATA4                         16	/* CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */
-#define SC_P_EMMC0_DATA5                         17	/* CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */
-#define SC_P_EMMC0_DATA6                         18	/* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
-#define SC_P_EMMC0_DATA7                         19	/* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */
-#define SC_P_EMMC0_STROBE                        20	/* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */
-#define SC_P_EMMC0_RESET_B                       21	/* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1       22	/*  */
-#define SC_P_USDHC1_RESET_B                      23	/* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */
-#define SC_P_USDHC1_VSELECT                      24	/* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */
-#define SC_P_CTL_NAND_RE_P_N                     25	/*  */
-#define SC_P_USDHC1_WP                           26	/* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */
-#define SC_P_USDHC1_CD_B                         27	/* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */
-#define SC_P_CTL_NAND_DQS_P_N                    28	/*  */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP       29	/*  */
-#define SC_P_USDHC1_CLK                          30	/* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */
-#define SC_P_USDHC1_CMD                          31	/* CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */
-#define SC_P_USDHC1_DATA0                        32	/* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */
-#define SC_P_USDHC1_DATA1                        33	/* CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */
-#define SC_P_USDHC1_DATA2                        34	/* CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */
-#define SC_P_USDHC1_DATA3                        35	/* CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3         36	/*  */
-#define SC_P_ENET0_RGMII_TXC                     37	/* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */
-#define SC_P_ENET0_RGMII_TX_CTL                  38	/* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */
-#define SC_P_ENET0_RGMII_TXD0                    39	/* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */
-#define SC_P_ENET0_RGMII_TXD1                    40	/* CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */
-#define SC_P_ENET0_RGMII_TXD2                    41	/* CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */
-#define SC_P_ENET0_RGMII_TXD3                    42	/* CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0   43	/*  */
-#define SC_P_ENET0_RGMII_RXC                     44	/* CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
-#define SC_P_ENET0_RGMII_RX_CTL                  45	/* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
-#define SC_P_ENET0_RGMII_RXD0                    46	/* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
-#define SC_P_ENET0_RGMII_RXD1                    47	/* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
-#define SC_P_ENET0_RGMII_RXD2                    48	/* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
-#define SC_P_ENET0_RGMII_RXD3                    49	/* CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1   50	/*  */
-#define SC_P_ENET0_REFCLK_125M_25M               51	/* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */
-#define SC_P_ENET0_MDIO                          52	/* CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */
-#define SC_P_ENET0_MDC                           53	/* CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT        54	/*  */
-#define SC_P_ESAI0_FSR                           55	/* ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */
-#define SC_P_ESAI0_FST                           56	/* ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */
-#define SC_P_ESAI0_SCKR                          57	/* ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
-#define SC_P_ESAI0_SCKT                          58	/* ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */
-#define SC_P_ESAI0_TX0                           59	/* ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */
-#define SC_P_ESAI0_TX1                           60	/* ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */
-#define SC_P_ESAI0_TX2_RX3                       61	/* ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */
-#define SC_P_ESAI0_TX3_RX2                       62	/* ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */
-#define SC_P_ESAI0_TX4_RX1                       63	/* ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */
-#define SC_P_ESAI0_TX5_RX0                       64	/* ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */
-#define SC_P_SPDIF0_RX                           65	/* ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */
-#define SC_P_SPDIF0_TX                           66	/* ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */
-#define SC_P_SPDIF0_EXT_CLK                      67	/* ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB       68	/*  */
-#define SC_P_SPI3_SCK                            69	/* ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */
-#define SC_P_SPI3_SDO                            70	/* ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */
-#define SC_P_SPI3_SDI                            71	/* ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */
-#define SC_P_SPI3_CS0                            72	/* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */
-#define SC_P_SPI3_CS1                            73	/* ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */
-#define SC_P_MCLK_IN1                            74	/* ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */
-#define SC_P_MCLK_IN0                            75	/* ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */
-#define SC_P_MCLK_OUT0                           76	/* ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */
-#define SC_P_UART1_TX                            77	/* ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */
-#define SC_P_UART1_RX                            78	/* ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
-#define SC_P_UART1_RTS_B                         79	/* ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
-#define SC_P_UART1_CTS_B                         80	/* ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK       81	/*  */
-#define SC_P_SAI0_TXD                            82	/* ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */
-#define SC_P_SAI0_TXC                            83	/* ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */
-#define SC_P_SAI0_RXD                            84	/* ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */
-#define SC_P_SAI0_TXFS                           85	/* ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */
-#define SC_P_SAI1_RXD                            86	/* ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */
-#define SC_P_SAI1_RXC                            87	/* ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */
-#define SC_P_SAI1_RXFS                           88	/* ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */
-#define SC_P_SPI2_CS0                            89	/* ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */
-#define SC_P_SPI2_SDO                            90	/* ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */
-#define SC_P_SPI2_SDI                            91	/* ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */
-#define SC_P_SPI2_SCK                            92	/* ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */
-#define SC_P_SPI0_SCK                            93	/* ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */
-#define SC_P_SPI0_SDI                            94	/* ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */
-#define SC_P_SPI0_SDO                            95	/* ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */
-#define SC_P_SPI0_CS1                            96	/* ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */
-#define SC_P_SPI0_CS0                            97	/* ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT       98	/*  */
-#define SC_P_ADC_IN1                             99	/* ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */
-#define SC_P_ADC_IN0                             100	/* ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */
-#define SC_P_ADC_IN3                             101	/* ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */
-#define SC_P_ADC_IN2                             102	/* ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */
-#define SC_P_ADC_IN5                             103	/* ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */
-#define SC_P_ADC_IN4                             104	/* ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */
-#define SC_P_FLEXCAN0_RX                         105	/* ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */
-#define SC_P_FLEXCAN0_TX                         106	/* ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */
-#define SC_P_FLEXCAN1_RX                         107	/* ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */
-#define SC_P_FLEXCAN1_TX                         108	/* ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
-#define SC_P_FLEXCAN2_RX                         109	/* ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
-#define SC_P_FLEXCAN2_TX                         110	/* ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
-#define SC_P_UART0_RX                            111	/* ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */
-#define SC_P_UART0_TX                            112	/* ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */
-#define SC_P_UART2_TX                            113	/* ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
-#define SC_P_UART2_RX                            114	/* ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH        115	/*  */
-#define SC_P_MIPI_DSI0_I2C0_SCL                  116	/* MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */
-#define SC_P_MIPI_DSI0_I2C0_SDA                  117	/* MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */
-#define SC_P_MIPI_DSI0_GPIO0_00                  118	/* MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */
-#define SC_P_MIPI_DSI0_GPIO0_01                  119	/* MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */
-#define SC_P_MIPI_DSI1_I2C0_SCL                  120	/* MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */
-#define SC_P_MIPI_DSI1_I2C0_SDA                  121	/* MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */
-#define SC_P_MIPI_DSI1_GPIO0_00                  122	/* MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */
-#define SC_P_MIPI_DSI1_GPIO0_01                  123	/* MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO   124	/*  */
-#define SC_P_JTAG_TRST_B                         125	/* SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
-#define SC_P_PMIC_I2C_SCL                        126	/* SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
-#define SC_P_PMIC_I2C_SDA                        127	/* SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
-#define SC_P_PMIC_INT_B                          128	/* SCU.DSC.PMIC_INT_B */
-#define SC_P_SCU_GPIO0_00                        129	/* SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
-#define SC_P_SCU_GPIO0_01                        130	/* SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
-#define SC_P_SCU_PMIC_STANDBY                    131	/* SCU.DSC.PMIC_STANDBY */
-#define SC_P_SCU_BOOT_MODE0                      132	/* SCU.DSC.BOOT_MODE0 */
-#define SC_P_SCU_BOOT_MODE1                      133	/* SCU.DSC.BOOT_MODE1 */
-#define SC_P_SCU_BOOT_MODE2                      134	/* SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */
-#define SC_P_SCU_BOOT_MODE3                      135	/* SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
-#define SC_P_CSI_D00                             136	/* CI_PI.D02, ADMA.SAI0.RXC */
-#define SC_P_CSI_D01                             137	/* CI_PI.D03, ADMA.SAI0.RXD */
-#define SC_P_CSI_D02                             138	/* CI_PI.D04, ADMA.SAI0.RXFS */
-#define SC_P_CSI_D03                             139	/* CI_PI.D05, ADMA.SAI2.RXC */
-#define SC_P_CSI_D04                             140	/* CI_PI.D06, ADMA.SAI2.RXD */
-#define SC_P_CSI_D05                             141	/* CI_PI.D07, ADMA.SAI2.RXFS */
-#define SC_P_CSI_D06                             142	/* CI_PI.D08, ADMA.SAI3.RXC */
-#define SC_P_CSI_D07                             143	/* CI_PI.D09, ADMA.SAI3.RXD */
-#define SC_P_CSI_HSYNC                           144	/* CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */
-#define SC_P_CSI_VSYNC                           145	/* CI_PI.VSYNC, CI_PI.D01 */
-#define SC_P_CSI_PCLK                            146	/* CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
-#define SC_P_CSI_MCLK                            147	/* CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
-#define SC_P_CSI_EN                              148	/* CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
-#define SC_P_CSI_RESET                           149	/* CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD       150	/*  */
-#define SC_P_MIPI_CSI0_MCLK_OUT                  151	/* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */
-#define SC_P_MIPI_CSI0_I2C0_SCL                  152	/* MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */
-#define SC_P_MIPI_CSI0_I2C0_SDA                  153	/* MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */
-#define SC_P_MIPI_CSI0_GPIO0_01                  154	/* MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */
-#define SC_P_MIPI_CSI0_GPIO0_00                  155	/* MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */
-#define SC_P_QSPI0A_DATA0                        156	/* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
-#define SC_P_QSPI0A_DATA1                        157	/* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
-#define SC_P_QSPI0A_DATA2                        158	/* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
-#define SC_P_QSPI0A_DATA3                        159	/* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
-#define SC_P_QSPI0A_DQS                          160	/* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
-#define SC_P_QSPI0A_SS0_B                        161	/* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
-#define SC_P_QSPI0A_SS1_B                        162	/* LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */
-#define SC_P_QSPI0A_SCLK                         163	/* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A        164	/*  */
-#define SC_P_QSPI0B_SCLK                         165	/* LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */
-#define SC_P_QSPI0B_DATA0                        166	/* LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */
-#define SC_P_QSPI0B_DATA1                        167	/* LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */
-#define SC_P_QSPI0B_DATA2                        168	/* LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */
-#define SC_P_QSPI0B_DATA3                        169	/* LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */
-#define SC_P_QSPI0B_DQS                          170	/* LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */
-#define SC_P_QSPI0B_SS0_B                        171	/* LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */
-#define SC_P_QSPI0B_SS1_B                        172	/* LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B        173	/*  */
+#define SC_P_PCIE_CTRL0_PERST_B                  0    /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
+#define SC_P_PCIE_CTRL0_CLKREQ_B                 1    /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
+#define SC_P_PCIE_CTRL0_WAKE_B                   2    /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP       3    /*  */
+#define SC_P_USB_SS3_TC0                         4    /* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */
+#define SC_P_USB_SS3_TC1                         5    /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
+#define SC_P_USB_SS3_TC2                         6    /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */
+#define SC_P_USB_SS3_TC3                         7    /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO            8    /*  */
+#define SC_P_EMMC0_CLK                           9    /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
+#define SC_P_EMMC0_CMD                           10   /* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
+#define SC_P_EMMC0_DATA0                         11   /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
+#define SC_P_EMMC0_DATA1                         12   /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
+#define SC_P_EMMC0_DATA2                         13   /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
+#define SC_P_EMMC0_DATA3                         14   /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0       15   /*  */
+#define SC_P_EMMC0_DATA4                         16   /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */
+#define SC_P_EMMC0_DATA5                         17   /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */
+#define SC_P_EMMC0_DATA6                         18   /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
+#define SC_P_EMMC0_DATA7                         19   /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */
+#define SC_P_EMMC0_STROBE                        20   /* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */
+#define SC_P_EMMC0_RESET_B                       21   /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1       22   /*  */
+#define SC_P_USDHC1_RESET_B                      23   /* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */
+#define SC_P_USDHC1_VSELECT                      24   /* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */
+#define SC_P_CTL_NAND_RE_P_N                     25   /*  */
+#define SC_P_USDHC1_WP                           26   /* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */
+#define SC_P_USDHC1_CD_B                         27   /* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */
+#define SC_P_CTL_NAND_DQS_P_N                    28   /*  */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP       29   /*  */
+#define SC_P_USDHC1_CLK                          30   /* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */
+#define SC_P_USDHC1_CMD                          31   /* CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */
+#define SC_P_USDHC1_DATA0                        32   /* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */
+#define SC_P_USDHC1_DATA1                        33   /* CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */
+#define SC_P_USDHC1_DATA2                        34   /* CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */
+#define SC_P_USDHC1_DATA3                        35   /* CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3         36   /*  */
+#define SC_P_ENET0_RGMII_TXC                     37   /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */
+#define SC_P_ENET0_RGMII_TX_CTL                  38   /* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */
+#define SC_P_ENET0_RGMII_TXD0                    39   /* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */
+#define SC_P_ENET0_RGMII_TXD1                    40   /* CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */
+#define SC_P_ENET0_RGMII_TXD2                    41   /* CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */
+#define SC_P_ENET0_RGMII_TXD3                    42   /* CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0   43   /*  */
+#define SC_P_ENET0_RGMII_RXC                     44   /* CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
+#define SC_P_ENET0_RGMII_RX_CTL                  45   /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
+#define SC_P_ENET0_RGMII_RXD0                    46   /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
+#define SC_P_ENET0_RGMII_RXD1                    47   /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
+#define SC_P_ENET0_RGMII_RXD2                    48   /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
+#define SC_P_ENET0_RGMII_RXD3                    49   /* CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1   50   /*  */
+#define SC_P_ENET0_REFCLK_125M_25M               51   /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */
+#define SC_P_ENET0_MDIO                          52   /* CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */
+#define SC_P_ENET0_MDC                           53   /* CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT        54   /*  */
+#define SC_P_ESAI0_FSR                           55   /* ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */
+#define SC_P_ESAI0_FST                           56   /* ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */
+#define SC_P_ESAI0_SCKR                          57   /* ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
+#define SC_P_ESAI0_SCKT                          58   /* ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */
+#define SC_P_ESAI0_TX0                           59   /* ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */
+#define SC_P_ESAI0_TX1                           60   /* ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */
+#define SC_P_ESAI0_TX2_RX3                       61   /* ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */
+#define SC_P_ESAI0_TX3_RX2                       62   /* ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */
+#define SC_P_ESAI0_TX4_RX1                       63   /* ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */
+#define SC_P_ESAI0_TX5_RX0                       64   /* ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */
+#define SC_P_SPDIF0_RX                           65   /* ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */
+#define SC_P_SPDIF0_TX                           66   /* ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */
+#define SC_P_SPDIF0_EXT_CLK                      67   /* ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB       68   /*  */
+#define SC_P_SPI3_SCK                            69   /* ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */
+#define SC_P_SPI3_SDO                            70   /* ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */
+#define SC_P_SPI3_SDI                            71   /* ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */
+#define SC_P_SPI3_CS0                            72   /* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */
+#define SC_P_SPI3_CS1                            73   /* ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */
+#define SC_P_MCLK_IN1                            74   /* ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */
+#define SC_P_MCLK_IN0                            75   /* ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */
+#define SC_P_MCLK_OUT0                           76   /* ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */
+#define SC_P_UART1_TX                            77   /* ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */
+#define SC_P_UART1_RX                            78   /* ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
+#define SC_P_UART1_RTS_B                         79   /* ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
+#define SC_P_UART1_CTS_B                         80   /* ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK       81   /*  */
+#define SC_P_SAI0_TXD                            82   /* ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */
+#define SC_P_SAI0_TXC                            83   /* ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */
+#define SC_P_SAI0_RXD                            84   /* ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */
+#define SC_P_SAI0_TXFS                           85   /* ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */
+#define SC_P_SAI1_RXD                            86   /* ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */
+#define SC_P_SAI1_RXC                            87   /* ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */
+#define SC_P_SAI1_RXFS                           88   /* ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */
+#define SC_P_SPI2_CS0                            89   /* ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */
+#define SC_P_SPI2_SDO                            90   /* ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */
+#define SC_P_SPI2_SDI                            91   /* ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */
+#define SC_P_SPI2_SCK                            92   /* ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */
+#define SC_P_SPI0_SCK                            93   /* ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */
+#define SC_P_SPI0_SDI                            94   /* ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */
+#define SC_P_SPI0_SDO                            95   /* ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */
+#define SC_P_SPI0_CS1                            96   /* ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */
+#define SC_P_SPI0_CS0                            97   /* ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT       98   /*  */
+#define SC_P_ADC_IN1                             99   /* ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */
+#define SC_P_ADC_IN0                             100  /* ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */
+#define SC_P_ADC_IN3                             101  /* ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */
+#define SC_P_ADC_IN2                             102  /* ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */
+#define SC_P_ADC_IN5                             103  /* ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */
+#define SC_P_ADC_IN4                             104  /* ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */
+#define SC_P_FLEXCAN0_RX                         105  /* ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */
+#define SC_P_FLEXCAN0_TX                         106  /* ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */
+#define SC_P_FLEXCAN1_RX                         107  /* ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */
+#define SC_P_FLEXCAN1_TX                         108  /* ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
+#define SC_P_FLEXCAN2_RX                         109  /* ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
+#define SC_P_FLEXCAN2_TX                         110  /* ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
+#define SC_P_UART0_RX                            111  /* ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */
+#define SC_P_UART0_TX                            112  /* ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */
+#define SC_P_UART2_TX                            113  /* ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
+#define SC_P_UART2_RX                            114  /* ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH        115  /*  */
+#define SC_P_MIPI_DSI0_I2C0_SCL                  116  /* MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */
+#define SC_P_MIPI_DSI0_I2C0_SDA                  117  /* MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */
+#define SC_P_MIPI_DSI0_GPIO0_00                  118  /* MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_DSI0_GPIO0_01                  119  /* MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_DSI1_I2C0_SCL                  120  /* MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */
+#define SC_P_MIPI_DSI1_I2C0_SDA                  121  /* MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */
+#define SC_P_MIPI_DSI1_GPIO0_00                  122  /* MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */
+#define SC_P_MIPI_DSI1_GPIO0_01                  123  /* MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO   124  /*  */
+#define SC_P_JTAG_TRST_B                         125  /* SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SCL                        126  /* SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
+#define SC_P_PMIC_I2C_SDA                        127  /* SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
+#define SC_P_PMIC_INT_B                          128  /* SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00                        129  /* SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
+#define SC_P_SCU_GPIO0_01                        130  /* SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
+#define SC_P_SCU_PMIC_STANDBY                    131  /* SCU.DSC.PMIC_STANDBY */
+#define SC_P_SCU_BOOT_MODE0                      132  /* SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE1                      133  /* SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE2                      134  /* SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */
+#define SC_P_SCU_BOOT_MODE3                      135  /* SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
+#define SC_P_CSI_D00                             136  /* CI_PI.D02, ADMA.SAI0.RXC */
+#define SC_P_CSI_D01                             137  /* CI_PI.D03, ADMA.SAI0.RXD */
+#define SC_P_CSI_D02                             138  /* CI_PI.D04, ADMA.SAI0.RXFS */
+#define SC_P_CSI_D03                             139  /* CI_PI.D05, ADMA.SAI2.RXC */
+#define SC_P_CSI_D04                             140  /* CI_PI.D06, ADMA.SAI2.RXD */
+#define SC_P_CSI_D05                             141  /* CI_PI.D07, ADMA.SAI2.RXFS */
+#define SC_P_CSI_D06                             142  /* CI_PI.D08, ADMA.SAI3.RXC */
+#define SC_P_CSI_D07                             143  /* CI_PI.D09, ADMA.SAI3.RXD */
+#define SC_P_CSI_HSYNC                           144  /* CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */
+#define SC_P_CSI_VSYNC                           145  /* CI_PI.VSYNC, CI_PI.D01 */
+#define SC_P_CSI_PCLK                            146  /* CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
+#define SC_P_CSI_MCLK                            147  /* CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
+#define SC_P_CSI_EN                              148  /* CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
+#define SC_P_CSI_RESET                           149  /* CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD       150  /*  */
+#define SC_P_MIPI_CSI0_MCLK_OUT                  151  /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */
+#define SC_P_MIPI_CSI0_I2C0_SCL                  152  /* MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */
+#define SC_P_MIPI_CSI0_I2C0_SDA                  153  /* MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */
+#define SC_P_MIPI_CSI0_GPIO0_01                  154  /* MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */
+#define SC_P_MIPI_CSI0_GPIO0_00                  155  /* MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */
+#define SC_P_QSPI0A_DATA0                        156  /* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
+#define SC_P_QSPI0A_DATA1                        157  /* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
+#define SC_P_QSPI0A_DATA2                        158  /* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
+#define SC_P_QSPI0A_DATA3                        159  /* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
+#define SC_P_QSPI0A_DQS                          160  /* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
+#define SC_P_QSPI0A_SS0_B                        161  /* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
+#define SC_P_QSPI0A_SS1_B                        162  /* LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */
+#define SC_P_QSPI0A_SCLK                         163  /* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A        164  /*  */
+#define SC_P_QSPI0B_SCLK                         165  /* LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */
+#define SC_P_QSPI0B_DATA0                        166  /* LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */
+#define SC_P_QSPI0B_DATA1                        167  /* LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */
+#define SC_P_QSPI0B_DATA2                        168  /* LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */
+#define SC_P_QSPI0B_DATA3                        169  /* LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */
+#define SC_P_QSPI0B_DQS                          170  /* LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */
+#define SC_P_QSPI0B_SS0_B                        171  /* LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */
+#define SC_P_QSPI0B_SS1_B                        172  /* LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B        173  /*  */
 /*@}*/
 
-#endif				/* SC_PADS_H */
+#endif /* SC_PADS_H */
+
diff --git a/plat/imx/common/include/sci/sci_ipc.h b/plat/imx/common/include/sci/sci_ipc.h
index c169a79..7cb1092 100644
--- a/plat/imx/common/include/sci/sci_ipc.h
+++ b/plat/imx/common/include/sci/sci_ipc.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -60,8 +61,9 @@
  *
  * This function will block if the outgoing buffer is full.
  */
-void sc_ipc_write(sc_ipc_t ipc, void *data);
+void sc_ipc_write(sc_ipc_t ipc, const void *data);
 
 sc_ipc_t ipc_handle;
 
-#endif				/* SC_IPC_H */
+#endif /* SC_IPC_H */
+
diff --git a/plat/imx/common/include/sci/sci_rpc.h b/plat/imx/common/include/sci/sci_rpc.h
index 052f361..f218def 100644
--- a/plat/imx/common/include/sci/sci_rpc.h
+++ b/plat/imx/common/include/sci/sci_rpc.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,17 +24,17 @@
 
 #define SC_RPC_MAX_MSG          8U
 
-#define RPC_VER(MSG)            ((MSG)->version)
-#define RPC_SIZE(MSG)           ((MSG)->size)
-#define RPC_SVC(MSG)            ((MSG)->svc)
-#define RPC_FUNC(MSG)           ((MSG)->func)
-#define RPC_R8(MSG)             ((MSG)->func)
-#define RPC_I32(MSG, IDX)       ((MSG)->DATA.i32[(IDX) / 4U])
-#define RPC_I16(MSG, IDX)       ((MSG)->DATA.i16[(IDX) / 2U])
-#define RPC_I8(MSG, IDX)        ((MSG)->DATA.i8[(IDX)])
-#define RPC_U32(MSG, IDX)       ((MSG)->DATA.u32[(IDX) / 4U])
-#define RPC_U16(MSG, IDX)       ((MSG)->DATA.u16[(IDX) / 2U])
-#define RPC_U8(MSG, IDX)        ((MSG)->DATA.u8[(IDX)])
+#define RPC_VER(MESG)           ((MESG)->version)
+#define RPC_SIZE(MESG)          ((MESG)->size)
+#define RPC_SVC(MESG)           ((MESG)->svc)
+#define RPC_FUNC(MESG)          ((MESG)->func)
+#define RPC_R8(MESG)            ((MESG)->func)
+#define RPC_I32(MESG, IDX)      ((MESG)->DATA.i32[(IDX) / 4U])
+#define RPC_I16(MESG, IDX)      ((MESG)->DATA.i16[(IDX) / 2U])
+#define RPC_I8(MESG, IDX)       ((MESG)->DATA.i8[(IDX)])
+#define RPC_U32(MESG, IDX)      ((MESG)->DATA.u32[(IDX) / 4U])
+#define RPC_U16(MESG, IDX)      ((MESG)->DATA.u16[(IDX) / 2U])
+#define RPC_U8(MESG, IDX)       ((MESG)->DATA.u8[(IDX)])
 
 #define SC_RPC_SVC_UNKNOWN      0U
 #define SC_RPC_SVC_RETURN       1U
@@ -43,7 +44,8 @@
 #define SC_RPC_SVC_PAD          6U
 #define SC_RPC_SVC_MISC         7U
 #define SC_RPC_SVC_IRQ          8U
-#define SC_RPC_SVC_ABORT        9U
+#define SC_RPC_SVC_SECO         9U
+#define SC_RPC_SVC_ABORT        10U
 
 #define SC_RPC_ASYNC_STATE_RD_START      0U
 #define SC_RPC_ASYNC_STATE_RD_ACTIVE     1U
@@ -53,13 +55,39 @@
 #define SC_RPC_ASYNC_STATE_WR_DONE       5U
 
 #define SC_RPC_MU_GIR_SVC       0x1U
+#define SC_RPC_MU_GIR_WAKE      0x2U
+#define SC_RPC_MU_GIR_BOOT      0x4U
 #define SC_RPC_MU_GIR_DBG       0x8U
 
+#define I8(X)       ((int8_t) (X))
+#define I16(X)      ((int16_t) (X))
+#define I32(X)      ((int32_t) (X))
+#define I64(X)      ((int64_t) (X))
+#define U8(X)       ((uint8_t) (X))
+#define U16(X)      ((uint16_t) (X))
+#define U32(X)      ((uint32_t) (X))
+#define U64(X)      ((uint64_t) (X))
+
+#define PTR_I8(X)   ((int8_t *) (X))
+#define PTR_I16(X)  ((int16_t *) (X))
+#define PTR_I32(X)  ((int32_t *) (X))
+#define PTR_I64(X)  ((int64_t *) (X))
+#define PTR_U8(X)   ((uint8_t *) (X))
+#define PTR_U16(X)  ((uint16_t *) (X))
+#define PTR_U32(X)  ((uint32_t *) (X))
+#define PTR_U64(X)  ((uint64_t *) (X))
+
+#define U2B(X)      (((X) != 0U) ? SC_TRUE : SC_FALSE)
+#define U2B32(X)    (((X) != 0UL) ? SC_TRUE : SC_FALSE)
+#define B2U8(X)     (((X) != SC_FALSE) ? U8(0x01U) : U8(0x00U))
+#define B2U16(X)    (((X) != SC_FALSE) ? U16(0x01U) : U16(0x00U))
+#define B2U32(X)    (((X) != SC_FALSE) ? U32(0x01U) : U32(0x00U))
+
 /* Types */
 
 typedef uint8_t sc_rpc_svc_t;
 
-typedef struct sc_rpc_msg_s {
+typedef struct {
 	uint8_t version;
 	uint8_t size;
 	uint8_t svc;
@@ -76,7 +104,7 @@
 
 typedef uint8_t sc_rpc_async_state_t;
 
-typedef struct sc_rpc_async_msg_s {
+typedef struct {
 	sc_rpc_async_state_t state;
 	uint8_t wordIdx;
 	sc_rpc_msg_t msg;
@@ -96,7 +124,7 @@
  * If \a no_resp is SC_FALSE then this function waits for a response
  * and returns the result in \a msg.
  */
-void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp);
+void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, sc_bool_t no_resp);
 
 /*!
  * This is an internal function to dispath an RPC call that has
@@ -124,4 +152,5 @@
  */
 void sc_rpc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
 
-#endif				/* SC_RPC_H */
+#endif /* SC_RPC_H */
+
diff --git a/plat/imx/common/include/sci/sci_types.h b/plat/imx/common/include/sci/sci_types.h
index 3ee5276..96501d9 100644
--- a/plat/imx/common/include/sci/sci_types.h
+++ b/plat/imx/common/include/sci/sci_types.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,6 +14,7 @@
 
 /* Includes */
 
+#include <stdbool.h>
 #include <sci/sci_scfw.h>
 
 /* Defines */
@@ -21,144 +23,156 @@
  * @name Defines for common frequencies
  */
 /*@{*/
-#define SC_32KHZ            32768U	/* 32KHz */
-#define SC_10MHZ         10000000U	/* 10MHz */
-#define SC_20MHZ         20000000U	/* 20MHz */
-#define SC_25MHZ         25000000U	/* 25MHz */
-#define SC_27MHZ         27000000U	/* 27MHz */
-#define SC_40MHZ         40000000U	/* 40MHz */
-#define SC_45MHZ         45000000U	/* 45MHz */
-#define SC_50MHZ         50000000U	/* 50MHz */
-#define SC_60MHZ         60000000U	/* 60MHz */
-#define SC_66MHZ         66666666U	/* 66MHz */
-#define SC_74MHZ         74250000U	/* 74.25MHz */
-#define SC_80MHZ         80000000U	/* 80MHz */
-#define SC_83MHZ         83333333U	/* 83MHz */
-#define SC_84MHZ         84375000U	/* 84.37MHz */
-#define SC_100MHZ       100000000U	/* 100MHz */
-#define SC_125MHZ       125000000U	/* 125MHz */
-#define SC_133MHZ       133333333U	/* 133MHz */
-#define SC_135MHZ       135000000U	/* 135MHz */
-#define SC_150MHZ       150000000U	/* 150MHz */
-#define SC_160MHZ       160000000U	/* 160MHz */
-#define SC_166MHZ       166666666U	/* 166MHz */
-#define SC_175MHZ       175000000U	/* 175MHz */
-#define SC_180MHZ       180000000U	/* 180MHz */
-#define SC_200MHZ       200000000U	/* 200MHz */
-#define SC_250MHZ       250000000U	/* 250MHz */
-#define SC_266MHZ       266666666U	/* 266MHz */
-#define SC_300MHZ       300000000U	/* 300MHz */
-#define SC_312MHZ       312500000U	/* 312.5MHZ */
-#define SC_320MHZ       320000000U	/* 320MHz */
-#define SC_325MHZ       325000000U	/* 325MHz */
-#define SC_333MHZ       333333333U	/* 333MHz */
-#define SC_350MHZ       350000000U	/* 350MHz */
-#define SC_372MHZ       372000000U	/* 372MHz */
-#define SC_375MHZ       375000000U	/* 375MHz */
-#define SC_400MHZ       400000000U	/* 400MHz */
-#define SC_500MHZ       500000000U	/* 500MHz */
-#define SC_594MHZ       594000000U	/* 594MHz */
-#define SC_625MHZ       625000000U	/* 625MHz */
-#define SC_640MHZ       640000000U	/* 640MHz */
-#define SC_650MHZ       650000000U	/* 650MHz */
-#define SC_667MHZ       666666667U	/* 667MHz */
-#define SC_675MHZ       675000000U	/* 675MHz */
-#define SC_700MHZ       700000000U	/* 700MHz */
-#define SC_720MHZ       720000000U	/* 720MHz */
-#define SC_750MHZ       750000000U	/* 750MHz */
-#define SC_800MHZ       800000000U	/* 800MHz */
-#define SC_850MHZ       850000000U	/* 850MHz */
-#define SC_900MHZ       900000000U	/* 900MHz */
-#define SC_1000MHZ     1000000000U	/* 1GHz */
-#define SC_1056MHZ     1056000000U	/* 1.056GHz */
-#define SC_1188MHZ     1188000000U	/* 1.188GHz */
-#define SC_1260MHZ     1260000000U	/* 1.26GHz */
-#define SC_1280MHZ     1280000000U	/* 1.28GHz */
-#define SC_1300MHZ     1300000000U	/* 1.3GHz */
-#define SC_1400MHZ     1400000000U	/* 1.4GHz */
-#define SC_1500MHZ     1500000000U	/* 1.5GHz */
-#define SC_1600MHZ     1600000000U	/* 1.6GHz */
-#define SC_1800MHZ     1800000000U	/* 1.8GHz */
-#define SC_2000MHZ     2000000000U	/* 2.0GHz */
-#define SC_2112MHZ     2112000000U	/* 2.12GHz */
+#define SC_32KHZ            32768U   /* 32KHz */
+#define SC_10MHZ         10000000U   /* 10MHz */
+#define SC_20MHZ         20000000U   /* 20MHz */
+#define SC_25MHZ         25000000U   /* 25MHz */
+#define SC_27MHZ         27000000U   /* 27MHz */
+#define SC_40MHZ         40000000U   /* 40MHz */
+#define SC_45MHZ         45000000U   /* 45MHz */
+#define SC_50MHZ         50000000U   /* 50MHz */
+#define SC_60MHZ         60000000U   /* 60MHz */
+#define SC_66MHZ         66666666U   /* 66MHz */
+#define SC_74MHZ         74250000U   /* 74.25MHz */
+#define SC_80MHZ         80000000U   /* 80MHz */
+#define SC_83MHZ         83333333U   /* 83MHz */
+#define SC_84MHZ         84375000U   /* 84.37MHz */
+#define SC_100MHZ       100000000U   /* 100MHz */
+#define SC_125MHZ       125000000U   /* 125MHz */
+#define SC_133MHZ       133333333U   /* 133MHz */
+#define SC_135MHZ       135000000U   /* 135MHz */
+#define SC_150MHZ       150000000U   /* 150MHz */
+#define SC_160MHZ       160000000U   /* 160MHz */
+#define SC_166MHZ       166666666U   /* 166MHz */
+#define SC_175MHZ       175000000U   /* 175MHz */
+#define SC_180MHZ       180000000U   /* 180MHz */
+#define SC_200MHZ       200000000U   /* 200MHz */
+#define SC_250MHZ       250000000U   /* 250MHz */
+#define SC_266MHZ       266666666U   /* 266MHz */
+#define SC_300MHZ       300000000U   /* 300MHz */
+#define SC_312MHZ       312500000U   /* 312.5MHZ */
+#define SC_320MHZ       320000000U   /* 320MHz */
+#define SC_325MHZ       325000000U   /* 325MHz */
+#define SC_333MHZ       333333333U   /* 333MHz */
+#define SC_350MHZ       350000000U   /* 350MHz */
+#define SC_372MHZ       372000000U   /* 372MHz */
+#define SC_375MHZ       375000000U   /* 375MHz */
+#define SC_400MHZ       400000000U   /* 400MHz */
+#define SC_500MHZ       500000000U   /* 500MHz */
+#define SC_594MHZ       594000000U   /* 594MHz */
+#define SC_625MHZ       625000000U   /* 625MHz */
+#define SC_640MHZ       640000000U   /* 640MHz */
+#define SC_648MHZ       648000000U   /* 648MHz */
+#define SC_650MHZ       650000000U   /* 650MHz */
+#define SC_667MHZ       666666667U   /* 667MHz */
+#define SC_675MHZ       675000000U   /* 675MHz */
+#define SC_700MHZ       700000000U   /* 700MHz */
+#define SC_720MHZ       720000000U   /* 720MHz */
+#define SC_750MHZ       750000000U   /* 750MHz */
+#define SC_753MHZ       753000000U   /* 753MHz */
+#define SC_793MHZ       793000000U   /* 793MHz */
+#define SC_800MHZ       800000000U   /* 800MHz */
+#define SC_850MHZ       850000000U   /* 850MHz */
+#define SC_858MHZ       858000000U   /* 858MHz */
+#define SC_900MHZ       900000000U   /* 900MHz */
+#define SC_953MHZ       953000000U   /* 953MHz */
+#define SC_963MHZ       963000000U   /* 963MHz */
+#define SC_1000MHZ     1000000000U   /* 1GHz */
+#define SC_1060MHZ     1060000000U   /* 1.06GHz */
+#define SC_1068MHZ     1068000000U   /* 1.068GHz */
+#define SC_1121MHZ     1121000000U   /* 1.121GHz */
+#define SC_1173MHZ     1173000000U   /* 1.173GHz */
+#define SC_1188MHZ     1188000000U   /* 1.188GHz */
+#define SC_1260MHZ     1260000000U   /* 1.26GHz */
+#define SC_1278MHZ     1278000000U   /* 1.278GHz */
+#define SC_1280MHZ     1280000000U   /* 1.28GHz */
+#define SC_1300MHZ     1300000000U   /* 1.3GHz */
+#define SC_1313MHZ     1313000000U   /* 1.313GHz */
+#define SC_1345MHZ     1345000000U   /* 1.345GHz */
+#define SC_1400MHZ     1400000000U   /* 1.4GHz */
+#define SC_1500MHZ     1500000000U   /* 1.5GHz */
+#define SC_1600MHZ     1600000000U   /* 1.6GHz */
+#define SC_1800MHZ     1800000000U   /* 1.8GHz */
+#define SC_2000MHZ     2000000000U   /* 2.0GHz */
+#define SC_2112MHZ     2112000000U   /* 2.12GHz */
 /*@}*/
 
 /*!
  * @name Defines for 24M related frequencies
  */
 /*@{*/
-#define SC_8MHZ           8000000U	/* 8MHz */
-#define SC_12MHZ         12000000U	/* 12MHz */
-#define SC_19MHZ         19800000U	/* 19.8MHz */
-#define SC_24MHZ         24000000U	/* 24MHz */
-#define SC_48MHZ         48000000U	/* 48MHz */
-#define SC_120MHZ       120000000U	/* 120MHz */
-#define SC_132MHZ       132000000U	/* 132MHz */
-#define SC_144MHZ       144000000U	/* 144MHz */
-#define SC_192MHZ       192000000U	/* 192MHz */
-#define SC_211MHZ       211200000U	/* 211.2MHz */
-#define SC_240MHZ       240000000U	/* 240MHz */
-#define SC_264MHZ       264000000U	/* 264MHz */
-#define SC_352MHZ       352000000U	/* 352MHz */
-#define SC_360MHZ       360000000U	/* 360MHz */
-#define SC_384MHZ       384000000U	/* 384MHz */
-#define SC_396MHZ       396000000U	/* 396MHz */
-#define SC_432MHZ       432000000U	/* 432MHz */
-#define SC_480MHZ       480000000U	/* 480MHz */
-#define SC_600MHZ       600000000U	/* 600MHz */
-#define SC_744MHZ       744000000U	/* 744MHz */
-#define SC_792MHZ       792000000U	/* 792MHz */
-#define SC_864MHZ       864000000U	/* 864MHz */
-#define SC_960MHZ       960000000U	/* 960MHz */
-#define SC_1056MHZ     1056000000U	/* 1056MHz */
-#define SC_1200MHZ     1200000000U	/* 1.2GHz */
-#define SC_1464MHZ     1464000000U	/* 1.464GHz */
-#define SC_2400MHZ     2400000000U	/* 2.4GHz */
+#define SC_8MHZ           8000000U   /* 8MHz */
+#define SC_12MHZ         12000000U   /* 12MHz */
+#define SC_19MHZ         19800000U   /* 19.8MHz */
+#define SC_24MHZ         24000000U   /* 24MHz */
+#define SC_48MHZ         48000000U   /* 48MHz */
+#define SC_120MHZ       120000000U   /* 120MHz */
+#define SC_132MHZ       132000000U   /* 132MHz */
+#define SC_144MHZ       144000000U   /* 144MHz */
+#define SC_192MHZ       192000000U   /* 192MHz */
+#define SC_211MHZ       211200000U   /* 211.2MHz */
+#define SC_240MHZ       240000000U   /* 240MHz */
+#define SC_264MHZ       264000000U   /* 264MHz */
+#define SC_352MHZ       352000000U   /* 352MHz */
+#define SC_360MHZ       360000000U   /* 360MHz */
+#define SC_384MHZ       384000000U   /* 384MHz */
+#define SC_396MHZ       396000000U   /* 396MHz */
+#define SC_432MHZ       432000000U   /* 432MHz */
+#define SC_480MHZ       480000000U   /* 480MHz */
+#define SC_600MHZ       600000000U   /* 600MHz */
+#define SC_744MHZ       744000000U   /* 744MHz */
+#define SC_792MHZ       792000000U   /* 792MHz */
+#define SC_864MHZ       864000000U   /* 864MHz */
+#define SC_960MHZ       960000000U   /* 960MHz */
+#define SC_1056MHZ     1056000000U   /* 1056MHz */
+#define SC_1104MHZ     1104000000U   /* 1104MHz */
+#define SC_1200MHZ     1200000000U   /* 1.2GHz */
+#define SC_1464MHZ     1464000000U   /* 1.464GHz */
+#define SC_2400MHZ     2400000000U   /* 2.4GHz */
 /*@}*/
 
 /*!
  * @name Defines for A/V related frequencies
  */
 /*@{*/
-#define SC_62MHZ         62937500U	/* 62.9375MHz */
-#define SC_755MHZ       755250000U	/* 755.25MHz */
+#define SC_62MHZ         62937500U   /* 62.9375MHz */
+#define SC_755MHZ       755250000U   /* 755.25MHz */
 /*@}*/
 
 /*!
  * @name Defines for type widths
  */
 /*@{*/
-#define SC_FADDR_W      36U	/* Width of sc_faddr_t */
-#define SC_BOOL_W       1U	/* Width of sc_bool_t */
-#define SC_ERR_W        4U	/* Width of sc_err_t */
-#define SC_RSRC_W       10U	/* Width of sc_rsrc_t */
-#define SC_CTRL_W       6U	/* Width of sc_ctrl_t */
+#define SC_BOOL_W       1U           /* Width of sc_bool_t */
+#define SC_ERR_W        4U           /* Width of sc_err_t */
+#define SC_RSRC_W       10U          /* Width of sc_rsrc_t */
+#define SC_CTRL_W       6U           /* Width of sc_ctrl_t */
 /*@}*/
 
 /*!
  * @name Defines for sc_bool_t
  */
 /*@{*/
-#define SC_FALSE        ((sc_bool_t) 0U)	/* True */
-#define SC_TRUE         ((sc_bool_t) 1U)	/* False */
+#define SC_FALSE        ((sc_bool_t) 0U)    /* False */
+#define SC_TRUE         ((sc_bool_t) 1U)    /* True */
 /*@}*/
 
 /*!
  * @name Defines for sc_err_t.
  */
 /*@{*/
-#define SC_ERR_NONE         0U	/* Success */
-#define SC_ERR_VERSION      1U	/* Incompatible API version */
-#define SC_ERR_CONFIG       2U	/* Configuration error */
-#define SC_ERR_PARM         3U	/* Bad parameter */
-#define SC_ERR_NOACCESS     4U	/* Permission error (no access) */
-#define SC_ERR_LOCKED       5U	/* Permission error (locked) */
-#define SC_ERR_UNAVAILABLE  6U	/* Unavailable (out of resources) */
-#define SC_ERR_NOTFOUND     7U	/* Not found */
-#define SC_ERR_NOPOWER      8U	/* No power */
-#define SC_ERR_IPC          9U	/* Generic IPC error */
-#define SC_ERR_BUSY         10U	/* Resource is currently busy/active */
-#define SC_ERR_FAIL         11U	/* General I/O failure */
+#define SC_ERR_NONE         0U      /* Success */
+#define SC_ERR_VERSION      1U      /* Incompatible API version */
+#define SC_ERR_CONFIG       2U      /* Configuration error */
+#define SC_ERR_PARM         3U      /* Bad parameter */
+#define SC_ERR_NOACCESS     4U      /* Permission error (no access) */
+#define SC_ERR_LOCKED       5U      /* Permission error (locked) */
+#define SC_ERR_UNAVAILABLE  6U      /* Unavailable (out of resources) */
+#define SC_ERR_NOTFOUND     7U      /* Not found */
+#define SC_ERR_NOPOWER      8U      /* No power */
+#define SC_ERR_IPC          9U      /* Generic IPC error */
+#define SC_ERR_BUSY         10U     /* Resource is currently busy/active */
+#define SC_ERR_FAIL         11U     /* General I/O failure */
 #define SC_ERR_LAST         12U
 /*@}*/
 
@@ -489,7 +503,7 @@
 #define SC_R_SAI_2                320U
 #define SC_R_IRQSTR_SCU2          321U
 #define SC_R_IRQSTR_DSP           322U
-#define SC_R_UNUSED5              323U
+#define SC_R_ELCDIF_PLL           323U
 #define SC_R_OCRAM                324U
 #define SC_R_AUDIO_PLL_0          325U
 #define SC_R_PI_0                 326U
@@ -707,8 +721,14 @@
 #define SC_R_VPU_MU_3             538U
 #define SC_R_VPU_ENC_1            539U
 #define SC_R_VPU                  540U
-#define SC_R_LAST                 541U
-#define SC_R_ALL                  ((sc_rsrc_t) UINT16_MAX)	/* All resources */
+#define SC_R_DMA_5_CH0            541U
+#define SC_R_DMA_5_CH1            542U
+#define SC_R_DMA_5_CH2            543U
+#define SC_R_DMA_5_CH3            544U
+#define SC_R_ATTESTATION          545U
+#define SC_R_PERF                 546U
+#define SC_R_LAST                 547U
+#define SC_R_ALL                  ((sc_rsrc_t) UINT16_MAX)  /* All resources */
 /*@}*/
 
 /* NOTE - please add by replacing some of the UNUSED from above! */
@@ -762,9 +782,19 @@
 #define SC_C_RST0                       43U
 #define SC_C_RST1                       44U
 #define SC_C_SEL0                       45U
-#define SC_C_LAST                       46U
+#define SC_C_CALIB0                     46U
+#define SC_C_CALIB1                     47U
+#define SC_C_CALIB2                     48U
+#define SC_C_IPG_DEBUG                  49U
+#define SC_C_IPG_DOZE                   50U
+#define SC_C_IPG_WAIT                   51U
+#define SC_C_IPG_STOP                   52U
+#define SC_C_IPG_STOP_MODE              53U
+#define SC_C_IPG_STOP_ACK               54U
+#define SC_C_SYNC_CTRL                  55U
+#define SC_C_LAST                       56U
 
-#define SC_P_ALL        ((sc_pad_t) UINT16_MAX)	/* All pads */
+#define SC_P_ALL        ((sc_pad_t) UINT16_MAX)   /* All pads */
 
 /* Types */
 
@@ -793,7 +823,7 @@
 /*!
  * This type is used to indicate a control.
  */
-typedef uint8_t sc_ctrl_t;
+typedef uint32_t sc_ctrl_t;
 
 /*!
  * This type is used to indicate a pad. Valid values are SoC specific.
@@ -805,45 +835,46 @@
 /* Extra documentation of standard types */
 
 #ifdef DOXYGEN
-    /*!
-     * Type used to declare an 8-bit integer.
-     */
+/*!
+ * Type used to declare an 8-bit integer.
+ */
 typedef __INT8_TYPE__ int8_t;
 
-    /*!
-     * Type used to declare a 16-bit integer.
-     */
+/*!
+ * Type used to declare a 16-bit integer.
+ */
 typedef __INT16_TYPE__ int16_t;
 
-    /*!
-     * Type used to declare a 32-bit integer.
-     */
+/*!
+ * Type used to declare a 32-bit integer.
+ */
 typedef __INT32_TYPE__ int32_t;
 
-    /*!
-     * Type used to declare a 64-bit integer.
-     */
+/*!
+ * Type used to declare a 64-bit integer.
+ */
 typedef __INT64_TYPE__ int64_t;
 
-    /*!
-     * Type used to declare an 8-bit unsigned integer.
-     */
+/*!
+ * Type used to declare an 8-bit unsigned integer.
+ */
 typedef __UINT8_TYPE__ uint8_t;
 
-    /*!
-     * Type used to declare a 16-bit unsigned integer.
-     */
+/*!
+ * Type used to declare a 16-bit unsigned integer.
+ */
 typedef __UINT16_TYPE__ uint16_t;
 
-    /*!
-     * Type used to declare a 32-bit unsigned integer.
-     */
+/*!
+ * Type used to declare a 32-bit unsigned integer.
+ */
 typedef __UINT32_TYPE__ uint32_t;
 
-    /*!
-     * Type used to declare a 64-bit unsigned integer.
-     */
+/*!
+ * Type used to declare a 64-bit unsigned integer.
+ */
 typedef __UINT64_TYPE__ uint64_t;
 #endif
 
-#endif				/* SC_TYPES_H */
+#endif /* SC_TYPES_H */
+
diff --git a/plat/imx/common/include/sci/svc/irq/sci_irq_api.h b/plat/imx/common/include/sci/svc/irq/sci_irq_api.h
new file mode 100644
index 0000000..49c75e0
--- /dev/null
+++ b/plat/imx/common/include/sci/svc/irq/sci_irq_api.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*!
+ * Header file containing the public API for the System Controller (SC)
+ * Interrupt (IRQ) function.
+ *
+ * @addtogroup IRQ_SVC (SVC) Interrupt Service
+ *
+ * Module for the Interrupt (IRQ) service.
+ *
+ * @{
+ */
+
+#ifndef SC_IRQ_API_H
+#define SC_IRQ_API_H
+
+/* Includes */
+
+#include <sci/sci_types.h>
+
+/* Defines */
+
+#define SC_IRQ_NUM_GROUP        7U   /* Number of groups */
+
+/*!
+ * @name Defines for sc_irq_group_t
+ */
+/*@{*/
+#define SC_IRQ_GROUP_TEMP       0U   /* Temp interrupts */
+#define SC_IRQ_GROUP_WDOG       1U   /* Watchdog interrupts */
+#define SC_IRQ_GROUP_RTC        2U   /* RTC interrupts */
+#define SC_IRQ_GROUP_WAKE       3U   /* Wakeup interrupts */
+#define SC_IRQ_GROUP_SYSCTR     4U   /* System counter interrupts */
+#define SC_IRQ_GROUP_REBOOTED   5U   /* Partition reboot complete */
+#define SC_IRQ_GROUP_REBOOT     6U   /* Partition reboot starting */
+/*@}*/
+
+/*!
+ * @name Defines for sc_irq_temp_t
+ */
+/*@{*/
+#define SC_IRQ_TEMP_HIGH         (1UL << 0U)    /* Temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU0_HIGH    (1UL << 1U)    /* CPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU1_HIGH    (1UL << 2U)    /* CPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU0_HIGH    (1UL << 3U)    /* GPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU1_HIGH    (1UL << 4U)    /* GPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC0_HIGH    (1UL << 5U)    /* DRC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC1_HIGH    (1UL << 6U)    /* DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_VPU_HIGH     (1UL << 7U)    /* DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC0_HIGH   (1UL << 8U)    /* PMIC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC1_HIGH   (1UL << 9U)    /* PMIC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_LOW          (1UL << 10U)   /* Temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU0_LOW     (1UL << 11U)   /* CPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU1_LOW     (1UL << 12U)   /* CPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU0_LOW     (1UL << 13U)   /* GPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU1_LOW     (1UL << 14U)   /* GPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC0_LOW     (1UL << 15U)   /* DRC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC1_LOW     (1UL << 16U)   /* DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_VPU_LOW      (1UL << 17U)   /* DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC0_LOW    (1UL << 18U)   /* PMIC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC1_LOW    (1UL << 19U)   /* PMIC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC2_HIGH   (1UL << 20U)   /* PMIC2 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC2_LOW    (1UL << 21U)   /* PMIC2 temp alarm interrupt */
+/*@}*/
+
+/*!
+ * @name Defines for sc_irq_wdog_t
+ */
+/*@{*/
+#define SC_IRQ_WDOG              (1U << 0U)    /* Watchdog interrupt */
+/*@}*/
+
+/*!
+ * @name Defines for sc_irq_rtc_t
+ */
+/*@{*/
+#define SC_IRQ_RTC               (1U << 0U)    /* RTC interrupt */
+/*@}*/
+
+/*!
+ * @name Defines for sc_irq_wake_t
+ */
+/*@{*/
+#define SC_IRQ_BUTTON            (1U << 0U)    /* Button interrupt */
+#define SC_IRQ_PAD               (1U << 1U)    /* Pad wakeup */
+#define SC_IRQ_USR1              (1U << 2U)    /* User defined 1 */
+#define SC_IRQ_USR2              (1U << 3U)    /* User defined 2 */
+/*@}*/
+
+/*!
+ * @name Defines for sc_irq_sysctr_t
+ */
+/*@{*/
+#define SC_IRQ_SYSCTR            (1U << 0U)    /* SYSCTR interrupt */
+/*@}*/
+
+/* Types */
+
+/*!
+ * This type is used to declare an interrupt group.
+ */
+typedef uint8_t sc_irq_group_t;
+
+/*!
+ * This type is used to declare a bit mask of temp interrupts.
+ */
+typedef uint8_t sc_irq_temp_t;
+
+/*!
+ * This type is used to declare a bit mask of watchdog interrupts.
+ */
+typedef uint8_t sc_irq_wdog_t;
+
+/*!
+ * This type is used to declare a bit mask of RTC interrupts.
+ */
+typedef uint8_t sc_irq_rtc_t;
+
+/*!
+ * This type is used to declare a bit mask of wakeup interrupts.
+ */
+typedef uint8_t sc_irq_wake_t;
+
+/* Functions */
+
+/*!
+ * This function enables/disables interrupts. If pending interrupts
+ * are unmasked, an interrupt will be triggered.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    MU channel
+ * @param[in]     group       group the interrupts are in
+ * @param[in]     mask        mask of interrupts to affect
+ * @param[in]     enable      state to change interrupts to
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if group invalid
+ */
+sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource,
+	sc_irq_group_t group, uint32_t mask, sc_bool_t enable);
+
+/*!
+ * This function returns the current interrupt status (regardless if
+ * masked). Automatically clears pending interrupts.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    MU channel
+ * @param[in]     group       groups the interrupts are in
+ * @param[in]     status      status of interrupts
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_PARM if group invalid
+ *
+ * The returned \a status may show interrupts pending that are
+ * currently masked.
+ */
+sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource,
+	sc_irq_group_t group, uint32_t *status);
+
+#endif /* SC_IRQ_API_H */
+
+/**@}*/
+
diff --git a/plat/imx/common/include/sci/svc/misc/sci_misc_api.h b/plat/imx/common/include/sci/svc/misc/sci_misc_api.h
index a288d58..f4f7585 100755
--- a/plat/imx/common/include/sci/svc/misc/sci_misc_api.h
+++ b/plat/imx/common/include/sci/svc/misc/sci_misc_api.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,8 +21,8 @@
 
 /* Includes */
 
-#include <sci/svc/rm/sci_rm_api.h>
 #include <sci/sci_types.h>
+#include <sci/svc/rm/sci_rm_api.h>
 
 /* Defines */
 
@@ -30,7 +30,7 @@
  * @name Defines for type widths
  */
 /*@{*/
-#define SC_MISC_DMA_GRP_W       5U	/* Width of sc_misc_dma_group_t */
+#define SC_MISC_DMA_GRP_W       5U      /* Width of sc_misc_dma_group_t */
 /*@}*/
 
 /*! Max DMA channel priority group */
@@ -40,35 +40,40 @@
  * @name Defines for sc_misc_boot_status_t
  */
 /*@{*/
-#define SC_MISC_BOOT_STATUS_SUCCESS     0U	/* Success */
-#define SC_MISC_BOOT_STATUS_SECURITY    1U	/* Security violation */
-/*@}*/
-
-/*!
- * @name Defines for sc_misc_seco_auth_cmd_t
- */
-/*@{*/
-#define SC_MISC_SECO_AUTH_SECO_FW       0U	/* SECO Firmware */
-#define SC_MISC_SECO_AUTH_HDMI_TX_FW    1U	/* HDMI TX Firmware */
-#define SC_MISC_SECO_AUTH_HDMI_RX_FW    2U	/* HDMI RX Firmware */
+#define SC_MISC_BOOT_STATUS_SUCCESS     0U   /* Success */
+#define SC_MISC_BOOT_STATUS_SECURITY    1U   /* Security violation */
 /*@}*/
 
 /*!
  * @name Defines for sc_misc_temp_t
  */
 /*@{*/
-#define SC_MISC_TEMP                    0U	/* Temp sensor */
-#define SC_MISC_TEMP_HIGH               1U	/* Temp high alarm */
-#define SC_MISC_TEMP_LOW                2U	/* Temp low alarm */
+#define SC_MISC_TEMP                    0U   /* Temp sensor */
+#define SC_MISC_TEMP_HIGH               1U   /* Temp high alarm */
+#define SC_MISC_TEMP_LOW                2U   /* Temp low alarm */
 /*@}*/
 
 /*!
  * @name Defines for sc_misc_seco_auth_cmd_t
  */
 /*@{*/
-#define SC_MISC_AUTH_CONTAINER          0U	/* Authenticate container */
-#define SC_MISC_VERIFY_IMAGE            1U	/* Verify image */
-#define SC_MISC_REL_CONTAINER           2U	/* Release container */
+#define SC_MISC_AUTH_CONTAINER          0U   /* Authenticate container */
+#define SC_MISC_VERIFY_IMAGE            1U   /* Verify image */
+#define SC_MISC_REL_CONTAINER           2U   /* Release container */
+#define SC_MISC_SECO_AUTH_SECO_FW       3U   /* SECO Firmware */
+#define SC_MISC_SECO_AUTH_HDMI_TX_FW    4U   /* HDMI TX Firmware */
+#define SC_MISC_SECO_AUTH_HDMI_RX_FW    5U   /* HDMI RX Firmware */
+/*@}*/
+
+/*!
+ * @name Defines for sc_misc_bt_t
+ */
+/*@{*/
+#define SC_MISC_BT_PRIMARY              0U   /* Primary boot */
+#define SC_MISC_BT_SECONDARY            1U   /* Secondary boot */
+#define SC_MISC_BT_RECOVERY             2U   /* Recovery boot */
+#define SC_MISC_BT_MANUFACTURE          3U   /* Manufacture boot */
+#define SC_MISC_BT_SERIAL               4U   /* Serial boot */
 /*@}*/
 
 /* Types */
@@ -93,6 +98,11 @@
  */
 typedef uint8_t sc_misc_temp_t;
 
+/*!
+ * This type is used report the boot type.
+ */
+typedef uint8_t sc_misc_bt_t;
+
 /* Functions */
 
 /*!
@@ -118,7 +128,7 @@
  * Refer to the [Control List](@ref CONTROLS) for valid control values.
  */
 sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
-			     sc_ctrl_t ctrl, uint32_t val);
+	sc_ctrl_t ctrl, uint32_t val);
 
 /*!
  * This function gets a miscellaneous control value.
@@ -138,7 +148,7 @@
  * Refer to the [Control List](@ref CONTROLS) for valid control values.
  */
 sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource,
-			     sc_ctrl_t ctrl, uint32_t *val);
+	sc_ctrl_t ctrl, uint32_t *val);
 
 /* @} */
 
@@ -166,7 +176,7 @@
  * Default is the max priority group for the parent partition of \a pt.
  */
 sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt,
-				   sc_misc_dma_group_t max);
+	sc_misc_dma_group_t max);
 
 /*!
  * This function configures the priority group for a DMA channel.
@@ -187,7 +197,7 @@
  * sc_misc_set_max_dma_group().
  */
 sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource,
-			       sc_misc_dma_group_t group);
+	sc_misc_dma_group_t group);
 
 /* @} */
 
@@ -197,146 +207,78 @@
  */
 
 /*!
- * This function loads a SECO image.
- *
- * @param[in]     ipc         IPC handle
- * @param[in]     addr_src    address of image source
- * @param[in]     addr_dst    address of image destination
- * @param[in]     len         lenth of image to load
- * @param[in]     fw          SC_TRUE = firmware load
- *
- * @return Returns an error code (SC_ERR_NONE = success).
- *
- * Return errors codes:
- * - SC_ERR_PARM if word fuse index param out of range or invalid
- * - SC_ERR_UNAVAILABLE if SECO not available
- *
- * This is used to load images via the SECO. Examples include SECO
- * Firmware and IVT/CSF data used for authentication. These are usually
- * loaded into SECO TCM. \a addr_src is in secure memory.
- *
- * See the Security Reference Manual (SRM) for more info.
+ * @deprecated Use sc_seco_image_load() instead.
  */
 sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src,
-				 sc_faddr_t addr_dst, uint32_t len,
-				 sc_bool_t fw);
+	sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw);
 
 /*!
- * This function is used to authenticate a SECO image or command.
- *
- * @param[in]     ipc         IPC handle
- * @param[in]     cmd         authenticate command
- * @param[in]     addr        address of/or metadata
- *
- * @return Returns an error code (SC_ERR_NONE = success).
- *
- * Return errors codes:
- * - SC_ERR_PARM if word fuse index param out of range or invalid
- * - SC_ERR_UNAVAILABLE if SECO not available
- *
- * This is used to authenticate a SECO image or issue a security
- * command. \a addr often points to an container. It is also
- * just data (or even unused) for some commands.
- *
- * See the Security Reference Manual (SRM) for more info.
+ * @deprecated Use sc_seco_authenticate() instead.
  */
 sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc,
-				   sc_misc_seco_auth_cmd_t cmd,
-				   sc_faddr_t addr);
+	sc_misc_seco_auth_cmd_t cmd, sc_faddr_t addr);
 
 /*!
- * This function securely writes a group of fuse words.
- *
- * @param[in]     ipc         IPC handle
- * @param[in]     addr        address of message block
- *
- * @return Returns and error code (SC_ERR_NONE = success).
- *
- * Return errors codes:
- * - SC_ERR_UNAVAILABLE if SECO not available
- *
- * Note \a addr must be a pointer to a signed message block.
- *
- * See the Security Reference Manual (SRM) for more info.
+ * @deprecated Use sc_seco_fuse_write() instead.
  */
 sc_err_t sc_misc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr);
 
 /*!
- * This function securely enables debug.
- *
- * @param[in]     ipc         IPC handle
- * @param[in]     addr        address of message block
- *
- * @return Returns and error code (SC_ERR_NONE = success).
- *
- * Return errors codes:
- * - SC_ERR_UNAVAILABLE if SECO not available
- *
- * Note \a addr must be a pointer to a signed message block.
- *
- * See the Security Reference Manual (SRM) for more info.
+ * @deprecated Use sc_seco_enable_debug() instead.
  */
 sc_err_t sc_misc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr);
 
 /*!
- * This function updates the lifecycle of the device.
- *
- * @param[in]     ipc         IPC handle
- * @param[in]     lifecycle   new lifecycle
- *
- * @return Returns and error code (SC_ERR_NONE = success).
- *
- * Return errors codes:
- * - SC_ERR_UNAVAILABLE if SECO not available
- *
- * This message is used for going from Open to NXP Closed to OEM Closed.
- *
- * See the Security Reference Manual (SRM) for more info.
+ * @deprecated Use sc_seco_forward_lifecycle() instead.
  */
-sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t lifecycle);
+sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t change);
 
 /*!
- * This function updates the lifecycle to one of the return lifecycles.
- *
- * @param[in]     ipc         IPC handle
- * @param[in]     addr        address of message block
- *
- * @return Returns and error code (SC_ERR_NONE = success).
- *
- * Return errors codes:
- * - SC_ERR_UNAVAILABLE if SECO not available
- *
- * Note \a addr must be a pointer to a signed message block.
- *
- * To switch back to NXP states (Full Field Return), message must be signed
- * by NXP SRK. For OEM States (Partial Field Return), must be signed by OEM
- * SRK.
- *
- * See the Security Reference Manual (SRM) for more info.
+ * @deprecated Use sc_seco_return_lifecycle() instead.
  */
 sc_err_t sc_misc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr);
 
 /*!
- * This function is used to return the SECO FW build info.
- *
- * @param[in]     ipc         IPC handle
- * @param[out]    version     pointer to return build number
- * @param[out]    commit      pointer to return commit ID (git SHA-1)
+ * @deprecated Use sc_seco_build_info() instead.
  */
-void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version, uint32_t *commit);
+void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version,
+	uint32_t *commit);
 
 /*!
- * This function is used to return SECO chip info.
- *
- * @param[in]     ipc         IPC handle
- * @param[out]    lc          pointer to return lifecycle
- * @param[out]    monotonic   pointer to return monotonic counter
- * @param[out]    uid_l       pointer to return UID (lower 32 bits)
- * @param[out]    uid_h       pointer to return UID (upper 32 bits)
+ * @deprecated Use sc_seco_chip_info() instead.
  */
 sc_err_t sc_misc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc,
-				uint16_t *monotonic, uint32_t *uid_l,
-				uint32_t *uid_h);
+	uint16_t *monotonic, uint32_t *uid_l, uint32_t *uid_h);
+
+/*!
+ * @deprecated Use sc_seco_attest_mode() instead.
+ */
+sc_err_t sc_misc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode);
+
+/*!
+ * @deprecated Use sc_seco_attest() instead.
+ */
+sc_err_t sc_misc_seco_attest(sc_ipc_t ipc, uint64_t nonce);
+
+/*!
+ * @deprecated Use sc_seco_get_attest_pkey() instead.
+ */
+sc_err_t sc_misc_seco_get_attest_pkey(sc_ipc_t ipc, sc_faddr_t addr);
+
+/*!
+ * @deprecated Use sc_seco_get_attest_sign() instead.
+ */
+sc_err_t sc_misc_seco_get_attest_sign(sc_ipc_t ipc, sc_faddr_t addr);
+
+/*!
+ * @deprecated Use sc_seco_attest_verify() instead.
+ */
+sc_err_t sc_misc_seco_attest_verify(sc_ipc_t ipc, sc_faddr_t addr);
+
+/*!
+ * @deprecated Use sc_seco_commit() instead.
+ */
+sc_err_t sc_misc_seco_commit(sc_ipc_t ipc, uint32_t *info);
 
 /* @} */
 
@@ -373,7 +315,8 @@
  * @param[out]    build       pointer to return build number
  * @param[out]    commit      pointer to return commit ID (git SHA-1)
  */
-void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, uint32_t *commit);
+void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build,
+	uint32_t *commit);
 
 /*!
  * This function is used to return the device's unique ID.
@@ -382,7 +325,8 @@
  * @param[out]    id_l        pointer to return lower 32-bit of ID [31:0]
  * @param[out]    id_h        pointer to return upper 32-bits of ID [63:32]
  */
-void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, uint32_t *id_h);
+void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l,
+	uint32_t *id_h);
 
 /* @} */
 
@@ -412,8 +356,7 @@
  * FISType and PM_Port.
  */
 sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource,
-			 sc_rsrc_t resource_mst, uint16_t ari,
-			 sc_bool_t enable);
+	sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable);
 
 /*!
  * This function reports boot status.
@@ -462,16 +405,24 @@
 sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val);
 
 /*!
- * This function writes a given fuse word index.
+ * This function writes a given fuse word index. Only the owner of the
+ * SC_R_SYSTEM resource or a partition with access permissions to
+ * SC_R_SYSTEM can do this.
  *
  * @param[in]     ipc         IPC handle
  * @param[in]     word        fuse word index
  * @param[in]     val         fuse write value
  *
+ * The command is passed as is to SECO. SECO uses part of the
+ * \a word parameter to indicate if the fuse should be locked
+ * after programming. See the "Write common fuse" section of
+ * the Security Reference Manual (SRM) for more info.
+ *
  * @return Returns and error code (SC_ERR_NONE = success).
  *
  * Return errors codes:
  * - SC_ERR_PARM if word fuse index param out of range or invalid
+ * - SC_ERR_NOACCESS if caller does not have SC_R_SYSTEM access
  * - SC_ERR_NOACCESS if write operation failed
  * - SC_ERR_LOCKED if write operation is locked
  */
@@ -494,9 +445,11 @@
  *
  * Return errors codes:
  * - SC_ERR_PARM if parameters invalid
+ * - SC_ERR_NOACCESS if caller does not own the resource
+ * - SC_ERR_NOPOWER if power domain of resource not powered
  */
 sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource,
-			  sc_misc_temp_t temp, int16_t celsius, int8_t tenths);
+	sc_misc_temp_t temp, int16_t celsius, int8_t tenths);
 
 /*!
  * This function gets a temp sensor value.
@@ -511,10 +464,11 @@
  *
  * Return errors codes:
  * - SC_ERR_PARM if parameters invalid
+ * - SC_ERR_BUSY if temp not ready yet (time delay after power on)
+ * - SC_ERR_NOPOWER if power domain of resource not powered
  */
 sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource,
-			  sc_misc_temp_t temp, int16_t * celsius,
-			  int8_t * tenths);
+	sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths);
 
 /*!
  * This function returns the boot device.
@@ -522,7 +476,20 @@
  * @param[in]     ipc         IPC handle
  * @param[out]    dev         pointer to return boot device
  */
-void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t * dev);
+void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev);
+
+/*!
+ * This function returns the boot type.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    type        pointer to return boot type
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * Return errors code:
+ * - SC_ERR_UNAVAILABLE if type not passed by ROM
+ */
+sc_err_t sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t *type);
 
 /*!
  * This function returns the current status of the ON/OFF button.
@@ -532,8 +499,32 @@
  */
 void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status);
 
+/*!
+ * This function returns the ROM patch checksum.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    checksum    pointer to return checksum
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_misc_rompatch_checksum(sc_ipc_t ipc, uint32_t *checksum);
+
+/*!
+ * This function calls the board IOCTL function.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in,out] parm1       pointer to pass parameter 1
+ * @param[in,out] parm2       pointer to pass parameter 2
+ * @param[in,out] parm3       pointer to pass parameter 3
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_misc_board_ioctl(sc_ipc_t ipc, uint32_t *parm1,
+	uint32_t *parm2, uint32_t *parm3);
+
 /* @} */
 
-#endif				/* SC_MISC_API_H */
+#endif /* SC_MISC_API_H */
 
 /**@}*/
+
diff --git a/plat/imx/common/include/sci/svc/pad/sci_pad_api.h b/plat/imx/common/include/sci/svc/pad/sci_pad_api.h
index 0955678..7727d66 100644
--- a/plat/imx/common/include/sci/svc/pad/sci_pad_api.h
+++ b/plat/imx/common/include/sci/svc/pad/sci_pad_api.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,7 +19,7 @@
  * features supported by the SC firmware include:
  *
  * - Configuring the mux, input/output connection, and low-power isolation
-     mode.
+	 mode.
  * - Configuring the technology-specific pad setting such as drive strength,
  *   pullup/pulldown, etc.
  * - Configuring compensation for pad groups with dual voltage capability.
@@ -49,6 +50,9 @@
  *
  * Note muxing two input pads to the same IP functional signal will
  * result in undefined behavior.
+ *
+ * @includedoc pad/details.dox
+ *
  * @{
  */
 
@@ -66,79 +70,79 @@
  * @name Defines for type widths
  */
 /*@{*/
-#define SC_PAD_MUX_W            3	/* Width of mux parameter */
+#define SC_PAD_MUX_W            3U    /* Width of mux parameter */
 /*@}*/
 
 /*!
  * @name Defines for sc_pad_config_t
  */
 /*@{*/
-#define SC_PAD_CONFIG_NORMAL    0U	/* Normal */
-#define SC_PAD_CONFIG_OD        1U	/* Open Drain */
-#define SC_PAD_CONFIG_OD_IN     2U	/* Open Drain and input */
-#define SC_PAD_CONFIG_OUT_IN    3U	/* Output and input */
+#define SC_PAD_CONFIG_NORMAL    0U    /* Normal */
+#define SC_PAD_CONFIG_OD        1U    /* Open Drain */
+#define SC_PAD_CONFIG_OD_IN     2U    /* Open Drain and input */
+#define SC_PAD_CONFIG_OUT_IN    3U    /* Output and input */
 /*@}*/
 
 /*!
  * @name Defines for sc_pad_iso_t
  */
 /*@{*/
-#define SC_PAD_ISO_OFF          0U	/* ISO latch is transparent */
-#define SC_PAD_ISO_EARLY        1U	/* Follow EARLY_ISO */
-#define SC_PAD_ISO_LATE         2U	/* Follow LATE_ISO */
-#define SC_PAD_ISO_ON           3U	/* ISO latched data is held */
+#define SC_PAD_ISO_OFF          0U    /* ISO latch is transparent */
+#define SC_PAD_ISO_EARLY        1U    /* Follow EARLY_ISO */
+#define SC_PAD_ISO_LATE         2U    /* Follow LATE_ISO */
+#define SC_PAD_ISO_ON           3U    /* ISO latched data is held */
 /*@}*/
 
 /*!
  * @name Defines for sc_pad_28fdsoi_dse_t
  */
 /*@{*/
-#define SC_PAD_28FDSOI_DSE_18V_1MA   0U	/* Drive strength of 1mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_2MA   1U	/* Drive strength of 2mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_4MA   2U	/* Drive strength of 4mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_6MA   3U	/* Drive strength of 6mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_8MA   4U	/* Drive strength of 8mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_10MA  5U	/* Drive strength of 10mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_12MA  6U	/* Drive strength of 12mA for 1.8v */
-#define SC_PAD_28FDSOI_DSE_18V_HS    7U	/* High-speed drive strength for 1.8v */
-#define SC_PAD_28FDSOI_DSE_33V_2MA   0U	/* Drive strength of 2mA for 3.3v */
-#define SC_PAD_28FDSOI_DSE_33V_4MA   1U	/* Drive strength of 4mA for 3.3v */
-#define SC_PAD_28FDSOI_DSE_33V_8MA   2U	/* Drive strength of 8mA for 3.3v */
-#define SC_PAD_28FDSOI_DSE_33V_12MA  3U	/* Drive strength of 12mA for 3.3v */
-#define SC_PAD_28FDSOI_DSE_DV_HIGH   0U	/* High drive strength for dual volt */
-#define SC_PAD_28FDSOI_DSE_DV_LOW    1U	/* Low drive strength for dual volt */
+#define SC_PAD_28FDSOI_DSE_18V_1MA   0U    /* Drive strength of 1mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_2MA   1U    /* Drive strength of 2mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_4MA   2U    /* Drive strength of 4mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_6MA   3U    /* Drive strength of 6mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_8MA   4U    /* Drive strength of 8mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_10MA  5U    /* Drive strength of 10mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_12MA  6U    /* Drive strength of 12mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_HS    7U    /* High-speed drive strength for 1.8v */
+#define SC_PAD_28FDSOI_DSE_33V_2MA   0U    /* Drive strength of 2mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_33V_4MA   1U    /* Drive strength of 4mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_33V_8MA   2U    /* Drive strength of 8mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_33V_12MA  3U    /* Drive strength of 12mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_DV_HIGH   0U    /* High drive strength for dual volt */
+#define SC_PAD_28FDSOI_DSE_DV_LOW    1U    /* Low drive strength for dual volt */
 /*@}*/
 
 /*!
  * @name Defines for sc_pad_28fdsoi_ps_t
  */
 /*@{*/
-#define SC_PAD_28FDSOI_PS_KEEPER 0U	/* Bus-keeper (only valid for 1.8v) */
-#define SC_PAD_28FDSOI_PS_PU     1U	/* Pull-up */
-#define SC_PAD_28FDSOI_PS_PD     2U	/* Pull-down */
-#define SC_PAD_28FDSOI_PS_NONE   3U	/* No pull (disabled) */
+#define SC_PAD_28FDSOI_PS_KEEPER 0U    /* Bus-keeper (only valid for 1.8v) */
+#define SC_PAD_28FDSOI_PS_PU     1U    /* Pull-up */
+#define SC_PAD_28FDSOI_PS_PD     2U    /* Pull-down */
+#define SC_PAD_28FDSOI_PS_NONE   3U    /* No pull (disabled) */
 /*@}*/
 
 /*!
  * @name Defines for sc_pad_28fdsoi_pus_t
  */
 /*@{*/
-#define SC_PAD_28FDSOI_PUS_30K_PD  0U	/* 30K pull-down */
-#define SC_PAD_28FDSOI_PUS_100K_PU 1U	/* 100K pull-up */
-#define SC_PAD_28FDSOI_PUS_3K_PU   2U	/* 3K pull-up */
-#define SC_PAD_28FDSOI_PUS_30K_PU  3U	/* 30K pull-up */
+#define SC_PAD_28FDSOI_PUS_30K_PD  0U    /* 30K pull-down */
+#define SC_PAD_28FDSOI_PUS_100K_PU 1U    /* 100K pull-up */
+#define SC_PAD_28FDSOI_PUS_3K_PU   2U    /* 3K pull-up */
+#define SC_PAD_28FDSOI_PUS_30K_PU  3U    /* 30K pull-up */
 /*@}*/
 
 /*!
  * @name Defines for sc_pad_wakeup_t
  */
 /*@{*/
-#define SC_PAD_WAKEUP_OFF       0U	/* Off */
-#define SC_PAD_WAKEUP_CLEAR     1U	/* Clears pending flag */
-#define SC_PAD_WAKEUP_LOW_LVL   4U	/* Low level */
-#define SC_PAD_WAKEUP_FALL_EDGE 5U	/* Falling edge */
-#define SC_PAD_WAKEUP_RISE_EDGE 6U	/* Rising edge */
-#define SC_PAD_WAKEUP_HIGH_LVL  7U	/* High-level */
+#define SC_PAD_WAKEUP_OFF       0U    /* Off */
+#define SC_PAD_WAKEUP_CLEAR     1U    /* Clears pending flag */
+#define SC_PAD_WAKEUP_LOW_LVL   4U    /* Low level */
+#define SC_PAD_WAKEUP_FALL_EDGE 5U    /* Falling edge */
+#define SC_PAD_WAKEUP_RISE_EDGE 6U    /* Rising edge */
+#define SC_PAD_WAKEUP_HIGH_LVL  7U    /* High-level */
 /*@}*/
 
 /* Types */
@@ -212,7 +216,7 @@
  * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
  */
 sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad,
-			uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso);
+	uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso);
 
 /*!
  * This function gets the mux settings for a pad. This includes
@@ -233,8 +237,7 @@
  * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
  */
 sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad,
-			uint8_t *mux, sc_pad_config_t *config,
-			sc_pad_iso_t *iso);
+	uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso);
 
 /*!
  * This function configures the general purpose pad control. This
@@ -291,7 +294,8 @@
  *
  * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
  */
-sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t wakeup);
+sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad,
+	sc_pad_wakeup_t wakeup);
 
 /*!
  * This function gets the wakeup mode of a pad.
@@ -308,7 +312,8 @@
  *
  * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
  */
-sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t *wakeup);
+sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad,
+	sc_pad_wakeup_t *wakeup);
 
 /*!
  * This function configures a pad.
@@ -336,8 +341,8 @@
  * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
  */
 sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux,
-			sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
-			sc_pad_wakeup_t wakeup);
+	sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
+	sc_pad_wakeup_t wakeup);
 
 /*!
  * This function gets a pad's config.
@@ -362,8 +367,8 @@
  * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
  */
 sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux,
-			sc_pad_config_t *config, sc_pad_iso_t *iso,
-			uint32_t *ctrl, sc_pad_wakeup_t *wakeup);
+	sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl,
+	sc_pad_wakeup_t *wakeup);
 
 /* @} */
 
@@ -433,8 +438,7 @@
  * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
  */
 sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
-			       sc_pad_28fdsoi_dse_t dse,
-			       sc_pad_28fdsoi_ps_t ps);
+	sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps);
 
 /*!
  * This function gets the pad control specific to 28FDSOI.
@@ -454,8 +458,7 @@
  * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
  */
 sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
-			       sc_pad_28fdsoi_dse_t *dse,
-			       sc_pad_28fdsoi_ps_t *ps);
+	sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps);
 
 /*!
  * This function configures the pad control specific to 28FDSOI.
@@ -478,9 +481,8 @@
  * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
  */
 sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
-				    sc_pad_28fdsoi_dse_t dse, sc_bool_t hys,
-				    sc_pad_28fdsoi_pus_t pus, sc_bool_t pke,
-				    sc_bool_t pue);
+	sc_pad_28fdsoi_dse_t dse, sc_bool_t hys, sc_pad_28fdsoi_pus_t pus,
+	sc_bool_t pke, sc_bool_t pue);
 
 /*!
  * This function gets the pad control specific to 28FDSOI.
@@ -503,9 +505,8 @@
  * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
  */
 sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
-				    sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys,
-				    sc_pad_28fdsoi_pus_t *pus, sc_bool_t *pke,
-				    sc_bool_t *pue);
+	sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys, sc_pad_28fdsoi_pus_t *pus,
+	sc_bool_t *pke, sc_bool_t *pue);
 
 /*!
  * This function configures the compensation control specific to 28FDSOI.
@@ -532,9 +533,8 @@
  * operation (e.g. some Ethernet pads).
  */
 sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
-				    uint8_t compen, sc_bool_t fastfrz,
-				    uint8_t rasrcp, uint8_t rasrcn,
-				    sc_bool_t nasrc_sel, sc_bool_t psw_ovr);
+	uint8_t compen, sc_bool_t fastfrz, uint8_t rasrcp, uint8_t rasrcn,
+	sc_bool_t nasrc_sel, sc_bool_t psw_ovr);
 
 /*!
  * This function gets the compensation control specific to 28FDSOI.
@@ -560,13 +560,12 @@
  * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
  */
 sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
-				    uint8_t *compen, sc_bool_t *fastfrz,
-				    uint8_t *rasrcp, uint8_t *rasrcn,
-				    sc_bool_t *nasrc_sel, sc_bool_t *compok,
-				    uint8_t *nasrc, sc_bool_t *psw_ovr);
+	uint8_t *compen, sc_bool_t *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn,
+	sc_bool_t *nasrc_sel, sc_bool_t *compok, uint8_t *nasrc, sc_bool_t *psw_ovr);
 
 /* @} */
 
-#endif				/* SC_PAD_API_H */
+#endif /* SC_PAD_API_H */
 
 /**@}*/
+
diff --git a/plat/imx/common/include/sci/svc/pm/sci_pm_api.h b/plat/imx/common/include/sci/svc/pm/sci_pm_api.h
index 5c3c382..4781629 100644
--- a/plat/imx/common/include/sci/svc/pm/sci_pm_api.h
+++ b/plat/imx/common/include/sci/svc/pm/sci_pm_api.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,6 +14,8 @@
  *
  * Module for the Power Management (PM) service.
  *
+ * @includedoc pm/details.dox
+ *
  * @{
  */
 
@@ -30,10 +33,10 @@
  * @name Defines for type widths
  */
 /*@{*/
-#define SC_PM_POWER_MODE_W      2	/* Width of sc_pm_power_mode_t */
-#define SC_PM_CLOCK_MODE_W      3	/* Width of sc_pm_clock_mode_t */
-#define SC_PM_RESET_TYPE_W      2	/* Width of sc_pm_reset_type_t */
-#define SC_PM_RESET_REASON_W    3	/* Width of sc_pm_reset_reason_t */
+#define SC_PM_POWER_MODE_W      2U      /* Width of sc_pm_power_mode_t */
+#define SC_PM_CLOCK_MODE_W      3U      /* Width of sc_pm_clock_mode_t */
+#define SC_PM_RESET_TYPE_W      2U      /* Width of sc_pm_reset_type_t */
+#define SC_PM_RESET_REASON_W    4U      /* Width of sc_pm_reset_reason_t */
 /*@}*/
 
 /*!
@@ -46,114 +49,108 @@
  * @name Defines for ALL parameters
  */
 /*@{*/
-#define SC_PM_CLK_ALL   UINT8_MAX	/* All clocks */
+#define SC_PM_CLK_ALL   ((sc_pm_clk_t) UINT8_MAX)   /* All clocks */
 /*@}*/
 
 /*!
  * @name Defines for sc_pm_power_mode_t
  */
 /*@{*/
-#define SC_PM_PW_MODE_OFF       0U	/* Power off */
-#define SC_PM_PW_MODE_STBY      1U	/* Power in standby */
-#define SC_PM_PW_MODE_LP        2U	/* Power in low-power */
-#define SC_PM_PW_MODE_ON        3U	/* Power on */
+#define SC_PM_PW_MODE_OFF       0U      /* Power off */
+#define SC_PM_PW_MODE_STBY      1U      /* Power in standby */
+#define SC_PM_PW_MODE_LP        2U      /* Power in low-power */
+#define SC_PM_PW_MODE_ON        3U      /* Power on */
 /*@}*/
 
 /*!
  * @name Defines for sc_pm_clk_t
  */
 /*@{*/
-#define SC_PM_CLK_SLV_BUS       0U	/* Slave bus clock */
-#define SC_PM_CLK_MST_BUS       1U	/* Master bus clock */
-#define SC_PM_CLK_PER           2U	/* Peripheral clock */
-#define SC_PM_CLK_PHY           3U	/* Phy clock */
-#define SC_PM_CLK_MISC          4U	/* Misc clock */
-#define SC_PM_CLK_MISC0         0U	/* Misc 0 clock */
-#define SC_PM_CLK_MISC1         1U	/* Misc 1 clock */
-#define SC_PM_CLK_MISC2         2U	/* Misc 2 clock */
-#define SC_PM_CLK_MISC3         3U	/* Misc 3 clock */
-#define SC_PM_CLK_MISC4         4U	/* Misc 4 clock */
-#define SC_PM_CLK_CPU           2U	/* CPU clock */
-#define SC_PM_CLK_PLL           4U	/* PLL */
-#define SC_PM_CLK_BYPASS        4U	/* Bypass clock */
+#define SC_PM_CLK_SLV_BUS       0U      /* Slave bus clock */
+#define SC_PM_CLK_MST_BUS       1U      /* Master bus clock */
+#define SC_PM_CLK_PER           2U      /* Peripheral clock */
+#define SC_PM_CLK_PHY           3U      /* Phy clock */
+#define SC_PM_CLK_MISC          4U      /* Misc clock */
+#define SC_PM_CLK_MISC0         0U      /* Misc 0 clock */
+#define SC_PM_CLK_MISC1         1U      /* Misc 1 clock */
+#define SC_PM_CLK_MISC2         2U      /* Misc 2 clock */
+#define SC_PM_CLK_MISC3         3U      /* Misc 3 clock */
+#define SC_PM_CLK_MISC4         4U      /* Misc 4 clock */
+#define SC_PM_CLK_CPU           2U      /* CPU clock */
+#define SC_PM_CLK_PLL           4U      /* PLL */
+#define SC_PM_CLK_BYPASS        4U      /* Bypass clock */
 /*@}*/
 
 /*!
  * @name Defines for sc_pm_clk_mode_t
  */
 /*@{*/
-#define SC_PM_CLK_MODE_ROM_INIT        0U	/* Clock is initialized by ROM. */
-#define SC_PM_CLK_MODE_OFF             1U	/* Clock is disabled */
-#define SC_PM_CLK_MODE_ON              2U	/* Clock is enabled. */
-#define SC_PM_CLK_MODE_AUTOGATE_SW     3U	/* Clock is in SW autogate mode */
-#define SC_PM_CLK_MODE_AUTOGATE_HW     4U	/* Clock is in HW autogate mode */
-#define SC_PM_CLK_MODE_AUTOGATE_SW_HW  5U	/* Clock is in SW-HW autogate mode */
+#define SC_PM_CLK_MODE_ROM_INIT        0U    /* Clock is initialized by ROM. */
+#define SC_PM_CLK_MODE_OFF             1U    /* Clock is disabled */
+#define SC_PM_CLK_MODE_ON              2U    /* Clock is enabled. */
+#define SC_PM_CLK_MODE_AUTOGATE_SW     3U    /* Clock is in SW autogate mode */
+#define SC_PM_CLK_MODE_AUTOGATE_HW     4U    /* Clock is in HW autogate mode */
+#define SC_PM_CLK_MODE_AUTOGATE_SW_HW  5U    /* Clock is in SW-HW autogate mode */
 /*@}*/
 
 /*!
  * @name Defines for sc_pm_clk_parent_t
  */
 /*@{*/
-#define SC_PM_PARENT_XTAL              0U	/* Parent is XTAL. */
-#define SC_PM_PARENT_PLL0              1U	/* Parent is PLL0 */
-#define SC_PM_PARENT_PLL1              2U	/* Parent is PLL1 or PLL0/2 */
-#define SC_PM_PARENT_PLL2              3U	/* Parent in PLL2 or PLL0/4 */
-#define SC_PM_PARENT_BYPS              4U	/* Parent is a bypass clock. */
+#define SC_PM_PARENT_XTAL              0U    /* Parent is XTAL. */
+#define SC_PM_PARENT_PLL0              1U    /* Parent is PLL0 */
+#define SC_PM_PARENT_PLL1              2U    /* Parent is PLL1 or PLL0/2 */
+#define SC_PM_PARENT_PLL2              3U    /* Parent in PLL2 or PLL0/4 */
+#define SC_PM_PARENT_BYPS              4U    /* Parent is a bypass clock. */
 /*@}*/
 
 /*!
  * @name Defines for sc_pm_reset_type_t
  */
 /*@{*/
-#define SC_PM_RESET_TYPE_COLD          0U	/* Cold reset */
-#define SC_PM_RESET_TYPE_WARM          1U	/* Warm reset */
-#define SC_PM_RESET_TYPE_BOARD         2U	/* Board reset */
-/*@}*/
-
-/*!
- * @name Defines for sc_pm_reset_cause_t
- */
-/*@{*/
-#define SC_PM_RESET_CAUSE_TEMP         0U	/* Reset due to temp panic alarm */
-#define SC_PM_RESET_CAUSE_FAULT        1U	/* Reset due to fault exception */
-#define SC_PM_RESET_CAUSE_IRQ          2U	/* Reset due to SCU reset IRQ */
-#define SC_PM_RESET_CAUSE_WDOG         3U	/* Reset due to SW WDOG */
-#define SC_PM_RESET_CAUSE_API          4U	/* Reset due to pm_reset() or monitor */
+#define SC_PM_RESET_TYPE_COLD          0U    /* Cold reset */
+#define SC_PM_RESET_TYPE_WARM          1U    /* Warm reset */
+#define SC_PM_RESET_TYPE_BOARD         2U    /* Board reset */
 /*@}*/
 
 /*!
  * @name Defines for sc_pm_reset_reason_t
  */
 /*@{*/
-#define SC_PM_RESET_REASON_POR         0U	/* Power on reset */
-#define SC_PM_RESET_REASON_WARM        1U	/* Warm reset */
-#define SC_PM_RESET_REASON_SW          2U	/* Software reset */
-#define SC_PM_RESET_REASON_WDOG        3U	/* Watchdog reset */
-#define SC_PM_RESET_REASON_LOCKUP      4U	/* Lockup reset */
-#define SC_PM_RESET_REASON_TAMPER      5U	/* Tamper reset */
-#define SC_PM_RESET_REASON_TEMP        6U	/* Temp reset */
-#define SC_PM_RESET_REASON_LOW_VOLT    7U	/* Low voltage reset */
+#define SC_PM_RESET_REASON_POR         0U    /* Power on reset */
+#define SC_PM_RESET_REASON_JTAG        1U    /* JTAG reset */
+#define SC_PM_RESET_REASON_SW          2U    /* Software reset */
+#define SC_PM_RESET_REASON_WDOG        3U    /* Partition watchdog reset */
+#define SC_PM_RESET_REASON_LOCKUP      4U    /* SCU lockup reset */
+#define SC_PM_RESET_REASON_SNVS        5U    /* SNVS reset */
+#define SC_PM_RESET_REASON_TEMP        6U    /* Temp panic reset */
+#define SC_PM_RESET_REASON_MSI         7U    /* MSI reset */
+#define SC_PM_RESET_REASON_UECC        8U    /* ECC reset */
+#define SC_PM_RESET_REASON_SCFW_WDOG   9U    /* SCFW watchdog reset */
+#define SC_PM_RESET_REASON_ROM_WDOG    10U   /* SCU ROM watchdog reset */
+#define SC_PM_RESET_REASON_SECO        11U   /* SECO reset */
+#define SC_PM_RESET_REASON_SCFW_FAULT  12U   /* SCFW fault reset */
 /*@}*/
 
 /*!
  * @name Defines for sc_pm_sys_if_t
  */
 /*@{*/
-#define SC_PM_SYS_IF_INTERCONNECT       0U	/* System interconnect */
-#define SC_PM_SYS_IF_MU                 1U	/* AP -> SCU message units */
-#define SC_PM_SYS_IF_OCMEM              2U	/* On-chip memory (ROM/OCRAM) */
-#define SC_PM_SYS_IF_DDR                3U	/* DDR memory */
+#define SC_PM_SYS_IF_INTERCONNECT       0U   /* System interconnect */
+#define SC_PM_SYS_IF_MU                 1U   /* AP -> SCU message units */
+#define SC_PM_SYS_IF_OCMEM              2U   /* On-chip memory (ROM/OCRAM) */
+#define SC_PM_SYS_IF_DDR                3U   /* DDR memory */
 /*@}*/
 
 /*!
  * @name Defines for sc_pm_wake_src_t
  */
 /*@{*/
-#define SC_PM_WAKE_SRC_NONE             0U	/* No wake source, used for self-kill */
-#define SC_PM_WAKE_SRC_SCU              1U	/* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */
-#define SC_PM_WAKE_SRC_IRQSTEER         2U	/* Wakeup from IRQSTEER to resume CPU (GIC powered down) */
-#define SC_PM_WAKE_SRC_IRQSTEER_GIC     3U	/* Wakeup from IRQSTEER+GIC to wake CPU  (GIC clock gated) */
-#define SC_PM_WAKE_SRC_GIC              4U	/* Wakeup from GIC to wake CPU */
+#define SC_PM_WAKE_SRC_NONE             0U   /* No wake source, used for self-kill */
+#define SC_PM_WAKE_SRC_SCU              1U   /* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */
+#define SC_PM_WAKE_SRC_IRQSTEER         2U   /* Wakeup from IRQSTEER to resume CPU (GIC powered down) */
+#define SC_PM_WAKE_SRC_IRQSTEER_GIC     3U   /* Wakeup from IRQSTEER+GIC to wake CPU  (GIC clock gated) */
+#define SC_PM_WAKE_SRC_GIC              4U   /* Wakeup from GIC to wake CPU */
 /*@}*/
 
 /* Types */
@@ -191,11 +188,6 @@
 typedef uint8_t sc_pm_reset_type_t;
 
 /*!
- * This type is used to declare a desired reset type.
- */
-typedef uint8_t sc_pm_reset_cause;
-
-/*!
  * This type is used to declare a reason for a reset.
  */
 typedef uint8_t sc_pm_reset_reason_t;
@@ -219,7 +211,8 @@
 
 /*!
  * This function sets the system power mode. Only the owner of the
- * SC_R_SYSTEM resource can do this.
+ * SC_R_SYSTEM resource or a partition with access permissions to
+ * SC_R_SYSTEM can do this.
  *
  * @param[in]     ipc         IPC handle
  * @param[in]     mode        power mode to apply
@@ -228,7 +221,7 @@
  *
  * Return errors:
  * - SC_ERR_PARM if invalid mode,
- * - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM
+ * - SC_ERR_NOACCESS if caller does not have SC_R_SYSTEM access
  *
  * @see sc_pm_set_sys_power_mode().
  */
@@ -254,7 +247,7 @@
  * individual resource mode set using sc_pm_set_resource_power_mode().
  */
 sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
-					sc_pm_power_mode_t mode);
+	sc_pm_power_mode_t mode);
 
 /*!
  * This function gets the power mode of a partition.
@@ -269,7 +262,7 @@
  * - SC_ERR_PARM if invalid partition
  */
 sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
-				  sc_pm_power_mode_t *mode);
+	sc_pm_power_mode_t *mode);
 
 /*!
  * This function sets the power mode of a resource.
@@ -285,6 +278,9 @@
  * - SC_ERR_NOACCESS if caller's partition is not the resource owner
  *   or parent of the owner
  *
+ * Resources must be at SC_PM_PW_MODE_LP mode or higher to access them,
+ * otherwise the master will get a bus error or hang.
+ *
  * This function will record the individual resource power mode
  * and change it if the requested mode is lower than or equal to the
  * partition power mode set with sc_pm_set_partition_power_mode().
@@ -304,7 +300,33 @@
  * infrastructure (bus fabrics, clock domains, etc.).
  */
 sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
-				       sc_pm_power_mode_t mode);
+	sc_pm_power_mode_t mode);
+
+/*!
+* This function sets the power mode for all the resources owned
+* by a child partition.
+*
+* @param[in]     ipc         IPC handle
+* @param[in]     pt          handle of child partition
+* @param[in]     mode        power mode to apply
+* @param[in]     exclude     resource to exclude
+*
+* @return Returns an error code (SC_ERR_NONE = success).
+*
+* Return errors:
+* - SC_ERR_PARM if invalid partition or mode,
+* - SC_ERR_NOACCESS if caller's partition is not the parent
+*   of \a pt
+*
+* This functions loops through all the resources owned by \a pt
+* and sets the power mode to \a mode. It will skip setting
+* \a exclude (SC_R_LAST to skip none).
+*
+* This function can only be called by the parent. It is used to
+* implement some aspects of virtualization.
+*/
+sc_err_t sc_pm_set_resource_power_mode_all(sc_ipc_t ipc,
+	sc_rm_pt_t pt, sc_pm_power_mode_t mode, sc_rsrc_t exclude);
 
 /*!
  * This function gets the power mode of a resource.
@@ -319,7 +341,7 @@
  * returned does not reflect the power mode of the partition..
  */
 sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
-				       sc_pm_power_mode_t *mode);
+	sc_pm_power_mode_t *mode);
 
 /*!
  * This function requests the low power mode some of the resources
@@ -340,7 +362,7 @@
  *
  */
 sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
-				  sc_pm_power_mode_t mode);
+	sc_pm_power_mode_t mode);
 
 /*!
  * This function requests low-power mode entry for CPU/cluster
@@ -363,8 +385,7 @@
  *
  */
 sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
-				      sc_pm_power_mode_t mode,
-				      sc_pm_wake_src_t wake_src);
+	sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src);
 
 /*!
  * This function is used to set the resume address of a CPU.
@@ -381,7 +402,7 @@
  *   resource (CPU) owner
  */
 sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource,
-				   sc_faddr_t address);
+	sc_faddr_t address);
 
 /*!
  * This function is used to set parameters for CPU resume from
@@ -400,7 +421,7 @@
  *   resource (CPU) owner
  */
 sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource,
-			      sc_bool_t isPrimary, sc_faddr_t address);
+	sc_bool_t isPrimary, sc_faddr_t address);
 
 /*!
  * This function requests the power mode configuration for system-level
@@ -420,9 +441,7 @@
  *
  */
 sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
-				     sc_pm_sys_if_t sys_if,
-				     sc_pm_power_mode_t hpm,
-				     sc_pm_power_mode_t lpm);
+	sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm);
 
 /* @} */
 
@@ -451,7 +470,7 @@
  * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values.
  */
 sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
-			      sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
+	sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
 
 /*!
  * This function gets the rate of a resource's clock/PLL.
@@ -472,7 +491,7 @@
  * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values.
  */
 sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
-			      sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
+	sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
 
 /*!
  * This function enables/disables a resource's clock.
@@ -500,7 +519,7 @@
  * Refer to the [Clock List](@ref CLOCKS) for valid clock values.
  */
 sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
-			    sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
+	sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
 
 /*!
  * This function sets the parent of a resource's clock.
@@ -524,7 +543,7 @@
  * Refer to the [Clock List](@ref CLOCKS) for valid clock values.
  */
 sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
-				sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
+	sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
 
 /*!
  * This function gets the parent of a resource's clock.
@@ -545,7 +564,7 @@
  * Refer to the [Clock List](@ref CLOCKS) for valid clock values.
  */
 sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
-				sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
+	sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
 
 /* @} */
 
@@ -556,7 +575,8 @@
 
 /*!
  * This function is used to reset the system. Only the owner of the
- * SC_R_SYSTEM resource can do this.
+ * SC_R_SYSTEM resource or a partition with access permissions to
+ * SC_R_SYSTEM can do this.
  *
  * @param[in]     ipc         IPC handle
  * @param[in]     type        reset type
@@ -565,7 +585,7 @@
  *
  * Return errors:
  * - SC_ERR_PARM if invalid type,
- * - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM
+ * - SC_ERR_NOACCESS if caller cannot access SC_R_SYSTEM
  *
  * If this function returns, then the reset did not occur due to an
  * invalid parameter.
@@ -576,13 +596,38 @@
  * This function gets a caller's reset reason.
  *
  * @param[in]     ipc         IPC handle
- * @param[out]    reason      pointer to return reset reason
+ * @param[out]    reason      pointer to return the reset reason
+ *
+ * This function returns the reason a partition was reset. If the reason
+ * is POR, then the system reset reason will be returned.
+ *
+ * Note depending on the connection of the WDOG_OUT signal and the OTP
+ * programming of the PMIC, some resets may trigger a system POR
+ * and the original reason will be lost.
  *
  * @return Returns an error code (SC_ERR_NONE = success).
  */
 sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason);
 
 /*!
+ * This function gets the partition that caused a reset.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    pt          pointer to return the resetting partition
+ *
+ * If the reset reason obtained via sc_pm_reset_reason() is POR then the
+ * result from this function will be 0. Some SECO causes of reset will
+ * also return 0.
+ *
+ * Note depending on the connection of the WDOG_OUT signal and the OTP
+ * programming of the PMIC, some resets may trigger a system POR
+ * and the partition info will be lost.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_pm_get_reset_part(sc_ipc_t ipc, sc_rm_pt_t *pt);
+
+/*!
  * This function is used to boot a partition.
  *
  * @param[in]     ipc          IPC handle
@@ -598,10 +643,14 @@
  * - SC_ERR_PARM if invalid partition, resource, or addr,
  * - SC_ERR_NOACCESS if caller's partition is not the parent of the
  *   partition to boot
+ *
+ * This must be used to boot a partition. Only a partition booted this
+ * way can be rebooted using the watchdog, sc_pm_boot() or
+ * sc_pm_reboot_partition().
  */
 sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
-		    sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
-		    sc_rsrc_t resource_mu, sc_rsrc_t resource_dev);
+	sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
+	sc_rsrc_t resource_mu, sc_rsrc_t resource_dev);
 
 /*!
  * This function is used to reboot the caller's partition.
@@ -614,12 +663,8 @@
  * power, clocks, etc.) is reset. The boot SW of the booting CPU must be
  * able to handle peripherals that that are not reset.
  *
- * If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset.
- * SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW
- * of the booting CPU must be able to handle peripherals and SC state that
- * that are not reset.
- *
- * If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action.
+ * If \a type is SC_PM_RESET_TYPE_WARM or SC_PM_RESET_TYPE_BOARD, then
+ * returns SC_ERR_PARM as these are not supported.
  *
  * If this function returns, then the reset did not occur due to an
  * invalid parameter.
@@ -638,26 +683,40 @@
  * power, clocks, etc.) is reset. The boot SW of the booting CPU must be
  * able to handle peripherals that that are not reset.
  *
- * If \a type is SC_PM_RESET_TYPE_WARM, then only the boot CPU is reset.
- * SC state (partitions, power, clocks, etc.) are NOT reset. The boot SW
- * of the booting CPU must be able to handle peripherals and SC state that
- * that are not reset.
- *
- * If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action.
+ * If \a type is SC_PM_RESET_TYPE_WARM or SC_PM_RESET_TYPE_BOARD, then
+ * returns SC_ERR_PARM as these are not supported.
  *
  * @return Returns an error code (SC_ERR_NONE = success).
  *
  * Return errors:
  * - SC_ERR_PARM if invalid partition or type
- * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
+ * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt
+ *   and the caller does not have access to SC_R_SYSTEM
  *
  * Most peripherals owned by the partition will be reset if
  * possible. SC state (partitions, power, clocks, etc.) is reset. The
  * boot SW of the booting CPU must be able to handle peripherals that
  * that are not reset.
+ *
+ * If board_reboot_part() returns a non-0 mask, then the reboot will
+ * be delayed until all partitions indicated in the mask have called
+ * sc_pm_reboot_continue() to continue the boot.
  */
 sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
-				sc_pm_reset_type_t type);
+	sc_pm_reset_type_t type);
+
+/*!
+ * This function is used to continue the reboot a partition.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to continue
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_PARM if invalid partition
+ */
+sc_err_t sc_pm_reboot_continue(sc_ipc_t ipc, sc_rm_pt_t pt);
 
 /*!
  * This function is used to start/stop a CPU.
@@ -673,12 +732,55 @@
  * - SC_ERR_PARM if invalid resource or address,
  * - SC_ERR_NOACCESS if caller's partition is not the parent of the
  *   resource (CPU) owner
+ *
+ * This function is usually used to start a secondar CPU in the
+ * same partition as the caller.  It is not used to start the first
+ * CPU in a dedicated partition.  That would be started by calling
+ * sc_pm_boot().
+ *
+ * A CPU started with sc_pm_cpu_start() will not restart as a result
+ * of a watchdog event or calling sc_pm_reboot() or sc_pm_reboot_partition().
+ * Those will reboot that partition which will start the CPU started with
+ * sc_pm_boot().
  */
 sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
-			 sc_faddr_t address);
+	sc_faddr_t address);
+
+/*!
+ * This function is used to reset a CPU.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    ID of the CPU resource
+ * @param[in]     address     64-bit boot address
+ *
+ * This function does not return anything as the calling core may have been
+ * reset. It can still fail if the resource or address is invalid. It can also
+ * fail if the caller's partition is not the owner of the CPU, not the parent
+ * of the CPU resource owner, or has access to SC_R_SYSTEM. Will also fail if
+ * the resource is not powered on. No indication of failure is returned.
+ *
+ * Note this just resets the CPU. None of the peripherals or bus fabric used by
+ * the CPU is reset. State configured in the SCFW is not reset. The SW running
+ * on the core has to understand and deal with this.
+ */
+void sc_pm_cpu_reset(sc_ipc_t ipc, sc_rsrc_t resource, sc_faddr_t address);
+
+/*!
+ * This function returns a bool indicating if a partition was started.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     pt          handle of partition to check
+ *
+ * @return Returns a bool (SC_TRUE = started).
+ *
+ * Note this indicates if a partition was started. It does not indicate if a
+ * partition is currently running or in a low power state.
+ */
+sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt);
 
 /* @} */
 
-#endif				/* SC_PM_API_H */
+#endif /* SC_PM_API_H */
 
 /**@}*/
+
diff --git a/plat/imx/common/include/sci/svc/rm/sci_rm_api.h b/plat/imx/common/include/sci/svc/rm/sci_rm_api.h
index 012d919..6d5ab8b 100644
--- a/plat/imx/common/include/sci/svc/rm/sci_rm_api.h
+++ b/plat/imx/common/include/sci/svc/rm/sci_rm_api.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -31,44 +32,44 @@
  * @name Defines for type widths
  */
 /*@{*/
-#define SC_RM_PARTITION_W   5	/* Width of sc_rm_pt_t */
-#define SC_RM_MEMREG_W      6	/* Width of sc_rm_mr_t */
-#define SC_RM_DID_W         4	/* Width of sc_rm_did_t */
-#define SC_RM_SID_W         6	/* Width of sc_rm_sid_t */
-#define SC_RM_SPA_W         2	/* Width of sc_rm_spa_t */
-#define SC_RM_PERM_W        3	/* Width of sc_rm_perm_t */
+#define SC_RM_PARTITION_W   5U      /* Width of sc_rm_pt_t */
+#define SC_RM_MEMREG_W      6U      /* Width of sc_rm_mr_t */
+#define SC_RM_DID_W         4U      /* Width of sc_rm_did_t */
+#define SC_RM_SID_W         6U      /* Width of sc_rm_sid_t */
+#define SC_RM_SPA_W         2U      /* Width of sc_rm_spa_t */
+#define SC_RM_PERM_W        3U      /* Width of sc_rm_perm_t */
 /*@}*/
 
 /*!
  * @name Defines for ALL parameters
  */
 /*@{*/
-#define SC_RM_PT_ALL        ((sc_rm_pt_t) UINT8_MAX)	/* All partitions */
-#define SC_RM_MR_ALL        ((sc_rm_mr_t) UINT8_MAX)	/* All memory regions */
+#define SC_RM_PT_ALL        ((sc_rm_pt_t) UINT8_MAX)   /* All partitions */
+#define SC_RM_MR_ALL        ((sc_rm_mr_t) UINT8_MAX)   /* All memory regions */
 /*@}*/
 
 /*!
  * @name Defines for sc_rm_spa_t
  */
 /*@{*/
-#define SC_RM_SPA_PASSTHRU  0U	/* Pass through (attribute driven by master) */
-#define SC_RM_SPA_PASSSID   1U	/* Pass through and output on SID */
-#define SC_RM_SPA_ASSERT    2U	/* Assert (force to be secure/privileged) */
-#define SC_RM_SPA_NEGATE    3U	/* Negate (force to be non-secure/user) */
+#define SC_RM_SPA_PASSTHRU  0U   /* Pass through (attribute driven by master) */
+#define SC_RM_SPA_PASSSID   1U   /* Pass through and output on SID */
+#define SC_RM_SPA_ASSERT    2U   /* Assert (force to be secure/privileged) */
+#define SC_RM_SPA_NEGATE    3U   /* Negate (force to be non-secure/user) */
 /*@}*/
 
 /*!
  * @name Defines for sc_rm_perm_t
  */
 /*@{*/
-#define SC_RM_PERM_NONE         0U	/* No access */
-#define SC_RM_PERM_SEC_R        1U	/* Secure RO */
-#define SC_RM_PERM_SECPRIV_RW   2U	/* Secure privilege R/W */
-#define SC_RM_PERM_SEC_RW       3U	/* Secure R/W */
-#define SC_RM_PERM_NSPRIV_R     4U	/* Secure R/W, non-secure privilege RO */
-#define SC_RM_PERM_NS_R         5U	/* Secure R/W, non-secure RO */
-#define SC_RM_PERM_NSPRIV_RW    6U	/* Secure R/W, non-secure privilege R/W */
-#define SC_RM_PERM_FULL         7U	/* Full access */
+#define SC_RM_PERM_NONE         0U   /* No access */
+#define SC_RM_PERM_SEC_R        1U   /* Secure RO */
+#define SC_RM_PERM_SECPRIV_RW   2U   /* Secure privilege R/W */
+#define SC_RM_PERM_SEC_RW       3U   /* Secure R/W */
+#define SC_RM_PERM_NSPRIV_R     4U   /* Secure R/W, non-secure privilege RO */
+#define SC_RM_PERM_NS_R         5U   /* Secure R/W, non-secure RO */
+#define SC_RM_PERM_NSPRIV_RW    6U   /* Secure R/W, non-secure privilege R/W */
+#define SC_RM_PERM_FULL         7U   /* Full access */
 /*@}*/
 
 /* Types */
@@ -147,8 +148,7 @@
  * controls of that master.
  */
 sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
-			       sc_bool_t isolated, sc_bool_t restricted,
-			       sc_bool_t grant, sc_bool_t coherent);
+	sc_bool_t isolated, sc_bool_t restricted, sc_bool_t grant, sc_bool_t coherent);
 
 /*!
  * This function makes a partition confidential.
@@ -223,7 +223,8 @@
  * Assumes no assigned resources or memory regions yet! The number of static
  * DID is fixed by the SC at boot.
  */
-sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_did_t did);
+sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt,
+	sc_rm_did_t did);
 
 /*!
  * This function locks a partition.
@@ -268,7 +269,8 @@
  * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
  * - SC_ERR_LOCKED if either partition is locked
  */
-sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent);
+sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt,
+	sc_rm_pt_t pt_parent);
 
 /*!
  * This function moves all movable resources/pads owned by a source partition
@@ -298,7 +300,7 @@
  * - SC_ERR_LOCKED if either partition is locked
  */
 sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
-			sc_bool_t move_rsrc, sc_bool_t move_pads);
+	sc_bool_t move_rsrc, sc_bool_t move_pads);
 
 /* @} */
 
@@ -322,7 +324,7 @@
  * ASSERT if the partition si secure and NEGATE if it is not, and
  * masters will defaulted to SMMU bypass. Access permissions will reset
  * to SEC_RW for the owning partition only for secure partitions, FULL for
- * non-secure. DEfault is no access by other partitions.
+ * non-secure. Default is no access by other partitions.
  *
  * Return errors:
  * - SC_ERR_NOACCESS if caller's partition is restricted,
@@ -331,7 +333,8 @@
  *   of the owner,
  * - SC_ERR_LOCKED if the owning partition or \a pt is locked
  */
-sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource);
+sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt,
+	sc_rsrc_t resource);
 
 /*!
  * This function flags resources as movable or not.
@@ -354,7 +357,7 @@
  * resources from moving.
  */
 sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
-				    sc_rsrc_t resource_lst, sc_bool_t movable);
+	sc_rsrc_t resource_lst, sc_bool_t movable);
 
 /*!
  * This function flags all of a subsystem's resources as movable
@@ -373,7 +376,7 @@
  * resources owned by the caller are set.
  */
 sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
-				       sc_bool_t movable);
+	sc_bool_t movable);
 
 /*!
  * This function sets attributes for a resource which is a bus master (i.e.
@@ -398,8 +401,7 @@
  * changed if the caller's partition is secure.
  */
 sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource,
-				     sc_rm_spa_t sa, sc_rm_spa_t pa,
-				     sc_bool_t smmu_bypass);
+	sc_rm_spa_t sa, sc_rm_spa_t pa, sc_bool_t smmu_bypass);
 
 /*!
  * This function sets the StreamID for a resource which is a bus master (i.e.
@@ -423,7 +425,7 @@
  * bypass.
  */
 sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource,
-			      sc_rm_sid_t sid);
+	sc_rm_sid_t sid);
 
 /*!
  * This function sets access permissions for a peripheral resource.
@@ -443,10 +445,11 @@
  * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt
  *
  * This function configures how the HW isolation will restrict access to a
- * peripheral based on the attributes of a transaction from bus master.
+ * peripheral based on the attributes of a transaction from bus master. It
+ * also allows the access permissions of SC_R_SYSTEM to be set.
  */
 sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
-					  sc_rm_pt_t pt, sc_rm_perm_t perm);
+	sc_rm_pt_t pt, sc_rm_perm_t perm);
 
 /*!
  * This function gets ownership status of a resource.
@@ -461,6 +464,23 @@
 sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
 
 /*!
+ * This function is used to get the owner of a resource.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     resource    resource to check
+ * @param[out]    pt          pointer to return owning partition
+ *
+ * @return Returns a boolean (SC_TRUE if the resource is a bus master).
+ *
+ * Return errors:
+ * - SC_PARM if arguments out of range or invalid
+ *
+ * If \a resource is out of range then SC_ERR_PARM is returned.
+ */
+sc_err_t sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource,
+	sc_rm_pt_t *pt);
+
+/*!
  * This function is used to test if a resource is a bus master.
  *
  * @param[in]     ipc         IPC handle
@@ -497,7 +517,7 @@
  * - SC_PARM if \a resource is out of range
  */
 sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource,
-				 sc_rm_sid_t *sid);
+	sc_rm_sid_t *sid);
 
 /* @} */
 
@@ -532,7 +552,7 @@
  * caller to access.
  */
 sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr,
-			    sc_faddr_t addr_start, sc_faddr_t addr_end);
+	sc_faddr_t addr_start, sc_faddr_t addr_end);
 
 /*!
  * This function requests that the SC split a memory region.
@@ -559,8 +579,33 @@
  * Note the new region must start or end on the split region.
  */
 sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr,
-			    sc_rm_mr_t *mr_ret, sc_faddr_t addr_start,
-			    sc_faddr_t addr_end);
+	sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end);
+
+/*!
+ * This function requests that the SC fragment a memory region.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    mr_ret      return handle for new region; used for
+ *                            subsequent function calls
+ *                            associated with this region
+ * @param[in]     addr_start  start address of region (physical)
+ * @param[in]     addr_end    end address of region (physical)
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors:
+ * - SC_ERR_LOCKED if caller's partition is locked,
+ * - SC_ERR_PARM if the new memory region spans multiple existing regions,
+ * - SC_ERR_NOACCESS if caller's partition does not own the memory containing
+ *   the new region,
+ * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation
+ *   space)
+ *
+ * This function finds the memory region containing the address range.
+ * It then splits it as required and returns the extracted region.
+ */
+sc_err_t sc_rm_memreg_frag(sc_ipc_t ipc, sc_rm_mr_t *mr_ret,
+	sc_faddr_t addr_start, sc_faddr_t addr_end);
 
 /*!
  * This function frees a memory region.
@@ -601,7 +646,7 @@
  * region containing the range specified.
  */
 sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr,
-			   sc_faddr_t addr_start, sc_faddr_t addr_end);
+	sc_faddr_t addr_start, sc_faddr_t addr_end);
 
 /*!
  * This function assigns ownership of a memory region.
@@ -644,7 +689,7 @@
  * memory region based on the attributes of a transaction from bus master.
  */
 sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
-				      sc_rm_pt_t pt, sc_rm_perm_t perm);
+	sc_rm_pt_t pt, sc_rm_perm_t perm);
 
 /*!
  * This function gets ownership status of a memory region.
@@ -673,7 +718,7 @@
  * - SC_PARM if \a mr is out of range
  */
 sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr,
-			       sc_faddr_t *addr_start, sc_faddr_t *addr_end);
+	sc_faddr_t *addr_start, sc_faddr_t *addr_end);
 
 /* @} */
 
@@ -722,7 +767,7 @@
  * pads from moving.
  */
 sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
-			       sc_pad_t pad_lst, sc_bool_t movable);
+	sc_pad_t pad_lst, sc_bool_t movable);
 
 /*!
  * This function gets ownership status of a pad.
@@ -752,6 +797,7 @@
 
 /* @} */
 
-#endif				/* SC_RM_API_H */
+#endif /* SC_RM_API_H */
 
 /**@}*/
+
diff --git a/plat/imx/common/include/sci/svc/seco/sci_seco_api.h b/plat/imx/common/include/sci/svc/seco/sci_seco_api.h
new file mode 100644
index 0000000..2ebd922
--- /dev/null
+++ b/plat/imx/common/include/sci/svc/seco/sci_seco_api.h
@@ -0,0 +1,512 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*!
+ * Header file containing the public API for the System Controller (SC)
+ * Security (SECO) function.
+ *
+ * @addtogroup SECO_SVC (SVC) Security Service
+ *
+ * Module for the Security (SECO) service.
+ *
+ * @{
+ */
+
+#ifndef SC_SECO_API_H
+#define SC_SECO_API_H
+
+/* Includes */
+
+#include <sci/sci_types.h>
+#include <sci/svc/rm/sci_rm_api.h>
+
+/* Defines */
+
+/*!
+ * @name Defines for sc_seco_auth_cmd_t
+ */
+/*@{*/
+#define SC_SECO_AUTH_CONTAINER          0U   /* Authenticate container */
+#define SC_SECO_VERIFY_IMAGE            1U   /* Verify image */
+#define SC_SECO_REL_CONTAINER           2U   /* Release container */
+#define SC_SECO_AUTH_SECO_FW            3U   /* SECO Firmware */
+#define SC_SECO_AUTH_HDMI_TX_FW         4U   /* HDMI TX Firmware */
+#define SC_SECO_AUTH_HDMI_RX_FW         5U   /* HDMI RX Firmware */
+/*@}*/
+
+/* Types */
+
+/*!
+ * This type is used to issue SECO authenticate commands.
+ */
+typedef uint8_t sc_seco_auth_cmd_t;
+
+/* Functions */
+
+/*!
+ * @name Image Functions
+ * @{
+ */
+
+/*!
+ * This function loads a SECO image.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     addr_src    address of image source
+ * @param[in]     addr_dst    address of image destination
+ * @param[in]     len         lenth of image to load
+ * @param[in]     fw          SC_TRUE = firmware load
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if word fuse index param out of range or invalid
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * This is used to load images via the SECO. Examples include SECO
+ * Firmware and IVT/CSF data used for authentication. These are usually
+ * loaded into SECO TCM. \a addr_src is in secure memory.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src,
+	sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw);
+
+/*!
+ * This function is used to authenticate a SECO image or command.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     cmd         authenticate command
+ * @param[in]     addr        address of/or metadata
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if word fuse index param out of range or invalid
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * This is used to authenticate a SECO image or issue a security
+ * command. \a addr often points to an container. It is also
+ * just data (or even unused) for some commands.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_seco_authenticate(sc_ipc_t ipc,
+	sc_seco_auth_cmd_t cmd, sc_faddr_t addr);
+
+/* @} */
+
+/*!
+ * @name Lifecycle Functions
+ * @{
+ */
+
+/*!
+ * This function updates the lifecycle of the device.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     change      desired lifecycle transistion
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * This message is used for going from Open to NXP Closed to OEM Closed.
+ * Note \a change is NOT the new desired lifecycle. It is a lifecycle
+ * transition as documented in the Security Reference Manual (SRM).
+ *
+ * If any SECO request fails or only succeeds because the part is in an
+ * "OEM open" lifecycle, then a request to transition from "NXP closed"
+ * to "OEM closed" will also fail. For example, booting a signed container
+ * when the OEM SRK is not fused will succeed, but as it is an abnormal
+ * situation, a subsequent request to transition the lifecycle will return
+ * an error.
+ */
+sc_err_t sc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t change);
+
+/*!
+ * This function updates the lifecycle to one of the return lifecycles.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     addr        address of message block
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * Note \a addr must be a pointer to a signed message block.
+ *
+ * To switch back to NXP states (Full Field Return), message must be signed
+ * by NXP SRK. For OEM States (Partial Field Return), must be signed by OEM
+ * SRK.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr);
+
+/*!
+ * This function is used to commit into the fuses any new SRK revocation
+ * and FW version information that have been found in the primary and
+ * secondary containers.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in,out] info        pointer to information type to be committed
+ *
+ * The return \a info will contain what was actually committed.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if \a info is invalid
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ */
+sc_err_t sc_seco_commit(sc_ipc_t ipc, uint32_t *info);
+
+/* @} */
+
+/*!
+ * @name Attestation Functions
+ * @{
+ */
+
+/*!
+ * This function is used to set the attestation mode. Only the owner of
+ * the SC_R_ATTESTATION resource may make this call.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     mode        mode
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if \a mode is invalid
+ * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * This is used to set the SECO attestation mode. This can be prover
+ * or verfier. See the Security Reference Manual (SRM) for more on the
+ * suported modes, mode values, and mode behavior.
+ */
+sc_err_t sc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode);
+
+/*!
+ * This function is used to request atestation. Only the owner of
+ * the SC_R_ATTESTATION resource may make this call.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     nonce       unique value
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * This is used to ask SECO to perform an attestation. The result depends
+ * on the attestation mode. After this call, the signature can be
+ * requested or a verify can be requested.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_seco_attest(sc_ipc_t ipc, uint64_t nonce);
+
+/*!
+ * This function is used to retrieve the attestation public key.
+ * Mode must be verifier. Only the owner of the SC_R_ATTESTATION resource
+ * may make this call.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     addr        address to write response
+ *
+ * Result will be written to \a addr. The \a addr parmater must point
+ * to an address SECO can access. It must be 64-bit aligned. There
+ * should be 96 bytes of space.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if \a addr bad or attestation has not been requested
+ * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_seco_get_attest_pkey(sc_ipc_t ipc, sc_faddr_t addr);
+
+/*!
+ * This function is used to retrieve attestation signature and parameters.
+ * Mode must be provider. Only the owner of the SC_R_ATTESTATION resource
+ * may make this call.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     addr        address to write response
+ *
+ * Result will be written to \a addr. The \a addr parmater must point
+ * to an address SECO can access. It must be 64-bit aligned. There
+ * should be 120 bytes of space.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if \a addr bad or attestation has not been requested
+ * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_seco_get_attest_sign(sc_ipc_t ipc, sc_faddr_t addr);
+
+/*!
+ * This function is used to verify attestation. Mode must be verifier.
+ * Only the owner of the SC_R_ATTESTATION resource may make this call.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     addr        address of signature
+ *
+ * The \a addr parmater must point to an address SECO can access. It must be
+ * 64-bit aligned.
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if \a addr bad or attestation has not been requested
+ * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ * - SC_ERR_FAIL if signature doesn't match
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_seco_attest_verify(sc_ipc_t ipc, sc_faddr_t addr);
+
+/* @} */
+
+/*!
+ * @name Key Functions
+ * @{
+ */
+
+/*!
+ * This function is used to generate a SECO key blob.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     id          key identifier
+ * @param[in]     load_addr   load address
+ * @param[in]     export_addr export address
+ * @param[in]     max_size    max export size
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if word fuse index param out of range or invalid
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * This function is used to encapsulate sensitive keys in a specific structure
+ * called a blob, which provides both confidentiality and integrity protection.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_seco_gen_key_blob(sc_ipc_t ipc, uint32_t id,
+	sc_faddr_t load_addr, sc_faddr_t export_addr, uint16_t max_size);
+
+/*!
+ * This function is used to load a SECO key.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     id          key identifier
+ * @param[in]     addr        key address
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if word fuse index param out of range or invalid
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * This function is used to install private cryptographic keys encapsulated
+ * in a blob previously generated by SECO. The controller can be either the
+ * IEE or the VPU. The blob header carries the controller type and the key
+ * size, as provided by the user when generating the key blob.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_seco_load_key(sc_ipc_t ipc, uint32_t id,
+	sc_faddr_t addr);
+
+/* @} */
+
+/*!
+ * @name Manufacturing Protection Functions
+ * @{
+ */
+
+/*!
+ * This function is used to get the manufacturing protection public key.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     dst_addr    destination address
+ * @param[in]     dst_size    destination size
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if word fuse index param out of range or invalid
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * This function is supported only in OEM-closed lifecycle. It generates
+ * the mfg public key and stores it in a specific location in the secure
+ * memory.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr,
+	uint16_t dst_size);
+
+/*!
+ * This function is used to update the manufacturing protection message
+ * register.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     addr        data address
+ * @param[in]     size        size
+ * @param[in]     lock        lock_reg
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if word fuse index param out of range or invalid
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * This function is supported only in OEM-closed lifecycle. It updates the
+ * content of the MPMR (Manufacturing Protection Message register of 256
+ * bits). This register will be appended to the input-data message when
+ * generating the signature. Please refer to the CAAM block guide for details.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr,
+	uint8_t size, uint8_t lock);
+
+/*!
+ * This function is used to get the manufacturing protection signature.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     msg_addr    message address
+ * @param[in]     msg_size    message size
+ * @param[in]     dst_addr    destination address
+ * @param[in]     dst_size    destination size
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_PARM if word fuse index param out of range or invalid
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * This function is used to generate an ECDSA signature for an input-data
+ * message and to store it in a specific location in the secure memory. It
+ * is only supported in OEM-closed lifecycle. In order to get the ECDSA
+ * signature, the RNG must be initialized. In case it has not been started
+ * an error will be returned.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
+	uint16_t msg_size, sc_faddr_t dst_addr, uint16_t dst_size);
+
+/* @} */
+
+/*!
+ * @name Debug Functions
+ * @{
+ */
+
+/*!
+ * This function is used to return the SECO FW build info.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    version     pointer to return build number
+ * @param[out]    commit      pointer to return commit ID (git SHA-1)
+ */
+void sc_seco_build_info(sc_ipc_t ipc, uint32_t *version,
+	uint32_t *commit);
+
+/*!
+ * This function is used to return SECO chip info.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    lc          pointer to return lifecycle
+ * @param[out]    monotonic   pointer to return monotonic counter
+ * @param[out]    uid_l       pointer to return UID (lower 32 bits)
+ * @param[out]    uid_h       pointer to return UID (upper 32 bits)
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ */
+sc_err_t sc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc,
+	uint16_t *monotonic, uint32_t *uid_l, uint32_t *uid_h);
+
+/*!
+ * This function securely enables debug.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     addr        address of message block
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * Note \a addr must be a pointer to a signed message block.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr);
+
+/*!
+ * This function is used to return an event from the SECO error log.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[out]    idx         index of event to return
+ * @param[out]    event       pointer to return event
+ *
+ * @return Returns an error code (SC_ERR_NONE = success).
+ *
+ * Read of \a idx 0 captures events from SECO. Loop starting
+ * with 0 until an error is returned to dump all events.
+ */
+sc_err_t sc_seco_get_event(sc_ipc_t ipc, uint8_t idx,
+	uint32_t *event);
+
+/* @} */
+
+/*!
+ * @name Miscellaneous Functions
+ * @{
+ */
+
+/*!
+ * This function securely writes a group of fuse words.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     addr        address of message block
+ *
+ * @return Returns and error code (SC_ERR_NONE = success).
+ *
+ * Return errors codes:
+ * - SC_ERR_UNAVAILABLE if SECO not available
+ *
+ * Note \a addr must be a pointer to a signed message block.
+ *
+ * See the Security Reference Manual (SRM) for more info.
+ */
+sc_err_t sc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr);
+
+/* @} */
+
+#endif /* SC_SECO_API_H */
+
+/**@}*/
+
diff --git a/plat/imx/common/include/sci/svc/timer/sci_timer_api.h b/plat/imx/common/include/sci/svc/timer/sci_timer_api.h
index 05e3382..29050f5 100644
--- a/plat/imx/common/include/sci/svc/timer/sci_timer_api.h
+++ b/plat/imx/common/include/sci/svc/timer/sci_timer_api.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -24,6 +24,7 @@
 /* Includes */
 
 #include <sci/sci_types.h>
+#include <sci/svc/rm/sci_rm_api.h>
 
 /* Defines */
 
@@ -31,18 +32,18 @@
  * @name Defines for type widths
  */
 /*@{*/
-#define SC_TIMER_ACTION_W   3U	/* Width of sc_timer_wdog_action_t */
+#define SC_TIMER_ACTION_W   3U      /* Width of sc_timer_wdog_action_t */
 /*@}*/
 
 /*!
  * @name Defines for sc_timer_wdog_action_t
  */
 /*@{*/
-#define SC_TIMER_WDOG_ACTION_PARTITION      0U	/* Reset partition */
-#define SC_TIMER_WDOG_ACTION_WARM           1U	/* Warm reset system */
-#define SC_TIMER_WDOG_ACTION_COLD           2U	/* Cold reset system */
-#define SC_TIMER_WDOG_ACTION_BOARD          3U	/* Reset board */
-#define SC_TIMER_WDOG_ACTION_IRQ            4U	/* Only generate IRQs */
+#define SC_TIMER_WDOG_ACTION_PARTITION      0U   /* Reset partition */
+#define SC_TIMER_WDOG_ACTION_WARM           1U   /* Warm reset system */
+#define SC_TIMER_WDOG_ACTION_COLD           2U   /* Cold reset system */
+#define SC_TIMER_WDOG_ACTION_BOARD          3U   /* Reset board */
+#define SC_TIMER_WDOG_ACTION_IRQ            4U   /* Only generate IRQs */
 /*@}*/
 
 /* Types */
@@ -75,7 +76,8 @@
  * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED
  *         = locked).
  */
-sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, sc_timer_wdog_time_t timeout);
+sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc,
+	sc_timer_wdog_time_t timeout);
 
 /*!
  * This function sets the watchdog pre-timeout in milliseconds. If not
@@ -92,7 +94,7 @@
  * @return Returns an error code (SC_ERR_NONE = success).
  */
 sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc,
-				       sc_timer_wdog_time_t pre_timeout);
+	sc_timer_wdog_time_t pre_timeout);
 
 /*!
  * This function starts the watchdog.
@@ -140,9 +142,8 @@
  * @return Returns an error code (SC_ERR_NONE = success).
  */
 sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc,
-				  sc_timer_wdog_time_t *timeout,
-				  sc_timer_wdog_time_t *max_timeout,
-				  sc_timer_wdog_time_t *remaining_time);
+	sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout,
+	sc_timer_wdog_time_t *remaining_time);
 
 /*!
  * This function gets the status of the watchdog of a partition. All
@@ -157,10 +158,8 @@
  *
  * @return Returns an error code (SC_ERR_NONE = success).
  */
-sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt,
-				     sc_bool_t *enb,
-				     sc_timer_wdog_time_t *timeout,
-				     sc_timer_wdog_time_t *remaining_time);
+sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t *enb,
+	sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *remaining_time);
 
 /*!
  * This function configures the action to be taken when a watchdog
@@ -180,7 +179,7 @@
  * - SC_ERR_LOCKED if the watchdog is locked
  */
 sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc,
-				  sc_rm_pt_t pt, sc_timer_wdog_action_t action);
+	sc_rm_pt_t pt, sc_timer_wdog_action_t action);
 
 /* @} */
 
@@ -191,7 +190,8 @@
 
 /*!
  * This function sets the RTC time. Only the owner of the SC_R_SYSTEM
- * resource can set the time.
+ * resource or a partition with access permissions to SC_R_SYSTEM can
+ * set the time.
  *
  * @param[in]     ipc         IPC handle
  * @param[in]     year        year (min 1970)
@@ -205,11 +205,10 @@
  *
  * Return errors:
  * - SC_ERR_PARM if invalid time/date parameters,
- * - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner
+ * - SC_ERR_NOACCESS if caller's partition cannot access SC_R_SYSTEM
  */
 sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon,
-			       uint8_t day, uint8_t hour, uint8_t min,
-			       uint8_t sec);
+	uint8_t day, uint8_t hour, uint8_t min, uint8_t sec);
 
 /*!
  * This function gets the RTC time.
@@ -225,8 +224,7 @@
  * @return Returns an error code (SC_ERR_NONE = success).
  */
 sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon,
-			       uint8_t *day, uint8_t *hour, uint8_t *min,
-			       uint8_t *sec);
+	uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec);
 
 /*!
  * This function gets the RTC time in seconds since 1/1/1970.
@@ -249,7 +247,8 @@
  * @param[in]     min         minute (0-59)
  * @param[in]     sec         second (0-59)
  *
- * Note this alarm setting clears when the alarm is triggered.
+ * Note this alarm setting clears when the alarm is triggered. This is an
+ * absolute time.
  *
  * @return Returns an error code (SC_ERR_NONE = success).
  *
@@ -257,8 +256,7 @@
  * - SC_ERR_PARM if invalid time/date parameters
  */
 sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon,
-				uint8_t day, uint8_t hour, uint8_t min,
-				uint8_t sec);
+	uint8_t day, uint8_t hour, uint8_t min, uint8_t sec);
 
 /*!
  * This function sets the RTC alarm (periodic mode).
@@ -268,6 +266,8 @@
  *
  * @return Returns an error code (SC_ERR_NONE = success).
  *
+ * Note this is a relative time.
+ *
  * Return errors:
  * - SC_ERR_PARM if invalid time/date parameters
  */
@@ -289,7 +289,8 @@
 
 /*!
  * This function sets the RTC calibration value. Only the owner of the SC_R_SYSTEM
- * resource can set the calibration.
+ * resource or a partition with access permissions to SC_R_SYSTEM can set the
+ * calibration.
  *
  * @param[in]     ipc         IPC handle
  * @param[in]     count       calbration count (-16 to 15)
@@ -315,7 +316,8 @@
  * @param[in]     ipc         IPC handle
  * @param[in]     ticks       number of 8MHz cycles
  *
- * Note this alarm setting clears when the alarm is triggered.
+ * Note the \a ticks parameter is an absolute time. This alarm
+ * setting clears when the alarm is triggered.
  *
  * @return Returns an error code (SC_ERR_NONE = success).
  *
@@ -330,12 +332,15 @@
  * @param[in]     ipc          IPC handle
  * @param[in]     ticks        number of 8MHz cycles
  *
+ * Note the \a ticks parameter is a relative time.
+ *
  * @return Returns an error code (SC_ERR_NONE = success).
  *
  * Return errors:
  * - SC_ERR_PARM if invalid time/date parameters
  */
-sc_err_t sc_timer_set_sysctr_periodic_alarm(sc_ipc_t ipc, uint64_t ticks);
+sc_err_t sc_timer_set_sysctr_periodic_alarm(sc_ipc_t ipc,
+	uint64_t ticks);
 
 /*!
  * This function cancels the SYSCTR alarm.
@@ -353,6 +358,7 @@
 
 /* @} */
 
-#endif				/* SC_TIMER_API_H */
+#endif /* SC_TIMER_API_H */
 
 /**@}*/
+
diff --git a/plat/imx/common/sci/ipc.c b/plat/imx/common/sci/ipc.c
index 2af2567..68b0b8e 100644
--- a/plat/imx/common/sci/ipc.c
+++ b/plat/imx/common/sci/ipc.c
@@ -1,22 +1,23 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <bakery_lock.h>
 #include <sci/sci_scfw.h>
 #include <sci/sci_ipc.h>
 #include <sci/sci_rpc.h>
 #include <stdlib.h>
+
 #include "imx8_mu.h"
 
+#include <bakery_lock.h>
 DEFINE_BAKERY_LOCK(sc_ipc_bakery_lock);
 #define sc_ipc_lock_init()	bakery_lock_init(&sc_ipc_bakery_lock)
 #define sc_ipc_lock()		bakery_lock_get(&sc_ipc_bakery_lock)
 #define sc_ipc_unlock()		bakery_lock_release(&sc_ipc_bakery_lock)
 
-void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp)
+void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, sc_bool_t no_resp)
 {
 	sc_ipc_lock();
 
@@ -88,7 +89,7 @@
 	}
 }
 
-void sc_ipc_write(sc_ipc_t ipc, void *data)
+void sc_ipc_write(sc_ipc_t ipc, const void *data)
 {
 	sc_rpc_msg_t *msg = (sc_rpc_msg_t *) data;
 	uint32_t base = ipc;
diff --git a/plat/imx/common/sci/sci_api.mk b/plat/imx/common/sci/sci_api.mk
index 52d8fab..cf54faf 100644
--- a/plat/imx/common/sci/sci_api.mk
+++ b/plat/imx/common/sci/sci_api.mk
@@ -10,4 +10,6 @@
 			plat/imx/common/sci/svc/pm/pm_rpc_clnt.c	\
 			plat/imx/common/sci/svc/rm/rm_rpc_clnt.c	\
 			plat/imx/common/sci/svc/timer/timer_rpc_clnt.c	\
-			plat/imx/common/sci/svc/misc/misc_rpc_clnt.c
+			plat/imx/common/sci/svc/misc/misc_rpc_clnt.c	\
+			plat/imx/common/sci/svc/irq/irq_rpc_clnt.c	\
+			plat/imx/common/sci/svc/seco/seco_rpc_clnt.c
diff --git a/plat/imx/common/sci/svc/irq/irq_rpc_clnt.c b/plat/imx/common/sci/svc/irq/irq_rpc_clnt.c
new file mode 100644
index 0000000..6c1393f
--- /dev/null
+++ b/plat/imx/common/sci/svc/irq/irq_rpc_clnt.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*!
+ * File containing client-side RPC functions for the IRQ service. These
+ * functions are ported to clients that communicate to the SC.
+ *
+ * @addtogroup IRQ_SVC
+ * @{
+ */
+
+/* Includes */
+
+#include <sci/sci_types.h>
+#include <sci/svc/rm/sci_rm_api.h>
+#include <sci/svc/irq/sci_irq_api.h>
+#include <sci/sci_rpc.h>
+#include "sci_irq_rpc.h"
+#include <stdlib.h>
+
+/* Local Defines */
+
+/* Local Types */
+
+/* Local Functions */
+
+sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource,
+	sc_irq_group_t group, uint32_t mask, sc_bool_t enable)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_IRQ);
+	RPC_FUNC(&msg) = U8(IRQ_FUNC_ENABLE);
+	RPC_U32(&msg, 0U) = U32(mask);
+	RPC_U16(&msg, 4U) = U16(resource);
+	RPC_U8(&msg, 6U) = U8(group);
+	RPC_U8(&msg, 7U) = B2U8(enable);
+	RPC_SIZE(&msg) = 3U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource,
+	sc_irq_group_t group, uint32_t *status)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_IRQ);
+	RPC_FUNC(&msg) = U8(IRQ_FUNC_STATUS);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U8(&msg, 2U) = U8(group);
+	RPC_SIZE(&msg) = 2U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	if (status != NULL)
+	    *status = RPC_U32(&msg, 0U);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+/**@}*/
+
diff --git a/plat/imx/common/sci/svc/irq/sci_irq_rpc.h b/plat/imx/common/sci/svc/irq/sci_irq_rpc.h
new file mode 100644
index 0000000..901e4c1
--- /dev/null
+++ b/plat/imx/common/sci/svc/irq/sci_irq_rpc.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*!
+ * Header file for the IRQ RPC implementation.
+ *
+ * @addtogroup IRQ_SVC
+ * @{
+ */
+
+#ifndef SC_IRQ_RPC_H
+#define SC_IRQ_RPC_H
+
+/* Includes */
+
+/* Defines */
+
+/*!
+ * @name Defines for RPC IRQ function calls
+ */
+/*@{*/
+#define IRQ_FUNC_UNKNOWN 0 /* Unknown function */
+#define IRQ_FUNC_ENABLE 1U /* Index for irq_enable() RPC call */
+#define IRQ_FUNC_STATUS 2U /* Index for irq_status() RPC call */
+/*@}*/
+
+/* Types */
+
+/* Functions */
+
+/*!
+ * This function dispatches an incoming IRQ RPC request.
+ *
+ * @param[in]     caller_pt   caller partition
+ * @param[in]     msg         pointer to RPC message
+ */
+void irq_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg);
+
+#endif /* SC_IRQ_RPC_H */
+
+/**@}*/
+
diff --git a/plat/imx/common/sci/svc/misc/misc_rpc_clnt.c b/plat/imx/common/sci/svc/misc/misc_rpc_clnt.c
index ec1d6b3..2f22ad3 100644
--- a/plat/imx/common/sci/svc/misc/misc_rpc_clnt.c
+++ b/plat/imx/common/sci/svc/misc/misc_rpc_clnt.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,8 +19,8 @@
 #include <sci/svc/rm/sci_rm_api.h>
 #include <sci/svc/misc/sci_misc_api.h>
 #include <sci/sci_rpc.h>
-#include <stdlib.h>
 #include "sci_misc_rpc.h"
+#include <stdlib.h>
 
 /* Local Defines */
 
@@ -29,17 +29,17 @@
 /* Local Functions */
 
 sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
-			     sc_ctrl_t ctrl, uint32_t val)
+	sc_ctrl_t ctrl, uint32_t val)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SET_CONTROL;
-	RPC_U32(&msg, 0U) = (uint32_t)ctrl;
-	RPC_U32(&msg, 4U) = (uint32_t)val;
-	RPC_U16(&msg, 8U) = (uint16_t)resource;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SET_CONTROL);
+	RPC_U32(&msg, 0U) = U32(ctrl);
+	RPC_U32(&msg, 4U) = U32(val);
+	RPC_U16(&msg, 8U) = U16(resource);
 	RPC_SIZE(&msg) = 4U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -49,39 +49,38 @@
 }
 
 sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource,
-			     sc_ctrl_t ctrl, uint32_t *val)
+	sc_ctrl_t ctrl, uint32_t *val)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_GET_CONTROL;
-	RPC_U32(&msg, 0U) = (uint32_t)ctrl;
-	RPC_U16(&msg, 4U) = (uint16_t)resource;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_GET_CONTROL);
+	RPC_U32(&msg, 0U) = U32(ctrl);
+	RPC_U16(&msg, 4U) = U16(resource);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (val != NULL) {
-		*val = RPC_U32(&msg, 0U);
-	}
+	if (val != NULL)
+	    *val = RPC_U32(&msg, 0U);
 
 	result = RPC_R8(&msg);
 	return (sc_err_t)result;
 }
 
 sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt,
-				   sc_misc_dma_group_t max)
+	sc_misc_dma_group_t max)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SET_MAX_DMA_GROUP;
-	RPC_U8(&msg, 0U) = (uint8_t)pt;
-	RPC_U8(&msg, 1U) = (uint8_t)max;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SET_MAX_DMA_GROUP);
+	RPC_U8(&msg, 0U) = U8(pt);
+	RPC_U8(&msg, 1U) = U8(max);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -91,16 +90,16 @@
 }
 
 sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource,
-			       sc_misc_dma_group_t group)
+	sc_misc_dma_group_t group)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SET_DMA_GROUP;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U8(&msg, 2U) = (uint8_t)group;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SET_DMA_GROUP);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U8(&msg, 2U) = U8(group);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -110,21 +109,20 @@
 }
 
 sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src,
-				 sc_faddr_t addr_dst, uint32_t len,
-				 sc_bool_t fw)
+	sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_IMAGE_LOAD;
-	RPC_U32(&msg, 0U) = (uint32_t)(addr_src >> 32U);
-	RPC_U32(&msg, 4U) = (uint32_t)addr_src;
-	RPC_U32(&msg, 8U) = (uint32_t)(addr_dst >> 32U);
-	RPC_U32(&msg, 12U) = (uint32_t)addr_dst;
-	RPC_U32(&msg, 16U) = (uint32_t)len;
-	RPC_U8(&msg, 20U) = (uint8_t)fw;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_IMAGE_LOAD);
+	RPC_U32(&msg, 0U) = U32(addr_src >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr_src);
+	RPC_U32(&msg, 8U) = U32(addr_dst >> 32ULL);
+	RPC_U32(&msg, 12U) = U32(addr_dst);
+	RPC_U32(&msg, 16U) = U32(len);
+	RPC_U8(&msg, 20U) = B2U8(fw);
 	RPC_SIZE(&msg) = 7U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -134,17 +132,17 @@
 }
 
 sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc,
-				   sc_misc_seco_auth_cmd_t cmd, sc_faddr_t addr)
+	sc_misc_seco_auth_cmd_t cmd, sc_faddr_t addr)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_AUTHENTICATE;
-	RPC_U32(&msg, 0U) = (uint32_t)(addr >> 32U);
-	RPC_U32(&msg, 4U) = (uint32_t)addr;
-	RPC_U8(&msg, 8U) = (uint8_t)cmd;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_AUTHENTICATE);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
+	RPC_U8(&msg, 8U) = U8(cmd);
 	RPC_SIZE(&msg) = 4U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -159,10 +157,10 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_FUSE_WRITE;
-	RPC_U32(&msg, 0U) = (uint32_t)(addr >> 32U);
-	RPC_U32(&msg, 4U) = (uint32_t)addr;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_FUSE_WRITE);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -177,10 +175,10 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_ENABLE_DEBUG;
-	RPC_U32(&msg, 0U) = (uint32_t)(addr >> 32U);
-	RPC_U32(&msg, 4U) = (uint32_t)addr;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_ENABLE_DEBUG);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -189,15 +187,15 @@
 	return (sc_err_t)result;
 }
 
-sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t lifecycle)
+sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t change)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_FORWARD_LIFECYCLE;
-	RPC_U32(&msg, 0U) = (uint32_t)lifecycle;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_FORWARD_LIFECYCLE);
+	RPC_U32(&msg, 0U) = U32(change);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -212,10 +210,10 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_RETURN_LIFECYCLE;
-	RPC_U32(&msg, 0U) = (uint32_t)(addr >> 32U);
-	RPC_U32(&msg, 4U) = (uint32_t)addr;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_RETURN_LIFECYCLE);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -224,70 +222,171 @@
 	return (sc_err_t)result;
 }
 
-void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version, uint32_t *commit)
+void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version,
+	uint32_t *commit)
 {
 	sc_rpc_msg_t msg;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_BUILD_INFO;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_BUILD_INFO);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (version != NULL) {
-		*version = RPC_U32(&msg, 0U);
-	}
+	if (version != NULL)
+	    *version = RPC_U32(&msg, 0U);
 
-	if (commit != NULL) {
-		*commit = RPC_U32(&msg, 4U);
-	}
+	if (commit != NULL)
+	    *commit = RPC_U32(&msg, 4U);
 
 	return;
 }
 
 sc_err_t sc_misc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc,
-				uint16_t *monotonic, uint32_t *uid_l,
-				uint32_t *uid_h)
+	uint16_t *monotonic, uint32_t *uid_l, uint32_t *uid_h)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_CHIP_INFO;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_CHIP_INFO);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (uid_l != NULL) {
-		*uid_l = RPC_U32(&msg, 0U);
-	}
+	if (uid_l != NULL)
+	    *uid_l = RPC_U32(&msg, 0U);
 
-	if (uid_h != NULL) {
-		*uid_h = RPC_U32(&msg, 4U);
-	}
+	if (uid_h != NULL)
+	    *uid_h = RPC_U32(&msg, 4U);
 
-	if (lc != NULL) {
-		*lc = RPC_U16(&msg, 8U);
-	}
+	if (lc != NULL)
+	    *lc = RPC_U16(&msg, 8U);
 
-	if (monotonic != NULL) {
-		*monotonic = RPC_U16(&msg, 10U);
-	}
+	if (monotonic != NULL)
+	    *monotonic = RPC_U16(&msg, 10U);
 
 	result = RPC_R8(&msg);
 	return (sc_err_t)result;
 }
 
+sc_err_t sc_misc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_ATTEST_MODE);
+	RPC_U32(&msg, 0U) = U32(mode);
+	RPC_SIZE(&msg) = 2U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_misc_seco_attest(sc_ipc_t ipc, uint64_t nonce)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_ATTEST);
+	RPC_U32(&msg, 0U) = U32(nonce >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(nonce);
+	RPC_SIZE(&msg) = 3U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_misc_seco_get_attest_pkey(sc_ipc_t ipc, sc_faddr_t addr)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_GET_ATTEST_PKEY);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
+	RPC_SIZE(&msg) = 3U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_misc_seco_get_attest_sign(sc_ipc_t ipc, sc_faddr_t addr)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_GET_ATTEST_SIGN);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
+	RPC_SIZE(&msg) = 3U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_misc_seco_attest_verify(sc_ipc_t ipc, sc_faddr_t addr)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_ATTEST_VERIFY);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
+	RPC_SIZE(&msg) = 3U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_misc_seco_commit(sc_ipc_t ipc, uint32_t *info)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_COMMIT);
+	RPC_U32(&msg, 0U) = *PTR_U32(info);
+	RPC_SIZE(&msg) = 2U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	*info = RPC_U32(&msg, 0U);
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
 void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch)
 {
 	sc_rpc_msg_t msg;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_DEBUG_OUT;
-	RPC_U8(&msg, 0U) = (uint8_t)ch;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_DEBUG_OUT);
+	RPC_U8(&msg, 0U) = U8(ch);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -301,9 +400,9 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_WAVEFORM_CAPTURE;
-	RPC_U8(&msg, 0U) = (uint8_t)enable;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_WAVEFORM_CAPTURE);
+	RPC_U8(&msg, 0U) = B2U8(enable);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -312,63 +411,61 @@
 	return (sc_err_t)result;
 }
 
-void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, uint32_t *commit)
+void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build,
+	uint32_t *commit)
 {
 	sc_rpc_msg_t msg;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_BUILD_INFO;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_BUILD_INFO);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (build != NULL) {
-		*build = RPC_U32(&msg, 0U);
-	}
+	if (build != NULL)
+	    *build = RPC_U32(&msg, 0U);
 
-	if (commit != NULL) {
-		*commit = RPC_U32(&msg, 4U);
-	}
+	if (commit != NULL)
+	    *commit = RPC_U32(&msg, 4U);
 
 	return;
 }
 
-void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, uint32_t *id_h)
+void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l,
+	uint32_t *id_h)
 {
 	sc_rpc_msg_t msg;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_UNIQUE_ID;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_UNIQUE_ID);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (id_l != NULL) {
-		*id_l = RPC_U32(&msg, 0U);
-	}
+	if (id_l != NULL)
+	    *id_l = RPC_U32(&msg, 0U);
 
-	if (id_h != NULL) {
-		*id_h = RPC_U32(&msg, 4U);
-	}
+	if (id_h != NULL)
+	    *id_h = RPC_U32(&msg, 4U);
 
 	return;
 }
 
 sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource,
-			 sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable)
+	sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SET_ARI;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U16(&msg, 2U) = (uint16_t)resource_mst;
-	RPC_U16(&msg, 4U) = (uint16_t)ari;
-	RPC_U8(&msg, 6U) = (uint8_t)enable;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SET_ARI);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U16(&msg, 2U) = U16(resource_mst);
+	RPC_U16(&msg, 4U) = U16(ari);
+	RPC_U8(&msg, 6U) = B2U8(enable);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -382,9 +479,9 @@
 	sc_rpc_msg_t msg;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_BOOT_STATUS;
-	RPC_U8(&msg, 0U) = (uint8_t)status;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_BOOT_STATUS);
+	RPC_U8(&msg, 0U) = U8(status);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_TRUE);
@@ -398,9 +495,9 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_BOOT_DONE;
-	RPC_U16(&msg, 0U) = (uint16_t)cpu;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_BOOT_DONE);
+	RPC_U16(&msg, 0U) = U16(cpu);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -415,16 +512,15 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_OTP_FUSE_READ;
-	RPC_U32(&msg, 0U) = (uint32_t)word;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_OTP_FUSE_READ);
+	RPC_U32(&msg, 0U) = U32(word);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (val != NULL) {
-		*val = RPC_U32(&msg, 0U);
-	}
+	if (val != NULL)
+	    *val = RPC_U32(&msg, 0U);
 
 	result = RPC_R8(&msg);
 	return (sc_err_t)result;
@@ -436,10 +532,10 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_OTP_FUSE_WRITE;
-	RPC_U32(&msg, 0U) = (uint32_t)word;
-	RPC_U32(&msg, 4U) = (uint32_t)val;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_OTP_FUSE_WRITE);
+	RPC_U32(&msg, 0U) = U32(word);
+	RPC_U32(&msg, 4U) = U32(val);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -449,18 +545,18 @@
 }
 
 sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource,
-			  sc_misc_temp_t temp, int16_t celsius, int8_t tenths)
+	sc_misc_temp_t temp, int16_t celsius, int8_t tenths)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SET_TEMP;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_I16(&msg, 2U) = (int16_t) celsius;
-	RPC_U8(&msg, 4U) = (uint8_t)temp;
-	RPC_I8(&msg, 5U) = (int8_t) tenths;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_SET_TEMP);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_I16(&msg, 2U) = I16(celsius);
+	RPC_U8(&msg, 4U) = U8(temp);
+	RPC_I8(&msg, 5U) = I8(tenths);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -470,67 +566,124 @@
 }
 
 sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource,
-			  sc_misc_temp_t temp, int16_t * celsius,
-			  int8_t * tenths)
+	sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_GET_TEMP;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U8(&msg, 2U) = (uint8_t)temp;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_GET_TEMP);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U8(&msg, 2U) = U8(temp);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (celsius != NULL) {
-		*celsius = RPC_I16(&msg, 0U);
-	}
+	if (celsius != NULL)
+	    *celsius = RPC_I16(&msg, 0U);
 
 	result = RPC_R8(&msg);
-	if (tenths != NULL) {
-		*tenths = RPC_I8(&msg, 2U);
-	}
+	if (tenths != NULL)
+	    *tenths = RPC_I8(&msg, 2U);
 
 	return (sc_err_t)result;
 }
 
-void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t * dev)
+void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev)
 {
 	sc_rpc_msg_t msg;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_GET_BOOT_DEV;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_GET_BOOT_DEV);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (dev != NULL) {
-		*dev = RPC_U16(&msg, 0U);
-	}
+	if (dev != NULL)
+	    *dev = RPC_U16(&msg, 0U);
 
 	return;
 }
 
+sc_err_t sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t *type)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_GET_BOOT_TYPE);
+	RPC_SIZE(&msg) = 1U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	if (type != NULL)
+	    *type = RPC_U8(&msg, 0U);
+
+	return (sc_err_t)result;
+}
+
 void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status)
 {
 	sc_rpc_msg_t msg;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
-	RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_GET_BUTTON_STATUS;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_GET_BUTTON_STATUS);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (status != NULL) {
-		*status = RPC_U8(&msg, 0U);
-	}
+	if (status != NULL)
+	    *status = U2B(RPC_U8(&msg, 0U));
 
 	return;
 }
 
+sc_err_t sc_misc_rompatch_checksum(sc_ipc_t ipc, uint32_t *checksum)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_ROMPATCH_CHECKSUM);
+	RPC_SIZE(&msg) = 1U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	if (checksum != NULL)
+	    *checksum = RPC_U32(&msg, 0U);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_misc_board_ioctl(sc_ipc_t ipc, uint32_t *parm1,
+	uint32_t *parm2, uint32_t *parm3)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = U8(MISC_FUNC_BOARD_IOCTL);
+	RPC_U32(&msg, 0U) = *PTR_U32(parm1);
+	RPC_U32(&msg, 4U) = *PTR_U32(parm2);
+	RPC_U32(&msg, 8U) = *PTR_U32(parm3);
+	RPC_SIZE(&msg) = 4U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	*parm1 = RPC_U32(&msg, 0U);
+	*parm2 = RPC_U32(&msg, 4U);
+	*parm3 = RPC_U32(&msg, 8U);
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
 /**@}*/
+
diff --git a/plat/imx/common/sci/svc/misc/sci_misc_rpc.h b/plat/imx/common/sci/svc/misc/sci_misc_rpc.h
index b9dc35b..7288435 100644
--- a/plat/imx/common/sci/svc/misc/sci_misc_rpc.h
+++ b/plat/imx/common/sci/svc/misc/sci_misc_rpc.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,32 +23,41 @@
  * @name Defines for RPC MISC function calls
  */
 /*@{*/
-#define MISC_FUNC_UNKNOWN 0	/* Unknown function */
-#define MISC_FUNC_SET_CONTROL 1U	/* Index for misc_set_control() RPC call */
-#define MISC_FUNC_GET_CONTROL 2U	/* Index for misc_get_control() RPC call */
-#define MISC_FUNC_SET_MAX_DMA_GROUP 4U	/* Index for misc_set_max_dma_group() RPC call */
-#define MISC_FUNC_SET_DMA_GROUP 5U	/* Index for misc_set_dma_group() RPC call */
-#define MISC_FUNC_SECO_IMAGE_LOAD 8U	/* Index for misc_seco_image_load() RPC call */
-#define MISC_FUNC_SECO_AUTHENTICATE 9U	/* Index for misc_seco_authenticate() RPC call */
-#define MISC_FUNC_SECO_FUSE_WRITE 20U	/* Index for misc_seco_fuse_write() RPC call */
-#define MISC_FUNC_SECO_ENABLE_DEBUG 21U	/* Index for misc_seco_enable_debug() RPC call */
-#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U	/* Index for misc_seco_forward_lifecycle() RPC call */
-#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U	/* Index for misc_seco_return_lifecycle() RPC call */
-#define MISC_FUNC_SECO_BUILD_INFO 24U	/* Index for misc_seco_build_info() RPC call */
-#define MISC_FUNC_SECO_CHIP_INFO 25U	/* Index for misc_seco_chip_info() RPC call */
-#define MISC_FUNC_DEBUG_OUT 10U	/* Index for misc_debug_out() RPC call */
-#define MISC_FUNC_WAVEFORM_CAPTURE 6U	/* Index for misc_waveform_capture() RPC call */
-#define MISC_FUNC_BUILD_INFO 15U	/* Index for misc_build_info() RPC call */
-#define MISC_FUNC_UNIQUE_ID 19U	/* Index for misc_unique_id() RPC call */
-#define MISC_FUNC_SET_ARI 3U	/* Index for misc_set_ari() RPC call */
-#define MISC_FUNC_BOOT_STATUS 7U	/* Index for misc_boot_status() RPC call */
-#define MISC_FUNC_BOOT_DONE 14U	/* Index for misc_boot_done() RPC call */
-#define MISC_FUNC_OTP_FUSE_READ 11U	/* Index for misc_otp_fuse_read() RPC call */
-#define MISC_FUNC_OTP_FUSE_WRITE 17U	/* Index for misc_otp_fuse_write() RPC call */
-#define MISC_FUNC_SET_TEMP 12U	/* Index for misc_set_temp() RPC call */
-#define MISC_FUNC_GET_TEMP 13U	/* Index for misc_get_temp() RPC call */
-#define MISC_FUNC_GET_BOOT_DEV 16U	/* Index for misc_get_boot_dev() RPC call */
-#define MISC_FUNC_GET_BUTTON_STATUS 18U	/* Index for misc_get_button_status() RPC call */
+#define MISC_FUNC_UNKNOWN 0 /* Unknown function */
+#define MISC_FUNC_SET_CONTROL 1U /* Index for misc_set_control() RPC call */
+#define MISC_FUNC_GET_CONTROL 2U /* Index for misc_get_control() RPC call */
+#define MISC_FUNC_SET_MAX_DMA_GROUP 4U /* Index for misc_set_max_dma_group() RPC call */
+#define MISC_FUNC_SET_DMA_GROUP 5U /* Index for misc_set_dma_group() RPC call */
+#define MISC_FUNC_SECO_IMAGE_LOAD 8U /* Index for misc_seco_image_load() RPC call */
+#define MISC_FUNC_SECO_AUTHENTICATE 9U /* Index for misc_seco_authenticate() RPC call */
+#define MISC_FUNC_SECO_FUSE_WRITE 20U /* Index for misc_seco_fuse_write() RPC call */
+#define MISC_FUNC_SECO_ENABLE_DEBUG 21U /* Index for misc_seco_enable_debug() RPC call */
+#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U /* Index for misc_seco_forward_lifecycle() RPC call */
+#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U /* Index for misc_seco_return_lifecycle() RPC call */
+#define MISC_FUNC_SECO_BUILD_INFO 24U /* Index for misc_seco_build_info() RPC call */
+#define MISC_FUNC_SECO_CHIP_INFO 25U /* Index for misc_seco_chip_info() RPC call */
+#define MISC_FUNC_SECO_ATTEST_MODE 27U /* Index for misc_seco_attest_mode() RPC call */
+#define MISC_FUNC_SECO_ATTEST 28U /* Index for misc_seco_attest() RPC call */
+#define MISC_FUNC_SECO_GET_ATTEST_PKEY 31U /* Index for misc_seco_get_attest_pkey() RPC call */
+#define MISC_FUNC_SECO_GET_ATTEST_SIGN 29U /* Index for misc_seco_get_attest_sign() RPC call */
+#define MISC_FUNC_SECO_ATTEST_VERIFY 30U /* Index for misc_seco_attest_verify() RPC call */
+#define MISC_FUNC_SECO_COMMIT 32U /* Index for misc_seco_commit() RPC call */
+#define MISC_FUNC_DEBUG_OUT 10U /* Index for misc_debug_out() RPC call */
+#define MISC_FUNC_WAVEFORM_CAPTURE 6U /* Index for misc_waveform_capture() RPC call */
+#define MISC_FUNC_BUILD_INFO 15U /* Index for misc_build_info() RPC call */
+#define MISC_FUNC_UNIQUE_ID 19U /* Index for misc_unique_id() RPC call */
+#define MISC_FUNC_SET_ARI 3U /* Index for misc_set_ari() RPC call */
+#define MISC_FUNC_BOOT_STATUS 7U /* Index for misc_boot_status() RPC call */
+#define MISC_FUNC_BOOT_DONE 14U /* Index for misc_boot_done() RPC call */
+#define MISC_FUNC_OTP_FUSE_READ 11U /* Index for misc_otp_fuse_read() RPC call */
+#define MISC_FUNC_OTP_FUSE_WRITE 17U /* Index for misc_otp_fuse_write() RPC call */
+#define MISC_FUNC_SET_TEMP 12U /* Index for misc_set_temp() RPC call */
+#define MISC_FUNC_GET_TEMP 13U /* Index for misc_get_temp() RPC call */
+#define MISC_FUNC_GET_BOOT_DEV 16U /* Index for misc_get_boot_dev() RPC call */
+#define MISC_FUNC_GET_BOOT_TYPE 33U /* Index for misc_get_boot_type() RPC call */
+#define MISC_FUNC_GET_BUTTON_STATUS 18U /* Index for misc_get_button_status() RPC call */
+#define MISC_FUNC_ROMPATCH_CHECKSUM 26U /* Index for misc_rompatch_checksum() RPC call */
+#define MISC_FUNC_BOARD_IOCTL 34U /* Index for misc_board_ioctl() RPC call */
 /*@}*/
 
 /* Types */
@@ -61,16 +70,9 @@
  * @param[in]     caller_pt   caller partition
  * @param[in]     msg         pointer to RPC message
  */
-void misc_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
+void misc_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg);
 
-/*!
- * This function translates and dispatches an MISC RPC request.
- *
- * @param[in]     ipc         IPC handle
- * @param[in]     msg         pointer to RPC message
- */
-void misc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
-
-#endif				/* SC_MISC_RPC_H */
+#endif /* SC_MISC_RPC_H */
 
 /**@}*/
+
diff --git a/plat/imx/common/sci/svc/pad/pad_rpc_clnt.c b/plat/imx/common/sci/svc/pad/pad_rpc_clnt.c
index 555e704..6bc6823 100644
--- a/plat/imx/common/sci/svc/pad/pad_rpc_clnt.c
+++ b/plat/imx/common/sci/svc/pad/pad_rpc_clnt.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,8 +19,8 @@
 #include <sci/svc/rm/sci_rm_api.h>
 #include <sci/svc/pad/sci_pad_api.h>
 #include <sci/sci_rpc.h>
-#include <stdlib.h>
 #include "sci_pad_rpc.h"
+#include <stdlib.h>
 
 /* Local Defines */
 
@@ -28,18 +29,18 @@
 /* Local Functions */
 
 sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad,
-			uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso)
+	uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_MUX;
-	RPC_U16(&msg, 0U) = (uint16_t)pad;
-	RPC_U8(&msg, 2U) = (uint8_t)mux;
-	RPC_U8(&msg, 3U) = (uint8_t)config;
-	RPC_U8(&msg, 4U) = (uint8_t)iso;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_SET_MUX);
+	RPC_U16(&msg, 0U) = U16(pad);
+	RPC_U8(&msg, 2U) = U8(mux);
+	RPC_U8(&msg, 3U) = U8(config);
+	RPC_U8(&msg, 4U) = U8(iso);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -49,32 +50,28 @@
 }
 
 sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad,
-			uint8_t *mux, sc_pad_config_t *config,
-			sc_pad_iso_t *iso)
+	uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_MUX;
-	RPC_U16(&msg, 0U) = (uint16_t)pad;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_GET_MUX);
+	RPC_U16(&msg, 0U) = U16(pad);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	if (mux != NULL) {
-		*mux = RPC_U8(&msg, 0U);
-	}
+	if (mux != NULL)
+	    *mux = RPC_U8(&msg, 0U);
 
-	if (config != NULL) {
-		*config = RPC_U8(&msg, 1U);
-	}
+	if (config != NULL)
+	    *config = RPC_U8(&msg, 1U);
 
-	if (iso != NULL) {
-		*iso = RPC_U8(&msg, 2U);
-	}
+	if (iso != NULL)
+	    *iso = RPC_U8(&msg, 2U);
 
 	return (sc_err_t)result;
 }
@@ -85,10 +82,10 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP;
-	RPC_U32(&msg, 0U) = (uint32_t)ctrl;
-	RPC_U16(&msg, 4U) = (uint16_t)pad;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP);
+	RPC_U32(&msg, 0U) = U32(ctrl);
+	RPC_U16(&msg, 4U) = U16(pad);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -103,31 +100,31 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP;
-	RPC_U16(&msg, 0U) = (uint16_t)pad;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP);
+	RPC_U16(&msg, 0U) = U16(pad);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (ctrl != NULL) {
-		*ctrl = RPC_U32(&msg, 0U);
-	}
+	if (ctrl != NULL)
+	    *ctrl = RPC_U32(&msg, 0U);
 
 	result = RPC_R8(&msg);
 	return (sc_err_t)result;
 }
 
-sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t wakeup)
+sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad,
+	sc_pad_wakeup_t wakeup)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_WAKEUP;
-	RPC_U16(&msg, 0U) = (uint16_t)pad;
-	RPC_U8(&msg, 2U) = (uint8_t)wakeup;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_SET_WAKEUP);
+	RPC_U16(&msg, 0U) = U16(pad);
+	RPC_U8(&msg, 2U) = U8(wakeup);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -136,43 +133,43 @@
 	return (sc_err_t)result;
 }
 
-sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t *wakeup)
+sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad,
+	sc_pad_wakeup_t *wakeup)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_WAKEUP;
-	RPC_U16(&msg, 0U) = (uint16_t)pad;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_GET_WAKEUP);
+	RPC_U16(&msg, 0U) = U16(pad);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	if (wakeup != NULL) {
-		*wakeup = RPC_U8(&msg, 0U);
-	}
+	if (wakeup != NULL)
+	    *wakeup = RPC_U8(&msg, 0U);
 
 	return (sc_err_t)result;
 }
 
 sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux,
-			sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
-			sc_pad_wakeup_t wakeup)
+	sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
+	sc_pad_wakeup_t wakeup)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_ALL;
-	RPC_U32(&msg, 0U) = (uint32_t)ctrl;
-	RPC_U16(&msg, 4U) = (uint16_t)pad;
-	RPC_U8(&msg, 6U) = (uint8_t)mux;
-	RPC_U8(&msg, 7U) = (uint8_t)config;
-	RPC_U8(&msg, 8U) = (uint8_t)iso;
-	RPC_U8(&msg, 9U) = (uint8_t)wakeup;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_SET_ALL);
+	RPC_U32(&msg, 0U) = U32(ctrl);
+	RPC_U16(&msg, 4U) = U16(pad);
+	RPC_U8(&msg, 6U) = U8(mux);
+	RPC_U8(&msg, 7U) = U8(config);
+	RPC_U8(&msg, 8U) = U8(iso);
+	RPC_U8(&msg, 9U) = U8(wakeup);
 	RPC_SIZE(&msg) = 4U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -182,40 +179,35 @@
 }
 
 sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux,
-			sc_pad_config_t *config, sc_pad_iso_t *iso,
-			uint32_t *ctrl, sc_pad_wakeup_t *wakeup)
+	sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl,
+	sc_pad_wakeup_t *wakeup)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_ALL;
-	RPC_U16(&msg, 0U) = (uint16_t)pad;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_GET_ALL);
+	RPC_U16(&msg, 0U) = U16(pad);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (ctrl != NULL) {
-		*ctrl = RPC_U32(&msg, 0U);
-	}
+	if (ctrl != NULL)
+	    *ctrl = RPC_U32(&msg, 0U);
 
 	result = RPC_R8(&msg);
-	if (mux != NULL) {
-		*mux = RPC_U8(&msg, 4U);
-	}
+	if (mux != NULL)
+	    *mux = RPC_U8(&msg, 4U);
 
-	if (config != NULL) {
-		*config = RPC_U8(&msg, 5U);
-	}
+	if (config != NULL)
+	    *config = RPC_U8(&msg, 5U);
 
-	if (iso != NULL) {
-		*iso = RPC_U8(&msg, 6U);
-	}
+	if (iso != NULL)
+	    *iso = RPC_U8(&msg, 6U);
 
-	if (wakeup != NULL) {
-		*wakeup = RPC_U8(&msg, 7U);
-	}
+	if (wakeup != NULL)
+	    *wakeup = RPC_U8(&msg, 7U);
 
 	return (sc_err_t)result;
 }
@@ -226,10 +218,10 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET;
-	RPC_U32(&msg, 0U) = (uint32_t)val;
-	RPC_U16(&msg, 4U) = (uint16_t)pad;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_SET);
+	RPC_U32(&msg, 0U) = U32(val);
+	RPC_U16(&msg, 4U) = U16(pad);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -244,33 +236,32 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET;
-	RPC_U16(&msg, 0U) = (uint16_t)pad;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_GET);
+	RPC_U16(&msg, 0U) = U16(pad);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (val != NULL) {
-		*val = RPC_U32(&msg, 0U);
-	}
+	if (val != NULL)
+	    *val = RPC_U32(&msg, 0U);
 
 	result = RPC_R8(&msg);
 	return (sc_err_t)result;
 }
 
 sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
-			       sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps)
+	sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP_28FDSOI;
-	RPC_U16(&msg, 0U) = (uint16_t)pad;
-	RPC_U8(&msg, 2U) = (uint8_t)dse;
-	RPC_U8(&msg, 3U) = (uint8_t)ps;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP_28FDSOI);
+	RPC_U16(&msg, 0U) = U16(pad);
+	RPC_U8(&msg, 2U) = U8(dse);
+	RPC_U8(&msg, 3U) = U8(ps);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -280,49 +271,45 @@
 }
 
 sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
-			       sc_pad_28fdsoi_dse_t *dse,
-			       sc_pad_28fdsoi_ps_t *ps)
+	sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP_28FDSOI;
-	RPC_U16(&msg, 0U) = (uint16_t)pad;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP_28FDSOI);
+	RPC_U16(&msg, 0U) = U16(pad);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	if (dse != NULL) {
-		*dse = RPC_U8(&msg, 0U);
-	}
+	if (dse != NULL)
+	    *dse = RPC_U8(&msg, 0U);
 
-	if (ps != NULL) {
-		*ps = RPC_U8(&msg, 1U);
-	}
+	if (ps != NULL)
+	    *ps = RPC_U8(&msg, 1U);
 
 	return (sc_err_t)result;
 }
 
 sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
-				    sc_pad_28fdsoi_dse_t dse, sc_bool_t hys,
-				    sc_pad_28fdsoi_pus_t pus, sc_bool_t pke,
-				    sc_bool_t pue)
+	sc_pad_28fdsoi_dse_t dse, sc_bool_t hys, sc_pad_28fdsoi_pus_t pus,
+	sc_bool_t pke, sc_bool_t pue)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP_28FDSOI_HSIC;
-	RPC_U16(&msg, 0U) = (uint16_t)pad;
-	RPC_U8(&msg, 2U) = (uint8_t)dse;
-	RPC_U8(&msg, 3U) = (uint8_t)pus;
-	RPC_U8(&msg, 4U) = (uint8_t)hys;
-	RPC_U8(&msg, 5U) = (uint8_t)pke;
-	RPC_U8(&msg, 6U) = (uint8_t)pue;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP_28FDSOI_HSIC);
+	RPC_U16(&msg, 0U) = U16(pad);
+	RPC_U8(&msg, 2U) = U8(dse);
+	RPC_U8(&msg, 3U) = U8(pus);
+	RPC_U8(&msg, 4U) = B2U8(hys);
+	RPC_U8(&msg, 5U) = B2U8(pke);
+	RPC_U8(&msg, 6U) = B2U8(pue);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -332,63 +319,56 @@
 }
 
 sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
-				    sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys,
-				    sc_pad_28fdsoi_pus_t *pus, sc_bool_t *pke,
-				    sc_bool_t *pue)
+	sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys, sc_pad_28fdsoi_pus_t *pus,
+	sc_bool_t *pke, sc_bool_t *pue)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP_28FDSOI_HSIC;
-	RPC_U16(&msg, 0U) = (uint16_t)pad;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP_28FDSOI_HSIC);
+	RPC_U16(&msg, 0U) = U16(pad);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	if (dse != NULL) {
-		*dse = RPC_U8(&msg, 0U);
-	}
+	if (dse != NULL)
+	    *dse = RPC_U8(&msg, 0U);
 
-	if (pus != NULL) {
-		*pus = RPC_U8(&msg, 1U);
-	}
+	if (pus != NULL)
+	    *pus = RPC_U8(&msg, 1U);
 
-	if (hys != NULL) {
-		*hys = RPC_U8(&msg, 2U);
-	}
+	if (hys != NULL)
+	    *hys = U2B(RPC_U8(&msg, 2U));
 
-	if (pke != NULL) {
-		*pke = RPC_U8(&msg, 3U);
-	}
+	if (pke != NULL)
+	    *pke = U2B(RPC_U8(&msg, 3U));
 
-	if (pue != NULL) {
-		*pue = RPC_U8(&msg, 4U);
-	}
+	if (pue != NULL)
+	    *pue = U2B(RPC_U8(&msg, 4U));
 
 	return (sc_err_t)result;
 }
 
 sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
-				    uint8_t compen, sc_bool_t fastfrz,
-				    uint8_t rasrcp, uint8_t rasrcn,
-				    sc_bool_t nasrc_sel, sc_bool_t psw_ovr)
+	uint8_t compen, sc_bool_t fastfrz, uint8_t rasrcp, uint8_t rasrcn,
+	sc_bool_t nasrc_sel, sc_bool_t psw_ovr)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP_28FDSOI_COMP;
-	RPC_U16(&msg, 0U) = (uint16_t)pad;
-	RPC_U8(&msg, 2U) = (uint8_t)compen;
-	RPC_U8(&msg, 3U) = (uint8_t)rasrcp;
-	RPC_U8(&msg, 4U) = (uint8_t)rasrcn;
-	RPC_U8(&msg, 5U) = (uint8_t)fastfrz;
-	RPC_U8(&msg, 6U) = (uint8_t)nasrc_sel;
-	RPC_U8(&msg, 7U) = (uint8_t)psw_ovr;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP_28FDSOI_COMP);
+	RPC_U16(&msg, 0U) = U16(pad);
+	RPC_U8(&msg, 2U) = U8(compen);
+	RPC_U8(&msg, 3U) = U8(rasrcp);
+	RPC_U8(&msg, 4U) = U8(rasrcn);
+	RPC_U8(&msg, 5U) = B2U8(fastfrz);
+	RPC_U8(&msg, 6U) = B2U8(nasrc_sel);
+	RPC_U8(&msg, 7U) = B2U8(psw_ovr);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -398,56 +378,47 @@
 }
 
 sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
-				    uint8_t *compen, sc_bool_t *fastfrz,
-				    uint8_t *rasrcp, uint8_t *rasrcn,
-				    sc_bool_t *nasrc_sel, sc_bool_t *compok,
-				    uint8_t *nasrc, sc_bool_t *psw_ovr)
+	uint8_t *compen, sc_bool_t *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn,
+	sc_bool_t *nasrc_sel, sc_bool_t *compok, uint8_t *nasrc, sc_bool_t *psw_ovr)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
-	RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP_28FDSOI_COMP;
-	RPC_U16(&msg, 0U) = (uint16_t)pad;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
+	RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP_28FDSOI_COMP);
+	RPC_U16(&msg, 0U) = U16(pad);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	if (compen != NULL) {
-		*compen = RPC_U8(&msg, 0U);
-	}
+	if (compen != NULL)
+	    *compen = RPC_U8(&msg, 0U);
 
-	if (rasrcp != NULL) {
-		*rasrcp = RPC_U8(&msg, 1U);
-	}
+	if (rasrcp != NULL)
+	    *rasrcp = RPC_U8(&msg, 1U);
 
-	if (rasrcn != NULL) {
-		*rasrcn = RPC_U8(&msg, 2U);
-	}
+	if (rasrcn != NULL)
+	    *rasrcn = RPC_U8(&msg, 2U);
 
-	if (nasrc != NULL) {
-		*nasrc = RPC_U8(&msg, 3U);
-	}
+	if (nasrc != NULL)
+	    *nasrc = RPC_U8(&msg, 3U);
 
-	if (fastfrz != NULL) {
-		*fastfrz = RPC_U8(&msg, 4U);
-	}
+	if (fastfrz != NULL)
+	    *fastfrz = U2B(RPC_U8(&msg, 4U));
 
-	if (nasrc_sel != NULL) {
-		*nasrc_sel = RPC_U8(&msg, 5U);
-	}
+	if (nasrc_sel != NULL)
+	    *nasrc_sel = U2B(RPC_U8(&msg, 5U));
 
-	if (compok != NULL) {
-		*compok = RPC_U8(&msg, 6U);
-	}
+	if (compok != NULL)
+	    *compok = U2B(RPC_U8(&msg, 6U));
 
-	if (psw_ovr != NULL) {
-		*psw_ovr = RPC_U8(&msg, 7U);
-	}
+	if (psw_ovr != NULL)
+	    *psw_ovr = U2B(RPC_U8(&msg, 7U));
 
 	return (sc_err_t)result;
 }
 
 /**@}*/
+
diff --git a/plat/imx/common/sci/svc/pad/sci_pad_rpc.h b/plat/imx/common/sci/svc/pad/sci_pad_rpc.h
index 686e6e9..134eec6 100644
--- a/plat/imx/common/sci/svc/pad/sci_pad_rpc.h
+++ b/plat/imx/common/sci/svc/pad/sci_pad_rpc.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,23 +23,23 @@
  * @name Defines for RPC PAD function calls
  */
 /*@{*/
-#define PAD_FUNC_UNKNOWN 0	/* Unknown function */
-#define PAD_FUNC_SET_MUX 1U	/* Index for pad_set_mux() RPC call */
-#define PAD_FUNC_GET_MUX 6U	/* Index for pad_get_mux() RPC call */
-#define PAD_FUNC_SET_GP 2U	/* Index for pad_set_gp() RPC call */
-#define PAD_FUNC_GET_GP 7U	/* Index for pad_get_gp() RPC call */
-#define PAD_FUNC_SET_WAKEUP 4U	/* Index for pad_set_wakeup() RPC call */
-#define PAD_FUNC_GET_WAKEUP 9U	/* Index for pad_get_wakeup() RPC call */
-#define PAD_FUNC_SET_ALL 5U	/* Index for pad_set_all() RPC call */
-#define PAD_FUNC_GET_ALL 10U	/* Index for pad_get_all() RPC call */
-#define PAD_FUNC_SET 15U	/* Index for pad_set() RPC call */
-#define PAD_FUNC_GET 16U	/* Index for pad_get() RPC call */
-#define PAD_FUNC_SET_GP_28FDSOI 11U	/* Index for pad_set_gp_28fdsoi() RPC call */
-#define PAD_FUNC_GET_GP_28FDSOI 12U	/* Index for pad_get_gp_28fdsoi() RPC call */
-#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U	/* Index for pad_set_gp_28fdsoi_hsic() RPC call */
-#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U	/* Index for pad_get_gp_28fdsoi_hsic() RPC call */
-#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U	/* Index for pad_set_gp_28fdsoi_comp() RPC call */
-#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U	/* Index for pad_get_gp_28fdsoi_comp() RPC call */
+#define PAD_FUNC_UNKNOWN 0 /* Unknown function */
+#define PAD_FUNC_SET_MUX 1U /* Index for pad_set_mux() RPC call */
+#define PAD_FUNC_GET_MUX 6U /* Index for pad_get_mux() RPC call */
+#define PAD_FUNC_SET_GP 2U /* Index for pad_set_gp() RPC call */
+#define PAD_FUNC_GET_GP 7U /* Index for pad_get_gp() RPC call */
+#define PAD_FUNC_SET_WAKEUP 4U /* Index for pad_set_wakeup() RPC call */
+#define PAD_FUNC_GET_WAKEUP 9U /* Index for pad_get_wakeup() RPC call */
+#define PAD_FUNC_SET_ALL 5U /* Index for pad_set_all() RPC call */
+#define PAD_FUNC_GET_ALL 10U /* Index for pad_get_all() RPC call */
+#define PAD_FUNC_SET 15U /* Index for pad_set() RPC call */
+#define PAD_FUNC_GET 16U /* Index for pad_get() RPC call */
+#define PAD_FUNC_SET_GP_28FDSOI 11U /* Index for pad_set_gp_28fdsoi() RPC call */
+#define PAD_FUNC_GET_GP_28FDSOI 12U /* Index for pad_get_gp_28fdsoi() RPC call */
+#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U /* Index for pad_set_gp_28fdsoi_hsic() RPC call */
+#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U /* Index for pad_get_gp_28fdsoi_hsic() RPC call */
+#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U /* Index for pad_set_gp_28fdsoi_comp() RPC call */
+#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U /* Index for pad_get_gp_28fdsoi_comp() RPC call */
 /*@}*/
 
 /* Types */
@@ -51,16 +52,9 @@
  * @param[in]     caller_pt   caller partition
  * @param[in]     msg         pointer to RPC message
  */
-void pad_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
+void pad_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg);
 
-/*!
- * This function translates and dispatches an PAD RPC request.
- *
- * @param[in]     ipc         IPC handle
- * @param[in]     msg         pointer to RPC message
- */
-void pad_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
-
-#endif				/* SC_PAD_RPC_H */
+#endif /* SC_PAD_RPC_H */
 
 /**@}*/
+
diff --git a/plat/imx/common/sci/svc/pm/pm_rpc_clnt.c b/plat/imx/common/sci/svc/pm/pm_rpc_clnt.c
index b108c49..9ef1c73 100644
--- a/plat/imx/common/sci/svc/pm/pm_rpc_clnt.c
+++ b/plat/imx/common/sci/svc/pm/pm_rpc_clnt.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,8 +19,8 @@
 #include <sci/svc/rm/sci_rm_api.h>
 #include <sci/svc/pm/sci_pm_api.h>
 #include <sci/sci_rpc.h>
-#include <stdlib.h>
 #include "sci_pm_rpc.h"
+#include <stdlib.h>
 
 /* Local Defines */
 
@@ -33,9 +34,9 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_SYS_POWER_MODE;
-	RPC_U8(&msg, 0U) = (uint8_t)mode;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_SET_SYS_POWER_MODE);
+	RPC_U8(&msg, 0U) = U8(mode);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -45,16 +46,16 @@
 }
 
 sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
-					sc_pm_power_mode_t mode)
+	sc_pm_power_mode_t mode)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_PARTITION_POWER_MODE;
-	RPC_U8(&msg, 0U) = (uint8_t)pt;
-	RPC_U8(&msg, 1U) = (uint8_t)mode;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_SET_PARTITION_POWER_MODE);
+	RPC_U8(&msg, 0U) = U8(pt);
+	RPC_U8(&msg, 1U) = U8(mode);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -64,38 +65,57 @@
 }
 
 sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
-				  sc_pm_power_mode_t *mode)
+	sc_pm_power_mode_t *mode)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_SYS_POWER_MODE;
-	RPC_U8(&msg, 0U) = (uint8_t)pt;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_GET_SYS_POWER_MODE);
+	RPC_U8(&msg, 0U) = U8(pt);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	if (mode != NULL) {
-		*mode = RPC_U8(&msg, 0U);
-	}
+	if (mode != NULL)
+	    *mode = RPC_U8(&msg, 0U);
 
 	return (sc_err_t)result;
 }
 
 sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
-				       sc_pm_power_mode_t mode)
+	sc_pm_power_mode_t mode)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_RESOURCE_POWER_MODE;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U8(&msg, 2U) = (uint8_t)mode;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_SET_RESOURCE_POWER_MODE);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U8(&msg, 2U) = U8(mode);
+	RPC_SIZE(&msg) = 2U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_pm_set_resource_power_mode_all(sc_ipc_t ipc,
+	sc_rm_pt_t pt, sc_pm_power_mode_t mode, sc_rsrc_t exclude)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_SET_RESOURCE_POWER_MODE_ALL);
+	RPC_U16(&msg, 0U) = U16(exclude);
+	RPC_U8(&msg, 2U) = U8(pt);
+	RPC_U8(&msg, 3U) = U8(mode);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -105,38 +125,37 @@
 }
 
 sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
-				       sc_pm_power_mode_t *mode)
+	sc_pm_power_mode_t *mode)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_RESOURCE_POWER_MODE;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_GET_RESOURCE_POWER_MODE);
+	RPC_U16(&msg, 0U) = U16(resource);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	if (mode != NULL) {
-		*mode = RPC_U8(&msg, 0U);
-	}
+	if (mode != NULL)
+	    *mode = RPC_U8(&msg, 0U);
 
 	return (sc_err_t)result;
 }
 
 sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
-				  sc_pm_power_mode_t mode)
+	sc_pm_power_mode_t mode)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REQ_LOW_POWER_MODE;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U8(&msg, 2U) = (uint8_t)mode;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_REQ_LOW_POWER_MODE);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U8(&msg, 2U) = U8(mode);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -146,18 +165,17 @@
 }
 
 sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
-				      sc_pm_power_mode_t mode,
-				      sc_pm_wake_src_t wake_src)
+	sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REQ_CPU_LOW_POWER_MODE;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U8(&msg, 2U) = (uint8_t)mode;
-	RPC_U8(&msg, 3U) = (uint8_t)wake_src;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_REQ_CPU_LOW_POWER_MODE);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U8(&msg, 2U) = U8(mode);
+	RPC_U8(&msg, 3U) = U8(wake_src);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -167,17 +185,17 @@
 }
 
 sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource,
-				   sc_faddr_t address)
+	sc_faddr_t address)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CPU_RESUME_ADDR;
-	RPC_U32(&msg, 0U) = (uint32_t)(address >> 32U);
-	RPC_U32(&msg, 4U) = (uint32_t)address;
-	RPC_U16(&msg, 8U) = (uint16_t)resource;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_SET_CPU_RESUME_ADDR);
+	RPC_U32(&msg, 0U) = U32(address >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(address);
+	RPC_U16(&msg, 8U) = U16(resource);
 	RPC_SIZE(&msg) = 4U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -187,18 +205,18 @@
 }
 
 sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource,
-			      sc_bool_t isPrimary, sc_faddr_t address)
+	sc_bool_t isPrimary, sc_faddr_t address)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CPU_RESUME;
-	RPC_U32(&msg, 0U) = (uint32_t)(address >> 32U);
-	RPC_U32(&msg, 4U) = (uint32_t)address;
-	RPC_U16(&msg, 8U) = (uint16_t)resource;
-	RPC_U8(&msg, 10U) = (uint8_t)isPrimary;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_SET_CPU_RESUME);
+	RPC_U32(&msg, 0U) = U32(address >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(address);
+	RPC_U16(&msg, 8U) = U16(resource);
+	RPC_U8(&msg, 10U) = B2U8(isPrimary);
 	RPC_SIZE(&msg) = 4U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -208,20 +226,18 @@
 }
 
 sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
-				     sc_pm_sys_if_t sys_if,
-				     sc_pm_power_mode_t hpm,
-				     sc_pm_power_mode_t lpm)
+	sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REQ_SYS_IF_POWER_MODE;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U8(&msg, 2U) = (uint8_t)sys_if;
-	RPC_U8(&msg, 3U) = (uint8_t)hpm;
-	RPC_U8(&msg, 4U) = (uint8_t)lpm;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_REQ_SYS_IF_POWER_MODE);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U8(&msg, 2U) = U8(sys_if);
+	RPC_U8(&msg, 3U) = U8(hpm);
+	RPC_U8(&msg, 4U) = U8(lpm);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -231,17 +247,17 @@
 }
 
 sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
-			      sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
+	sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CLOCK_RATE;
-	RPC_U32(&msg, 0U) = *(uint32_t *)rate;
-	RPC_U16(&msg, 4U) = (uint16_t)resource;
-	RPC_U8(&msg, 6U) = (uint8_t)clk;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_SET_CLOCK_RATE);
+	RPC_U32(&msg, 0U) = *PTR_U32(rate);
+	RPC_U16(&msg, 4U) = U16(resource);
+	RPC_U8(&msg, 6U) = U8(clk);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -252,41 +268,40 @@
 }
 
 sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
-			      sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
+	sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_CLOCK_RATE;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U8(&msg, 2U) = (uint8_t)clk;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_GET_CLOCK_RATE);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U8(&msg, 2U) = U8(clk);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (rate != NULL) {
-		*rate = RPC_U32(&msg, 0U);
-	}
+	if (rate != NULL)
+	    *rate = RPC_U32(&msg, 0U);
 
 	result = RPC_R8(&msg);
 	return (sc_err_t)result;
 }
 
 sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
-			    sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog)
+	sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_CLOCK_ENABLE;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U8(&msg, 2U) = (uint8_t)clk;
-	RPC_U8(&msg, 3U) = (uint8_t)enable;
-	RPC_U8(&msg, 4U) = (uint8_t)autog;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_CLOCK_ENABLE);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U8(&msg, 2U) = U8(clk);
+	RPC_U8(&msg, 3U) = B2U8(enable);
+	RPC_U8(&msg, 4U) = B2U8(autog);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -296,17 +311,17 @@
 }
 
 sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
-				sc_pm_clk_t clk, sc_pm_clk_parent_t parent)
+	sc_pm_clk_t clk, sc_pm_clk_parent_t parent)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CLOCK_PARENT;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U8(&msg, 2U) = (uint8_t)clk;
-	RPC_U8(&msg, 3U) = (uint8_t)parent;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_SET_CLOCK_PARENT);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U8(&msg, 2U) = U8(clk);
+	RPC_U8(&msg, 3U) = U8(parent);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -316,24 +331,23 @@
 }
 
 sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
-				sc_pm_clk_t clk, sc_pm_clk_parent_t *parent)
+	sc_pm_clk_t clk, sc_pm_clk_parent_t *parent)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_CLOCK_PARENT;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U8(&msg, 2U) = (uint8_t)clk;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_GET_CLOCK_PARENT);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U8(&msg, 2U) = U8(clk);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	if (parent != NULL) {
-		*parent = RPC_U8(&msg, 0U);
-	}
+	if (parent != NULL)
+	    *parent = RPC_U8(&msg, 0U);
 
 	return (sc_err_t)result;
 }
@@ -344,9 +358,9 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_RESET;
-	RPC_U8(&msg, 0U) = (uint8_t)type;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_RESET);
+	RPC_U8(&msg, 0U) = U8(type);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -361,36 +375,54 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_RESET_REASON;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_RESET_REASON);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	if (reason != NULL) {
-		*reason = RPC_U8(&msg, 0U);
-	}
+	if (reason != NULL)
+	    *reason = RPC_U8(&msg, 0U);
 
 	return (sc_err_t)result;
 }
 
-sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
-		    sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
-		    sc_rsrc_t resource_mu, sc_rsrc_t resource_dev)
+sc_err_t sc_pm_get_reset_part(sc_ipc_t ipc, sc_rm_pt_t *pt)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_BOOT;
-	RPC_U32(&msg, 0U) = (uint32_t)(boot_addr >> 32U);
-	RPC_U32(&msg, 4U) = (uint32_t)boot_addr;
-	RPC_U16(&msg, 8U) = (uint16_t)resource_cpu;
-	RPC_U16(&msg, 10U) = (uint16_t)resource_mu;
-	RPC_U16(&msg, 12U) = (uint16_t)resource_dev;
-	RPC_U8(&msg, 14U) = (uint8_t)pt;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_GET_RESET_PART);
+	RPC_SIZE(&msg) = 1U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	if (pt != NULL)
+	    *pt = RPC_U8(&msg, 0U);
+
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
+	sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
+	sc_rsrc_t resource_mu, sc_rsrc_t resource_dev)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_BOOT);
+	RPC_U32(&msg, 0U) = U32(boot_addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(boot_addr);
+	RPC_U16(&msg, 8U) = U16(resource_cpu);
+	RPC_U16(&msg, 10U) = U16(resource_mu);
+	RPC_U16(&msg, 12U) = U16(resource_dev);
+	RPC_U8(&msg, 14U) = U8(pt);
 	RPC_SIZE(&msg) = 5U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -404,27 +436,42 @@
 	sc_rpc_msg_t msg;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REBOOT;
-	RPC_U8(&msg, 0U) = (uint8_t)type;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_REBOOT);
+	RPC_U8(&msg, 0U) = U8(type);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_TRUE);
-
-	return;
 }
 
 sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
-				sc_pm_reset_type_t type)
+	sc_pm_reset_type_t type)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REBOOT_PARTITION;
-	RPC_U8(&msg, 0U) = (uint8_t)pt;
-	RPC_U8(&msg, 1U) = (uint8_t)type;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_REBOOT_PARTITION);
+	RPC_U8(&msg, 0U) = U8(pt);
+	RPC_U8(&msg, 1U) = U8(type);
+	RPC_SIZE(&msg) = 2U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_pm_reboot_continue(sc_ipc_t ipc, sc_rm_pt_t pt)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_REBOOT_CONTINUE);
+	RPC_U8(&msg, 0U) = U8(pt);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -434,18 +481,18 @@
 }
 
 sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
-			 sc_faddr_t address)
+	sc_faddr_t address)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
-	RPC_FUNC(&msg) = (uint8_t)PM_FUNC_CPU_START;
-	RPC_U32(&msg, 0U) = (uint32_t)(address >> 32U);
-	RPC_U32(&msg, 4U) = (uint32_t)address;
-	RPC_U16(&msg, 8U) = (uint16_t)resource;
-	RPC_U8(&msg, 10U) = (uint8_t)enable;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_CPU_START);
+	RPC_U32(&msg, 0U) = U32(address >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(address);
+	RPC_U16(&msg, 8U) = U16(resource);
+	RPC_U8(&msg, 10U) = B2U8(enable);
 	RPC_SIZE(&msg) = 4U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -454,4 +501,37 @@
 	return (sc_err_t)result;
 }
 
+void sc_pm_cpu_reset(sc_ipc_t ipc, sc_rsrc_t resource, sc_faddr_t address)
+{
+	sc_rpc_msg_t msg;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_CPU_RESET);
+	RPC_U32(&msg, 0U) = U32(address >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(address);
+	RPC_U16(&msg, 8U) = U16(resource);
+	RPC_SIZE(&msg) = 4U;
+
+	sc_call_rpc(ipc, &msg, SC_TRUE);
+}
+
+sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt)
+{
+	sc_rpc_msg_t msg;
+	sc_bool_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = U8(PM_FUNC_IS_PARTITION_STARTED);
+	RPC_U8(&msg, 0U) = U8(pt);
+	RPC_SIZE(&msg) = 2U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = U2B(RPC_R8(&msg));
+	return result;
+}
+
 /**@}*/
+
diff --git a/plat/imx/common/sci/svc/pm/sci_pm_rpc.h b/plat/imx/common/sci/svc/pm/sci_pm_rpc.h
index 19ab6e4..a03e30e 100644
--- a/plat/imx/common/sci/svc/pm/sci_pm_rpc.h
+++ b/plat/imx/common/sci/svc/pm/sci_pm_rpc.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,28 +23,33 @@
  * @name Defines for RPC PM function calls
  */
 /*@{*/
-#define PM_FUNC_UNKNOWN 0	/* Unknown function */
-#define PM_FUNC_SET_SYS_POWER_MODE 19U	/* Index for pm_set_sys_power_mode() RPC call */
-#define PM_FUNC_SET_PARTITION_POWER_MODE 1U	/* Index for pm_set_partition_power_mode() RPC call */
-#define PM_FUNC_GET_SYS_POWER_MODE 2U	/* Index for pm_get_sys_power_mode() RPC call */
-#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U	/* Index for pm_set_resource_power_mode() RPC call */
-#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U	/* Index for pm_get_resource_power_mode() RPC call */
-#define PM_FUNC_REQ_LOW_POWER_MODE 16U	/* Index for pm_req_low_power_mode() RPC call */
-#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U	/* Index for pm_req_cpu_low_power_mode() RPC call */
-#define PM_FUNC_SET_CPU_RESUME_ADDR 17U	/* Index for pm_set_cpu_resume_addr() RPC call */
-#define PM_FUNC_SET_CPU_RESUME 21U	/* Index for pm_set_cpu_resume() RPC call */
-#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U	/* Index for pm_req_sys_if_power_mode() RPC call */
-#define PM_FUNC_SET_CLOCK_RATE 5U	/* Index for pm_set_clock_rate() RPC call */
-#define PM_FUNC_GET_CLOCK_RATE 6U	/* Index for pm_get_clock_rate() RPC call */
-#define PM_FUNC_CLOCK_ENABLE 7U	/* Index for pm_clock_enable() RPC call */
-#define PM_FUNC_SET_CLOCK_PARENT 14U	/* Index for pm_set_clock_parent() RPC call */
-#define PM_FUNC_GET_CLOCK_PARENT 15U	/* Index for pm_get_clock_parent() RPC call */
-#define PM_FUNC_RESET 13U	/* Index for pm_reset() RPC call */
-#define PM_FUNC_RESET_REASON 10U	/* Index for pm_reset_reason() RPC call */
-#define PM_FUNC_BOOT 8U		/* Index for pm_boot() RPC call */
-#define PM_FUNC_REBOOT 9U	/* Index for pm_reboot() RPC call */
-#define PM_FUNC_REBOOT_PARTITION 12U	/* Index for pm_reboot_partition() RPC call */
-#define PM_FUNC_CPU_START 11U	/* Index for pm_cpu_start() RPC call */
+#define PM_FUNC_UNKNOWN 0 /* Unknown function */
+#define PM_FUNC_SET_SYS_POWER_MODE 19U /* Index for pm_set_sys_power_mode() RPC call */
+#define PM_FUNC_SET_PARTITION_POWER_MODE 1U /* Index for pm_set_partition_power_mode() RPC call */
+#define PM_FUNC_GET_SYS_POWER_MODE 2U /* Index for pm_get_sys_power_mode() RPC call */
+#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U /* Index for pm_set_resource_power_mode() RPC call */
+#define PM_FUNC_SET_RESOURCE_POWER_MODE_ALL 22U /* Index for pm_set_resource_power_mode_all() RPC call */
+#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U /* Index for pm_get_resource_power_mode() RPC call */
+#define PM_FUNC_REQ_LOW_POWER_MODE 16U /* Index for pm_req_low_power_mode() RPC call */
+#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U /* Index for pm_req_cpu_low_power_mode() RPC call */
+#define PM_FUNC_SET_CPU_RESUME_ADDR 17U /* Index for pm_set_cpu_resume_addr() RPC call */
+#define PM_FUNC_SET_CPU_RESUME 21U /* Index for pm_set_cpu_resume() RPC call */
+#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U /* Index for pm_req_sys_if_power_mode() RPC call */
+#define PM_FUNC_SET_CLOCK_RATE 5U /* Index for pm_set_clock_rate() RPC call */
+#define PM_FUNC_GET_CLOCK_RATE 6U /* Index for pm_get_clock_rate() RPC call */
+#define PM_FUNC_CLOCK_ENABLE 7U /* Index for pm_clock_enable() RPC call */
+#define PM_FUNC_SET_CLOCK_PARENT 14U /* Index for pm_set_clock_parent() RPC call */
+#define PM_FUNC_GET_CLOCK_PARENT 15U /* Index for pm_get_clock_parent() RPC call */
+#define PM_FUNC_RESET 13U /* Index for pm_reset() RPC call */
+#define PM_FUNC_RESET_REASON 10U /* Index for pm_reset_reason() RPC call */
+#define PM_FUNC_GET_RESET_PART 26U /* Index for pm_get_reset_part() RPC call */
+#define PM_FUNC_BOOT 8U /* Index for pm_boot() RPC call */
+#define PM_FUNC_REBOOT 9U /* Index for pm_reboot() RPC call */
+#define PM_FUNC_REBOOT_PARTITION 12U /* Index for pm_reboot_partition() RPC call */
+#define PM_FUNC_REBOOT_CONTINUE 25U /* Index for pm_reboot_continue() RPC call */
+#define PM_FUNC_CPU_START 11U /* Index for pm_cpu_start() RPC call */
+#define PM_FUNC_CPU_RESET 23U /* Index for pm_cpu_reset() RPC call */
+#define PM_FUNC_IS_PARTITION_STARTED 24U /* Index for pm_is_partition_started() RPC call */
 /*@}*/
 
 /* Types */
@@ -56,16 +62,9 @@
  * @param[in]     caller_pt   caller partition
  * @param[in]     msg         pointer to RPC message
  */
-void pm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
+void pm_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg);
 
-/*!
- * This function translates and dispatches an PM RPC request.
- *
- * @param[in]     ipc         IPC handle
- * @param[in]     msg         pointer to RPC message
- */
-void pm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
-
-#endif				/* SC_PM_RPC_H */
+#endif /* SC_PM_RPC_H */
 
 /**@}*/
+
diff --git a/plat/imx/common/sci/svc/rm/rm_rpc_clnt.c b/plat/imx/common/sci/svc/rm/rm_rpc_clnt.c
index 230956c..fe76ab3 100644
--- a/plat/imx/common/sci/svc/rm/rm_rpc_clnt.c
+++ b/plat/imx/common/sci/svc/rm/rm_rpc_clnt.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,8 +18,8 @@
 #include <sci/sci_types.h>
 #include <sci/svc/rm/sci_rm_api.h>
 #include <sci/sci_rpc.h>
-#include <stdlib.h>
 #include "sci_rm_rpc.h"
+#include <stdlib.h>
 
 /* Local Defines */
 
@@ -27,28 +28,26 @@
 /* Local Functions */
 
 sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
-			       sc_bool_t isolated, sc_bool_t restricted,
-			       sc_bool_t grant, sc_bool_t coherent)
+	sc_bool_t isolated, sc_bool_t restricted, sc_bool_t grant, sc_bool_t coherent)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_ALLOC;
-	RPC_U8(&msg, 0U) = (uint8_t)secure;
-	RPC_U8(&msg, 1U) = (uint8_t)isolated;
-	RPC_U8(&msg, 2U) = (uint8_t)restricted;
-	RPC_U8(&msg, 3U) = (uint8_t)grant;
-	RPC_U8(&msg, 4U) = (uint8_t)coherent;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_ALLOC);
+	RPC_U8(&msg, 0U) = B2U8(secure);
+	RPC_U8(&msg, 1U) = B2U8(isolated);
+	RPC_U8(&msg, 2U) = B2U8(restricted);
+	RPC_U8(&msg, 3U) = B2U8(grant);
+	RPC_U8(&msg, 4U) = B2U8(coherent);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	if (pt != NULL) {
-		*pt = RPC_U8(&msg, 0U);
-	}
+	if (pt != NULL)
+	    *pt = RPC_U8(&msg, 0U);
 
 	return (sc_err_t)result;
 }
@@ -59,10 +58,10 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_CONFIDENTIAL;
-	RPC_U8(&msg, 0U) = (uint8_t)pt;
-	RPC_U8(&msg, 1U) = (uint8_t)retro;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_SET_CONFIDENTIAL);
+	RPC_U8(&msg, 0U) = U8(pt);
+	RPC_U8(&msg, 1U) = B2U8(retro);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -77,9 +76,9 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_FREE;
-	RPC_U8(&msg, 0U) = (uint8_t)pt;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_FREE);
+	RPC_U8(&msg, 0U) = U8(pt);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -94,26 +93,27 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_DID;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_GET_DID);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	return (sc_rm_did_t) result;
+	return (sc_rm_did_t)result;
 }
 
-sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_did_t did)
+sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt,
+	sc_rm_did_t did)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_STATIC;
-	RPC_U8(&msg, 0U) = (uint8_t)pt;
-	RPC_U8(&msg, 1U) = (uint8_t)did;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_STATIC);
+	RPC_U8(&msg, 0U) = U8(pt);
+	RPC_U8(&msg, 1U) = U8(did);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -128,9 +128,9 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_LOCK;
-	RPC_U8(&msg, 0U) = (uint8_t)pt;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_LOCK);
+	RPC_U8(&msg, 0U) = U8(pt);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -145,30 +145,30 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_PARTITION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_GET_PARTITION);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	if (pt != NULL) {
-		*pt = RPC_U8(&msg, 0U);
-	}
+	if (pt != NULL)
+	    *pt = RPC_U8(&msg, 0U);
 
 	return (sc_err_t)result;
 }
 
-sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent)
+sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt,
+	sc_rm_pt_t pt_parent)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_PARENT;
-	RPC_U8(&msg, 0U) = (uint8_t)pt;
-	RPC_U8(&msg, 1U) = (uint8_t)pt_parent;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_SET_PARENT);
+	RPC_U8(&msg, 0U) = U8(pt);
+	RPC_U8(&msg, 1U) = U8(pt_parent);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -178,18 +178,18 @@
 }
 
 sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
-			sc_bool_t move_rsrc, sc_bool_t move_pads)
+	sc_bool_t move_rsrc, sc_bool_t move_pads)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MOVE_ALL;
-	RPC_U8(&msg, 0U) = (uint8_t)pt_src;
-	RPC_U8(&msg, 1U) = (uint8_t)pt_dst;
-	RPC_U8(&msg, 2U) = (uint8_t)move_rsrc;
-	RPC_U8(&msg, 3U) = (uint8_t)move_pads;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_MOVE_ALL);
+	RPC_U8(&msg, 0U) = U8(pt_src);
+	RPC_U8(&msg, 1U) = U8(pt_dst);
+	RPC_U8(&msg, 2U) = B2U8(move_rsrc);
+	RPC_U8(&msg, 3U) = B2U8(move_pads);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -198,16 +198,17 @@
 	return (sc_err_t)result;
 }
 
-sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource)
+sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt,
+	sc_rsrc_t resource)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_ASSIGN_RESOURCE;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U8(&msg, 2U) = (uint8_t)pt;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_ASSIGN_RESOURCE);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U8(&msg, 2U) = U8(pt);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -217,17 +218,17 @@
 }
 
 sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
-				    sc_rsrc_t resource_lst, sc_bool_t movable)
+	sc_rsrc_t resource_lst, sc_bool_t movable)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_RESOURCE_MOVABLE;
-	RPC_U16(&msg, 0U) = (uint16_t)resource_fst;
-	RPC_U16(&msg, 2U) = (uint16_t)resource_lst;
-	RPC_U8(&msg, 4U) = (uint8_t)movable;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_SET_RESOURCE_MOVABLE);
+	RPC_U16(&msg, 0U) = U16(resource_fst);
+	RPC_U16(&msg, 2U) = U16(resource_lst);
+	RPC_U8(&msg, 4U) = B2U8(movable);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -237,16 +238,16 @@
 }
 
 sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
-				       sc_bool_t movable)
+	sc_bool_t movable)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_SUBSYS_RSRC_MOVABLE;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U8(&msg, 2U) = (uint8_t)movable;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_SET_SUBSYS_RSRC_MOVABLE);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U8(&msg, 2U) = B2U8(movable);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -256,19 +257,18 @@
 }
 
 sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource,
-				     sc_rm_spa_t sa, sc_rm_spa_t pa,
-				     sc_bool_t smmu_bypass)
+	sc_rm_spa_t sa, sc_rm_spa_t pa, sc_bool_t smmu_bypass)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_MASTER_ATTRIBUTES;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U8(&msg, 2U) = (uint8_t)sa;
-	RPC_U8(&msg, 3U) = (uint8_t)pa;
-	RPC_U8(&msg, 4U) = (uint8_t)smmu_bypass;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_SET_MASTER_ATTRIBUTES);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U8(&msg, 2U) = U8(sa);
+	RPC_U8(&msg, 3U) = U8(pa);
+	RPC_U8(&msg, 4U) = B2U8(smmu_bypass);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -277,16 +277,17 @@
 	return (sc_err_t)result;
 }
 
-sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid)
+sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource,
+	sc_rm_sid_t sid)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_MASTER_SID;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U16(&msg, 2U) = (uint16_t)sid;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_SET_MASTER_SID);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U16(&msg, 2U) = U16(sid);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -296,17 +297,17 @@
 }
 
 sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
-					  sc_rm_pt_t pt, sc_rm_perm_t perm)
+	sc_rm_pt_t pt, sc_rm_perm_t perm)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_PERIPHERAL_PERMISSIONS;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
-	RPC_U8(&msg, 2U) = (uint8_t)pt;
-	RPC_U8(&msg, 3U) = (uint8_t)perm;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_SET_PERIPHERAL_PERMISSIONS);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_U8(&msg, 2U) = U8(pt);
+	RPC_U8(&msg, 3U) = U8(perm);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -318,124 +319,165 @@
 sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource)
 {
 	sc_rpc_msg_t msg;
+	sc_bool_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_IS_RESOURCE_OWNED);
+	RPC_U16(&msg, 0U) = U16(resource);
+	RPC_SIZE(&msg) = 2U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = U2B(RPC_R8(&msg));
+	return result;
+}
+
+sc_err_t sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource,
+	sc_rm_pt_t *pt)
+{
+	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_RESOURCE_OWNED;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_GET_RESOURCE_OWNER);
+	RPC_U16(&msg, 0U) = U16(resource);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	return (sc_bool_t)result;
+	if (pt != NULL)
+	    *pt = RPC_U8(&msg, 0U);
+
+	return (sc_err_t)result;
 }
 
 sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource)
 {
 	sc_rpc_msg_t msg;
-	uint8_t result;
+	sc_bool_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_RESOURCE_MASTER;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_IS_RESOURCE_MASTER);
+	RPC_U16(&msg, 0U) = U16(resource);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	result = RPC_R8(&msg);
-	return (sc_bool_t)result;
+	result = U2B(RPC_R8(&msg));
+	return result;
 }
 
 sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource)
 {
 	sc_rpc_msg_t msg;
-	uint8_t result;
+	sc_bool_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_RESOURCE_PERIPHERAL;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_IS_RESOURCE_PERIPHERAL);
+	RPC_U16(&msg, 0U) = U16(resource);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	result = RPC_R8(&msg);
-	return (sc_bool_t)result;
+	result = U2B(RPC_R8(&msg));
+	return result;
 }
 
 sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource,
-				 sc_rm_sid_t *sid)
+	sc_rm_sid_t *sid)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_RESOURCE_INFO;
-	RPC_U16(&msg, 0U) = (uint16_t)resource;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_GET_RESOURCE_INFO);
+	RPC_U16(&msg, 0U) = U16(resource);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (sid != NULL) {
-		*sid = RPC_U16(&msg, 0U);
-	}
+	if (sid != NULL)
+	    *sid = RPC_U16(&msg, 0U);
 
 	result = RPC_R8(&msg);
 	return (sc_err_t)result;
 }
 
 sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr,
-			    sc_faddr_t addr_start, sc_faddr_t addr_end)
+	sc_faddr_t addr_start, sc_faddr_t addr_end)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MEMREG_ALLOC;
-	RPC_U32(&msg, 0U) = (uint32_t)(addr_start >> 32U);
-	RPC_U32(&msg, 4U) = (uint32_t)addr_start;
-	RPC_U32(&msg, 8U) = (uint32_t)(addr_end >> 32U);
-	RPC_U32(&msg, 12U) = (uint32_t)addr_end;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_ALLOC);
+	RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr_start);
+	RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL);
+	RPC_U32(&msg, 12U) = U32(addr_end);
 	RPC_SIZE(&msg) = 5U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	if (mr != NULL) {
-		*mr = RPC_U8(&msg, 0U);
-	}
+	if (mr != NULL)
+	    *mr = RPC_U8(&msg, 0U);
 
 	return (sc_err_t)result;
 }
 
 sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr,
-			    sc_rm_mr_t *mr_ret, sc_faddr_t addr_start,
-			    sc_faddr_t addr_end)
+	sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MEMREG_SPLIT;
-	RPC_U32(&msg, 0U) = (uint32_t)(addr_start >> 32U);
-	RPC_U32(&msg, 4U) = (uint32_t)addr_start;
-	RPC_U32(&msg, 8U) = (uint32_t)(addr_end >> 32U);
-	RPC_U32(&msg, 12U) = (uint32_t)addr_end;
-	RPC_U8(&msg, 16U) = (uint8_t)mr;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_SPLIT);
+	RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr_start);
+	RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL);
+	RPC_U32(&msg, 12U) = U32(addr_end);
+	RPC_U8(&msg, 16U) = U8(mr);
 	RPC_SIZE(&msg) = 6U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	if (mr_ret != NULL) {
-		*mr_ret = RPC_U8(&msg, 0U);
-	}
+	if (mr_ret != NULL)
+	    *mr_ret = RPC_U8(&msg, 0U);
+
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_rm_memreg_frag(sc_ipc_t ipc, sc_rm_mr_t *mr_ret,
+	sc_faddr_t addr_start, sc_faddr_t addr_end)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_FRAG);
+	RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr_start);
+	RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL);
+	RPC_U32(&msg, 12U) = U32(addr_end);
+	RPC_SIZE(&msg) = 5U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	if (mr_ret != NULL)
+	    *mr_ret = RPC_U8(&msg, 0U);
 
 	return (sc_err_t)result;
 }
@@ -446,9 +488,9 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MEMREG_FREE;
-	RPC_U8(&msg, 0U) = (uint8_t)mr;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_FREE);
+	RPC_U8(&msg, 0U) = U8(mr);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -458,26 +500,25 @@
 }
 
 sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr,
-			   sc_faddr_t addr_start, sc_faddr_t addr_end)
+	sc_faddr_t addr_start, sc_faddr_t addr_end)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_FIND_MEMREG;
-	RPC_U32(&msg, 0U) = (uint32_t)(addr_start >> 32U);
-	RPC_U32(&msg, 4U) = (uint32_t)addr_start;
-	RPC_U32(&msg, 8U) = (uint32_t)(addr_end >> 32U);
-	RPC_U32(&msg, 12U) = (uint32_t)addr_end;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_FIND_MEMREG);
+	RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr_start);
+	RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL);
+	RPC_U32(&msg, 12U) = U32(addr_end);
 	RPC_SIZE(&msg) = 5U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
 	result = RPC_R8(&msg);
-	if (mr != NULL) {
-		*mr = RPC_U8(&msg, 0U);
-	}
+	if (mr != NULL)
+	    *mr = RPC_U8(&msg, 0U);
 
 	return (sc_err_t)result;
 }
@@ -488,10 +529,10 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_ASSIGN_MEMREG;
-	RPC_U8(&msg, 0U) = (uint8_t)pt;
-	RPC_U8(&msg, 1U) = (uint8_t)mr;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_ASSIGN_MEMREG);
+	RPC_U8(&msg, 0U) = U8(pt);
+	RPC_U8(&msg, 1U) = U8(mr);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -501,17 +542,17 @@
 }
 
 sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
-				      sc_rm_pt_t pt, sc_rm_perm_t perm)
+	sc_rm_pt_t pt, sc_rm_perm_t perm)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_MEMREG_PERMISSIONS;
-	RPC_U8(&msg, 0U) = (uint8_t)mr;
-	RPC_U8(&msg, 1U) = (uint8_t)pt;
-	RPC_U8(&msg, 2U) = (uint8_t)perm;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_SET_MEMREG_PERMISSIONS);
+	RPC_U8(&msg, 0U) = U8(mr);
+	RPC_U8(&msg, 1U) = U8(pt);
+	RPC_U8(&msg, 2U) = U8(perm);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -523,43 +564,39 @@
 sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
 {
 	sc_rpc_msg_t msg;
-	uint8_t result;
+	sc_bool_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_MEMREG_OWNED;
-	RPC_U8(&msg, 0U) = (uint8_t)mr;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_IS_MEMREG_OWNED);
+	RPC_U8(&msg, 0U) = U8(mr);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	result = RPC_R8(&msg);
-	return (sc_bool_t)result;
+	result = U2B(RPC_R8(&msg));
+	return result;
 }
 
 sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr,
-			       sc_faddr_t *addr_start, sc_faddr_t *addr_end)
+	sc_faddr_t *addr_start, sc_faddr_t *addr_end)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_MEMREG_INFO;
-	RPC_U8(&msg, 0U) = (uint8_t)mr;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_GET_MEMREG_INFO);
+	RPC_U8(&msg, 0U) = U8(mr);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (addr_start != NULL) {
-		*addr_start =
-		    ((uint64_t) RPC_U32(&msg, 0U) << 32U) | RPC_U32(&msg, 4U);
-	}
+	if (addr_start != NULL)
+	    *addr_start = ((uint64_t) RPC_U32(&msg, 0U) << 32U) | RPC_U32(&msg, 4U);
 
-	if (addr_end != NULL) {
-		*addr_end =
-		    ((uint64_t) RPC_U32(&msg, 8U) << 32U) | RPC_U32(&msg, 12U);
-	}
+	if (addr_end != NULL)
+	    *addr_end = ((uint64_t) RPC_U32(&msg, 8U) << 32U) | RPC_U32(&msg, 12U);
 
 	result = RPC_R8(&msg);
 	return (sc_err_t)result;
@@ -571,10 +608,10 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_ASSIGN_PAD;
-	RPC_U16(&msg, 0U) = (uint16_t)pad;
-	RPC_U8(&msg, 2U) = (uint8_t)pt;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_ASSIGN_PAD);
+	RPC_U16(&msg, 0U) = U16(pad);
+	RPC_U8(&msg, 2U) = U8(pt);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -584,17 +621,17 @@
 }
 
 sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
-			       sc_pad_t pad_lst, sc_bool_t movable)
+	sc_pad_t pad_lst, sc_bool_t movable)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_PAD_MOVABLE;
-	RPC_U16(&msg, 0U) = (uint16_t)pad_fst;
-	RPC_U16(&msg, 2U) = (uint16_t)pad_lst;
-	RPC_U8(&msg, 4U) = (uint8_t)movable;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_SET_PAD_MOVABLE);
+	RPC_U16(&msg, 0U) = U16(pad_fst);
+	RPC_U16(&msg, 2U) = U16(pad_lst);
+	RPC_U8(&msg, 4U) = B2U8(movable);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -606,18 +643,18 @@
 sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad)
 {
 	sc_rpc_msg_t msg;
-	uint8_t result;
+	sc_bool_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_PAD_OWNED;
-	RPC_U8(&msg, 0U) = (uint8_t)pad;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_IS_PAD_OWNED);
+	RPC_U8(&msg, 0U) = U8(pad);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	result = RPC_R8(&msg);
-	return (sc_bool_t)result;
+	result = U2B(RPC_R8(&msg));
+	return result;
 }
 
 void sc_rm_dump(sc_ipc_t ipc)
@@ -625,13 +662,12 @@
 	sc_rpc_msg_t msg;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
-	RPC_FUNC(&msg) = (uint8_t)RM_FUNC_DUMP;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
+	RPC_FUNC(&msg) = U8(RM_FUNC_DUMP);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
-
-	return;
 }
 
 /**@}*/
+
diff --git a/plat/imx/common/sci/svc/rm/sci_rm_rpc.h b/plat/imx/common/sci/svc/rm/sci_rm_rpc.h
index e3de450..af72556 100644
--- a/plat/imx/common/sci/svc/rm/sci_rm_rpc.h
+++ b/plat/imx/common/sci/svc/rm/sci_rm_rpc.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,38 +23,40 @@
  * @name Defines for RPC RM function calls
  */
 /*@{*/
-#define RM_FUNC_UNKNOWN 0	/* Unknown function */
-#define RM_FUNC_PARTITION_ALLOC 1U	/* Index for rm_partition_alloc() RPC call */
-#define RM_FUNC_SET_CONFIDENTIAL 31U	/* Index for rm_set_confidential() RPC call */
-#define RM_FUNC_PARTITION_FREE 2U	/* Index for rm_partition_free() RPC call */
-#define RM_FUNC_GET_DID 26U	/* Index for rm_get_did() RPC call */
-#define RM_FUNC_PARTITION_STATIC 3U	/* Index for rm_partition_static() RPC call */
-#define RM_FUNC_PARTITION_LOCK 4U	/* Index for rm_partition_lock() RPC call */
-#define RM_FUNC_GET_PARTITION 5U	/* Index for rm_get_partition() RPC call */
-#define RM_FUNC_SET_PARENT 6U	/* Index for rm_set_parent() RPC call */
-#define RM_FUNC_MOVE_ALL 7U	/* Index for rm_move_all() RPC call */
-#define RM_FUNC_ASSIGN_RESOURCE 8U	/* Index for rm_assign_resource() RPC call */
-#define RM_FUNC_SET_RESOURCE_MOVABLE 9U	/* Index for rm_set_resource_movable() RPC call */
-#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U	/* Index for rm_set_subsys_rsrc_movable() RPC call */
-#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U	/* Index for rm_set_master_attributes() RPC call */
-#define RM_FUNC_SET_MASTER_SID 11U	/* Index for rm_set_master_sid() RPC call */
-#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U	/* Index for rm_set_peripheral_permissions() RPC call */
-#define RM_FUNC_IS_RESOURCE_OWNED 13U	/* Index for rm_is_resource_owned() RPC call */
-#define RM_FUNC_IS_RESOURCE_MASTER 14U	/* Index for rm_is_resource_master() RPC call */
-#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U	/* Index for rm_is_resource_peripheral() RPC call */
-#define RM_FUNC_GET_RESOURCE_INFO 16U	/* Index for rm_get_resource_info() RPC call */
-#define RM_FUNC_MEMREG_ALLOC 17U	/* Index for rm_memreg_alloc() RPC call */
-#define RM_FUNC_MEMREG_SPLIT 29U	/* Index for rm_memreg_split() RPC call */
-#define RM_FUNC_MEMREG_FREE 18U	/* Index for rm_memreg_free() RPC call */
-#define RM_FUNC_FIND_MEMREG 30U	/* Index for rm_find_memreg() RPC call */
-#define RM_FUNC_ASSIGN_MEMREG 19U	/* Index for rm_assign_memreg() RPC call */
-#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U	/* Index for rm_set_memreg_permissions() RPC call */
-#define RM_FUNC_IS_MEMREG_OWNED 21U	/* Index for rm_is_memreg_owned() RPC call */
-#define RM_FUNC_GET_MEMREG_INFO 22U	/* Index for rm_get_memreg_info() RPC call */
-#define RM_FUNC_ASSIGN_PAD 23U	/* Index for rm_assign_pad() RPC call */
-#define RM_FUNC_SET_PAD_MOVABLE 24U	/* Index for rm_set_pad_movable() RPC call */
-#define RM_FUNC_IS_PAD_OWNED 25U	/* Index for rm_is_pad_owned() RPC call */
-#define RM_FUNC_DUMP 27U	/* Index for rm_dump() RPC call */
+#define RM_FUNC_UNKNOWN 0 /* Unknown function */
+#define RM_FUNC_PARTITION_ALLOC 1U /* Index for rm_partition_alloc() RPC call */
+#define RM_FUNC_SET_CONFIDENTIAL 31U /* Index for rm_set_confidential() RPC call */
+#define RM_FUNC_PARTITION_FREE 2U /* Index for rm_partition_free() RPC call */
+#define RM_FUNC_GET_DID 26U /* Index for rm_get_did() RPC call */
+#define RM_FUNC_PARTITION_STATIC 3U /* Index for rm_partition_static() RPC call */
+#define RM_FUNC_PARTITION_LOCK 4U /* Index for rm_partition_lock() RPC call */
+#define RM_FUNC_GET_PARTITION 5U /* Index for rm_get_partition() RPC call */
+#define RM_FUNC_SET_PARENT 6U /* Index for rm_set_parent() RPC call */
+#define RM_FUNC_MOVE_ALL 7U /* Index for rm_move_all() RPC call */
+#define RM_FUNC_ASSIGN_RESOURCE 8U /* Index for rm_assign_resource() RPC call */
+#define RM_FUNC_SET_RESOURCE_MOVABLE 9U /* Index for rm_set_resource_movable() RPC call */
+#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U /* Index for rm_set_subsys_rsrc_movable() RPC call */
+#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U /* Index for rm_set_master_attributes() RPC call */
+#define RM_FUNC_SET_MASTER_SID 11U /* Index for rm_set_master_sid() RPC call */
+#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U /* Index for rm_set_peripheral_permissions() RPC call */
+#define RM_FUNC_IS_RESOURCE_OWNED 13U /* Index for rm_is_resource_owned() RPC call */
+#define RM_FUNC_GET_RESOURCE_OWNER 33U /* Index for rm_get_resource_owner() RPC call */
+#define RM_FUNC_IS_RESOURCE_MASTER 14U /* Index for rm_is_resource_master() RPC call */
+#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U /* Index for rm_is_resource_peripheral() RPC call */
+#define RM_FUNC_GET_RESOURCE_INFO 16U /* Index for rm_get_resource_info() RPC call */
+#define RM_FUNC_MEMREG_ALLOC 17U /* Index for rm_memreg_alloc() RPC call */
+#define RM_FUNC_MEMREG_SPLIT 29U /* Index for rm_memreg_split() RPC call */
+#define RM_FUNC_MEMREG_FRAG 32U /* Index for rm_memreg_frag() RPC call */
+#define RM_FUNC_MEMREG_FREE 18U /* Index for rm_memreg_free() RPC call */
+#define RM_FUNC_FIND_MEMREG 30U /* Index for rm_find_memreg() RPC call */
+#define RM_FUNC_ASSIGN_MEMREG 19U /* Index for rm_assign_memreg() RPC call */
+#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U /* Index for rm_set_memreg_permissions() RPC call */
+#define RM_FUNC_IS_MEMREG_OWNED 21U /* Index for rm_is_memreg_owned() RPC call */
+#define RM_FUNC_GET_MEMREG_INFO 22U /* Index for rm_get_memreg_info() RPC call */
+#define RM_FUNC_ASSIGN_PAD 23U /* Index for rm_assign_pad() RPC call */
+#define RM_FUNC_SET_PAD_MOVABLE 24U /* Index for rm_set_pad_movable() RPC call */
+#define RM_FUNC_IS_PAD_OWNED 25U /* Index for rm_is_pad_owned() RPC call */
+#define RM_FUNC_DUMP 27U /* Index for rm_dump() RPC call */
 /*@}*/
 
 /* Types */
@@ -66,16 +69,9 @@
  * @param[in]     caller_pt   caller partition
  * @param[in]     msg         pointer to RPC message
  */
-void rm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
+void rm_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg);
 
-/*!
- * This function translates and dispatches an RM RPC request.
- *
- * @param[in]     ipc         IPC handle
- * @param[in]     msg         pointer to RPC message
- */
-void rm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
-
-#endif				/* SC_RM_RPC_H */
+#endif /* SC_RM_RPC_H */
 
 /**@}*/
+
diff --git a/plat/imx/common/sci/svc/seco/sci_seco_rpc.h b/plat/imx/common/sci/svc/seco/sci_seco_rpc.h
new file mode 100644
index 0000000..840a29d
--- /dev/null
+++ b/plat/imx/common/sci/svc/seco/sci_seco_rpc.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*!
+ * Header file for the SECO RPC implementation.
+ *
+ * @addtogroup SECO_SVC
+ * @{
+ */
+
+#ifndef SC_SECO_RPC_H
+#define SC_SECO_RPC_H
+
+/* Includes */
+
+/* Defines */
+
+/*!
+ * @name Defines for RPC SECO function calls
+ */
+/*@{*/
+#define SECO_FUNC_UNKNOWN 0 /* Unknown function */
+#define SECO_FUNC_IMAGE_LOAD 1U /* Index for seco_image_load() RPC call */
+#define SECO_FUNC_AUTHENTICATE 2U /* Index for seco_authenticate() RPC call */
+#define SECO_FUNC_FORWARD_LIFECYCLE 3U /* Index for seco_forward_lifecycle() RPC call */
+#define SECO_FUNC_RETURN_LIFECYCLE 4U /* Index for seco_return_lifecycle() RPC call */
+#define SECO_FUNC_COMMIT 5U /* Index for seco_commit() RPC call */
+#define SECO_FUNC_ATTEST_MODE 6U /* Index for seco_attest_mode() RPC call */
+#define SECO_FUNC_ATTEST 7U /* Index for seco_attest() RPC call */
+#define SECO_FUNC_GET_ATTEST_PKEY 8U /* Index for seco_get_attest_pkey() RPC call */
+#define SECO_FUNC_GET_ATTEST_SIGN 9U /* Index for seco_get_attest_sign() RPC call */
+#define SECO_FUNC_ATTEST_VERIFY 10U /* Index for seco_attest_verify() RPC call */
+#define SECO_FUNC_GEN_KEY_BLOB 11U /* Index for seco_gen_key_blob() RPC call */
+#define SECO_FUNC_LOAD_KEY 12U /* Index for seco_load_key() RPC call */
+#define SECO_FUNC_GET_MP_KEY 13U /* Index for seco_get_mp_key() RPC call */
+#define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */
+#define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */
+#define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */
+#define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */
+#define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */
+#define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */
+#define SECO_FUNC_FUSE_WRITE 20U /* Index for seco_fuse_write() RPC call */
+/*@}*/
+
+/* Types */
+
+/* Functions */
+
+/*!
+ * This function dispatches an incoming SECO RPC request.
+ *
+ * @param[in]     caller_pt   caller partition
+ * @param[in]     msg         pointer to RPC message
+ */
+void seco_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg);
+
+#endif /* SC_SECO_RPC_H */
+
+/**@}*/
+
diff --git a/plat/imx/common/sci/svc/seco/seco_rpc_clnt.c b/plat/imx/common/sci/svc/seco/seco_rpc_clnt.c
new file mode 100644
index 0000000..33092d6
--- /dev/null
+++ b/plat/imx/common/sci/svc/seco/seco_rpc_clnt.c
@@ -0,0 +1,429 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*!
+ * File containing client-side RPC functions for the SECO service. These
+ * functions are ported to clients that communicate to the SC.
+ *
+ * @addtogroup SECO_SVC
+ * @{
+ */
+
+/* Includes */
+
+#include <sci/sci_types.h>
+#include <sci/svc/rm/sci_rm_api.h>
+#include <sci/svc/seco/sci_seco_api.h>
+#include <sci/sci_rpc.h>
+#include "sci_seco_rpc.h"
+#include <stdlib.h>
+
+/* Local Defines */
+
+/* Local Types */
+
+/* Local Functions */
+
+sc_err_t sc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src,
+	sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_IMAGE_LOAD);
+	RPC_U32(&msg, 0U) = U32(addr_src >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr_src);
+	RPC_U32(&msg, 8U) = U32(addr_dst >> 32ULL);
+	RPC_U32(&msg, 12U) = U32(addr_dst);
+	RPC_U32(&msg, 16U) = U32(len);
+	RPC_U8(&msg, 20U) = B2U8(fw);
+	RPC_SIZE(&msg) = 7U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_authenticate(sc_ipc_t ipc,
+	sc_seco_auth_cmd_t cmd, sc_faddr_t addr)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_AUTHENTICATE);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
+	RPC_U8(&msg, 8U) = U8(cmd);
+	RPC_SIZE(&msg) = 4U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t change)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_FORWARD_LIFECYCLE);
+	RPC_U32(&msg, 0U) = U32(change);
+	RPC_SIZE(&msg) = 2U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_RETURN_LIFECYCLE);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
+	RPC_SIZE(&msg) = 3U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_commit(sc_ipc_t ipc, uint32_t *info)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_COMMIT);
+	RPC_U32(&msg, 0U) = *PTR_U32(info);
+	RPC_SIZE(&msg) = 2U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	*info = RPC_U32(&msg, 0U);
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_ATTEST_MODE);
+	RPC_U32(&msg, 0U) = U32(mode);
+	RPC_SIZE(&msg) = 2U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_attest(sc_ipc_t ipc, uint64_t nonce)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_ATTEST);
+	RPC_U32(&msg, 0U) = U32(nonce >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(nonce);
+	RPC_SIZE(&msg) = 3U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_get_attest_pkey(sc_ipc_t ipc, sc_faddr_t addr)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_GET_ATTEST_PKEY);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
+	RPC_SIZE(&msg) = 3U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_get_attest_sign(sc_ipc_t ipc, sc_faddr_t addr)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_GET_ATTEST_SIGN);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
+	RPC_SIZE(&msg) = 3U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_attest_verify(sc_ipc_t ipc, sc_faddr_t addr)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_ATTEST_VERIFY);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
+	RPC_SIZE(&msg) = 3U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_gen_key_blob(sc_ipc_t ipc, uint32_t id,
+	sc_faddr_t load_addr, sc_faddr_t export_addr, uint16_t max_size)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_GEN_KEY_BLOB);
+	RPC_U32(&msg, 0U) = U32(load_addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(load_addr);
+	RPC_U32(&msg, 8U) = U32(export_addr >> 32ULL);
+	RPC_U32(&msg, 12U) = U32(export_addr);
+	RPC_U32(&msg, 16U) = U32(id);
+	RPC_U16(&msg, 20U) = U16(max_size);
+	RPC_SIZE(&msg) = 7U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_load_key(sc_ipc_t ipc, uint32_t id,
+	sc_faddr_t addr)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_LOAD_KEY);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
+	RPC_U32(&msg, 8U) = U32(id);
+	RPC_SIZE(&msg) = 4U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr,
+	uint16_t dst_size)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_GET_MP_KEY);
+	RPC_U32(&msg, 0U) = U32(dst_addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(dst_addr);
+	RPC_U16(&msg, 8U) = U16(dst_size);
+	RPC_SIZE(&msg) = 4U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr,
+	uint8_t size, uint8_t lock)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_UPDATE_MPMR);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
+	RPC_U8(&msg, 8U) = U8(size);
+	RPC_U8(&msg, 9U) = U8(lock);
+	RPC_SIZE(&msg) = 4U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
+	uint16_t msg_size, sc_faddr_t dst_addr, uint16_t dst_size)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_GET_MP_SIGN);
+	RPC_U32(&msg, 0U) = U32(msg_addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(msg_addr);
+	RPC_U32(&msg, 8U) = U32(dst_addr >> 32ULL);
+	RPC_U32(&msg, 12U) = U32(dst_addr);
+	RPC_U16(&msg, 16U) = U16(msg_size);
+	RPC_U16(&msg, 18U) = U16(dst_size);
+	RPC_SIZE(&msg) = 6U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+void sc_seco_build_info(sc_ipc_t ipc, uint32_t *version,
+	uint32_t *commit)
+{
+	sc_rpc_msg_t msg;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_BUILD_INFO);
+	RPC_SIZE(&msg) = 1U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	if (version != NULL)
+	    *version = RPC_U32(&msg, 0U);
+
+	if (commit != NULL)
+	    *commit = RPC_U32(&msg, 4U);
+}
+
+sc_err_t sc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc,
+	uint16_t *monotonic, uint32_t *uid_l, uint32_t *uid_h)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_CHIP_INFO);
+	RPC_SIZE(&msg) = 1U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	if (uid_l != NULL)
+	    *uid_l = RPC_U32(&msg, 0U);
+
+	if (uid_h != NULL)
+	    *uid_h = RPC_U32(&msg, 4U);
+
+	if (lc != NULL)
+	    *lc = RPC_U16(&msg, 8U);
+
+	if (monotonic != NULL)
+	    *monotonic = RPC_U16(&msg, 10U);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_ENABLE_DEBUG);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
+	RPC_SIZE(&msg) = 3U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_get_event(sc_ipc_t ipc, uint8_t idx,
+	uint32_t *event)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_GET_EVENT);
+	RPC_U8(&msg, 0U) = U8(idx);
+	RPC_SIZE(&msg) = 2U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	if (event != NULL)
+	    *event = RPC_U32(&msg, 0U);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+sc_err_t sc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr)
+{
+	sc_rpc_msg_t msg;
+	uint8_t result;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = U8(SECO_FUNC_FUSE_WRITE);
+	RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(addr);
+	RPC_SIZE(&msg) = 3U;
+
+	sc_call_rpc(ipc, &msg, SC_FALSE);
+
+	result = RPC_R8(&msg);
+	return (sc_err_t)result;
+}
+
+/**@}*/
+
diff --git a/plat/imx/common/sci/svc/timer/sci_timer_rpc.h b/plat/imx/common/sci/svc/timer/sci_timer_rpc.h
index 23d5c77..af78d66 100644
--- a/plat/imx/common/sci/svc/timer/sci_timer_rpc.h
+++ b/plat/imx/common/sci/svc/timer/sci_timer_rpc.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,25 +23,25 @@
  * @name Defines for RPC TIMER function calls
  */
 /*@{*/
-#define TIMER_FUNC_UNKNOWN 0	/* Unknown function */
-#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U	/* Index for timer_set_wdog_timeout() RPC call */
-#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U	/* Index for timer_set_wdog_pre_timeout() RPC call */
-#define TIMER_FUNC_START_WDOG 2U	/* Index for timer_start_wdog() RPC call */
-#define TIMER_FUNC_STOP_WDOG 3U	/* Index for timer_stop_wdog() RPC call */
-#define TIMER_FUNC_PING_WDOG 4U	/* Index for timer_ping_wdog() RPC call */
-#define TIMER_FUNC_GET_WDOG_STATUS 5U	/* Index for timer_get_wdog_status() RPC call */
-#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U	/* Index for timer_pt_get_wdog_status() RPC call */
-#define TIMER_FUNC_SET_WDOG_ACTION 10U	/* Index for timer_set_wdog_action() RPC call */
-#define TIMER_FUNC_SET_RTC_TIME 6U	/* Index for timer_set_rtc_time() RPC call */
-#define TIMER_FUNC_GET_RTC_TIME 7U	/* Index for timer_get_rtc_time() RPC call */
-#define TIMER_FUNC_GET_RTC_SEC1970 9U	/* Index for timer_get_rtc_sec1970() RPC call */
-#define TIMER_FUNC_SET_RTC_ALARM 8U	/* Index for timer_set_rtc_alarm() RPC call */
-#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U	/* Index for timer_set_rtc_periodic_alarm() RPC call */
-#define TIMER_FUNC_CANCEL_RTC_ALARM 15U	/* Index for timer_cancel_rtc_alarm() RPC call */
-#define TIMER_FUNC_SET_RTC_CALB 11U	/* Index for timer_set_rtc_calb() RPC call */
-#define TIMER_FUNC_SET_SYSCTR_ALARM 16U	/* Index for timer_set_sysctr_alarm() RPC call */
-#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U	/* Index for timer_set_sysctr_periodic_alarm() RPC call */
-#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U	/* Index for timer_cancel_sysctr_alarm() RPC call */
+#define TIMER_FUNC_UNKNOWN 0 /* Unknown function */
+#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for timer_set_wdog_timeout() RPC call */
+#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for timer_set_wdog_pre_timeout() RPC call */
+#define TIMER_FUNC_START_WDOG 2U /* Index for timer_start_wdog() RPC call */
+#define TIMER_FUNC_STOP_WDOG 3U /* Index for timer_stop_wdog() RPC call */
+#define TIMER_FUNC_PING_WDOG 4U /* Index for timer_ping_wdog() RPC call */
+#define TIMER_FUNC_GET_WDOG_STATUS 5U /* Index for timer_get_wdog_status() RPC call */
+#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /* Index for timer_pt_get_wdog_status() RPC call */
+#define TIMER_FUNC_SET_WDOG_ACTION 10U /* Index for timer_set_wdog_action() RPC call */
+#define TIMER_FUNC_SET_RTC_TIME 6U /* Index for timer_set_rtc_time() RPC call */
+#define TIMER_FUNC_GET_RTC_TIME 7U /* Index for timer_get_rtc_time() RPC call */
+#define TIMER_FUNC_GET_RTC_SEC1970 9U /* Index for timer_get_rtc_sec1970() RPC call */
+#define TIMER_FUNC_SET_RTC_ALARM 8U /* Index for timer_set_rtc_alarm() RPC call */
+#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /* Index for timer_set_rtc_periodic_alarm() RPC call */
+#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /* Index for timer_cancel_rtc_alarm() RPC call */
+#define TIMER_FUNC_SET_RTC_CALB 11U /* Index for timer_set_rtc_calb() RPC call */
+#define TIMER_FUNC_SET_SYSCTR_ALARM 16U /* Index for timer_set_sysctr_alarm() RPC call */
+#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for timer_set_sysctr_periodic_alarm() RPC call */
+#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for timer_cancel_sysctr_alarm() RPC call */
 /*@}*/
 
 /* Types */
@@ -54,16 +54,9 @@
  * @param[in]     caller_pt   caller partition
  * @param[in]     msg         pointer to RPC message
  */
-void timer_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
+void timer_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg);
 
-/*!
- * This function translates and dispatches an TIMER RPC request.
- *
- * @param[in]     ipc         IPC handle
- * @param[in]     msg         pointer to RPC message
- */
-void timer_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
-
-#endif				/* SC_TIMER_RPC_H */
+#endif /* SC_TIMER_RPC_H */
 
 /**@}*/
+
diff --git a/plat/imx/common/sci/svc/timer/timer_rpc_clnt.c b/plat/imx/common/sci/svc/timer/timer_rpc_clnt.c
index 0f9acee..176a66a 100644
--- a/plat/imx/common/sci/svc/timer/timer_rpc_clnt.c
+++ b/plat/imx/common/sci/svc/timer/timer_rpc_clnt.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2019 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,8 +19,8 @@
 #include <sci/svc/rm/sci_rm_api.h>
 #include <sci/svc/timer/sci_timer_api.h>
 #include <sci/sci_rpc.h>
-#include <stdlib.h>
 #include "sci_timer_rpc.h"
+#include <stdlib.h>
 
 /* Local Defines */
 
@@ -28,15 +28,16 @@
 
 /* Local Functions */
 
-sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, sc_timer_wdog_time_t timeout)
+sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc,
+	sc_timer_wdog_time_t timeout)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_WDOG_TIMEOUT;
-	RPC_U32(&msg, 0U) = (uint32_t)timeout;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_WDOG_TIMEOUT);
+	RPC_U32(&msg, 0U) = U32(timeout);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -46,15 +47,15 @@
 }
 
 sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc,
-				       sc_timer_wdog_time_t pre_timeout)
+	sc_timer_wdog_time_t pre_timeout)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_WDOG_PRE_TIMEOUT;
-	RPC_U32(&msg, 0U) = (uint32_t)pre_timeout;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_WDOG_PRE_TIMEOUT);
+	RPC_U32(&msg, 0U) = U32(pre_timeout);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -69,9 +70,9 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_START_WDOG;
-	RPC_U8(&msg, 0U) = (uint8_t)lock;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_START_WDOG);
+	RPC_U8(&msg, 0U) = B2U8(lock);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -86,8 +87,8 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_STOP_WDOG;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_STOP_WDOG);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -102,8 +103,8 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_PING_WDOG;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_PING_WDOG);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -113,79 +114,70 @@
 }
 
 sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc,
-				  sc_timer_wdog_time_t *timeout,
-				  sc_timer_wdog_time_t *max_timeout,
-				  sc_timer_wdog_time_t *remaining_time)
+	sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout,
+	sc_timer_wdog_time_t *remaining_time)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_GET_WDOG_STATUS;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_GET_WDOG_STATUS);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (timeout != NULL) {
-		*timeout = RPC_U32(&msg, 0U);
-	}
+	if (timeout != NULL)
+	    *timeout = RPC_U32(&msg, 0U);
 
-	if (max_timeout != NULL) {
-		*max_timeout = RPC_U32(&msg, 4U);
-	}
+	if (max_timeout != NULL)
+	    *max_timeout = RPC_U32(&msg, 4U);
 
-	if (remaining_time != NULL) {
-		*remaining_time = RPC_U32(&msg, 8U);
-	}
+	if (remaining_time != NULL)
+	    *remaining_time = RPC_U32(&msg, 8U);
 
 	result = RPC_R8(&msg);
 	return (sc_err_t)result;
 }
 
-sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt,
-				     sc_bool_t *enb,
-				     sc_timer_wdog_time_t *timeout,
-				     sc_timer_wdog_time_t *remaining_time)
+sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t *enb,
+	sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *remaining_time)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_PT_GET_WDOG_STATUS;
-	RPC_U8(&msg, 0U) = (uint8_t)pt;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_PT_GET_WDOG_STATUS);
+	RPC_U8(&msg, 0U) = U8(pt);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (timeout != NULL) {
-		*timeout = RPC_U32(&msg, 0U);
-	}
+	if (timeout != NULL)
+	    *timeout = RPC_U32(&msg, 0U);
 
-	if (remaining_time != NULL) {
-		*remaining_time = RPC_U32(&msg, 4U);
-	}
+	if (remaining_time != NULL)
+	    *remaining_time = RPC_U32(&msg, 4U);
 
 	result = RPC_R8(&msg);
-	if (enb != NULL) {
-		*enb = RPC_U8(&msg, 8U);
-	}
+	if (enb != NULL)
+	    *enb = U2B(RPC_U8(&msg, 8U));
 
 	return (sc_err_t)result;
 }
 
 sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc,
-				  sc_rm_pt_t pt, sc_timer_wdog_action_t action)
+	sc_rm_pt_t pt, sc_timer_wdog_action_t action)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_WDOG_ACTION;
-	RPC_U8(&msg, 0U) = (uint8_t)pt;
-	RPC_U8(&msg, 1U) = (uint8_t)action;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_WDOG_ACTION);
+	RPC_U8(&msg, 0U) = U8(pt);
+	RPC_U8(&msg, 1U) = U8(action);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -195,21 +187,20 @@
 }
 
 sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon,
-			       uint8_t day, uint8_t hour, uint8_t min,
-			       uint8_t sec)
+	uint8_t day, uint8_t hour, uint8_t min, uint8_t sec)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_RTC_TIME;
-	RPC_U16(&msg, 0U) = (uint16_t)year;
-	RPC_U8(&msg, 2U) = (uint8_t)mon;
-	RPC_U8(&msg, 3U) = (uint8_t)day;
-	RPC_U8(&msg, 4U) = (uint8_t)hour;
-	RPC_U8(&msg, 5U) = (uint8_t)min;
-	RPC_U8(&msg, 6U) = (uint8_t)sec;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_TIME);
+	RPC_U16(&msg, 0U) = U16(year);
+	RPC_U8(&msg, 2U) = U8(mon);
+	RPC_U8(&msg, 3U) = U8(day);
+	RPC_U8(&msg, 4U) = U8(hour);
+	RPC_U8(&msg, 5U) = U8(min);
+	RPC_U8(&msg, 6U) = U8(sec);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -219,43 +210,36 @@
 }
 
 sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon,
-			       uint8_t *day, uint8_t *hour, uint8_t *min,
-			       uint8_t *sec)
+	uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_GET_RTC_TIME;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_GET_RTC_TIME);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (year != NULL) {
-		*year = RPC_U16(&msg, 0U);
-	}
+	if (year != NULL)
+	    *year = RPC_U16(&msg, 0U);
 
 	result = RPC_R8(&msg);
-	if (mon != NULL) {
-		*mon = RPC_U8(&msg, 2U);
-	}
+	if (mon != NULL)
+	    *mon = RPC_U8(&msg, 2U);
 
-	if (day != NULL) {
-		*day = RPC_U8(&msg, 3U);
-	}
+	if (day != NULL)
+	    *day = RPC_U8(&msg, 3U);
 
-	if (hour != NULL) {
-		*hour = RPC_U8(&msg, 4U);
-	}
+	if (hour != NULL)
+	    *hour = RPC_U8(&msg, 4U);
 
-	if (min != NULL) {
-		*min = RPC_U8(&msg, 5U);
-	}
+	if (min != NULL)
+	    *min = RPC_U8(&msg, 5U);
 
-	if (sec != NULL) {
-		*sec = RPC_U8(&msg, 6U);
-	}
+	if (sec != NULL)
+	    *sec = RPC_U8(&msg, 6U);
 
 	return (sc_err_t)result;
 }
@@ -266,36 +250,34 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_GET_RTC_SEC1970;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_GET_RTC_SEC1970);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
 
-	if (sec != NULL) {
-		*sec = RPC_U32(&msg, 0U);
-	}
+	if (sec != NULL)
+	    *sec = RPC_U32(&msg, 0U);
 
 	result = RPC_R8(&msg);
 	return (sc_err_t)result;
 }
 
 sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon,
-				uint8_t day, uint8_t hour, uint8_t min,
-				uint8_t sec)
+	uint8_t day, uint8_t hour, uint8_t min, uint8_t sec)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_RTC_ALARM;
-	RPC_U16(&msg, 0U) = (uint16_t)year;
-	RPC_U8(&msg, 2U) = (uint8_t)mon;
-	RPC_U8(&msg, 3U) = (uint8_t)day;
-	RPC_U8(&msg, 4U) = (uint8_t)hour;
-	RPC_U8(&msg, 5U) = (uint8_t)min;
-	RPC_U8(&msg, 6U) = (uint8_t)sec;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_ALARM);
+	RPC_U16(&msg, 0U) = U16(year);
+	RPC_U8(&msg, 2U) = U8(mon);
+	RPC_U8(&msg, 3U) = U8(day);
+	RPC_U8(&msg, 4U) = U8(hour);
+	RPC_U8(&msg, 5U) = U8(min);
+	RPC_U8(&msg, 6U) = U8(sec);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -310,9 +292,9 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_RTC_PERIODIC_ALARM;
-	RPC_U32(&msg, 0U) = (uint32_t)sec;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_PERIODIC_ALARM);
+	RPC_U32(&msg, 0U) = U32(sec);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -327,8 +309,8 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_CANCEL_RTC_ALARM;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_CANCEL_RTC_ALARM);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -343,9 +325,9 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_RTC_CALB;
-	RPC_I8(&msg, 0U) = (int8_t) count;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_CALB);
+	RPC_I8(&msg, 0U) = I8(count);
 	RPC_SIZE(&msg) = 2U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -360,10 +342,10 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_SYSCTR_ALARM;
-	RPC_U32(&msg, 0U) = (uint32_t)(ticks >> 32U);
-	RPC_U32(&msg, 4U) = (uint32_t)ticks;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_SYSCTR_ALARM);
+	RPC_U32(&msg, 0U) = U32(ticks >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(ticks);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -372,16 +354,17 @@
 	return (sc_err_t)result;
 }
 
-sc_err_t sc_timer_set_sysctr_periodic_alarm(sc_ipc_t ipc, uint64_t ticks)
+sc_err_t sc_timer_set_sysctr_periodic_alarm(sc_ipc_t ipc,
+	uint64_t ticks)
 {
 	sc_rpc_msg_t msg;
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM;
-	RPC_U32(&msg, 0U) = (uint32_t)(ticks >> 32U);
-	RPC_U32(&msg, 4U) = (uint32_t)ticks;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM);
+	RPC_U32(&msg, 0U) = U32(ticks >> 32ULL);
+	RPC_U32(&msg, 4U) = U32(ticks);
 	RPC_SIZE(&msg) = 3U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -396,8 +379,8 @@
 	uint8_t result;
 
 	RPC_VER(&msg) = SC_RPC_VERSION;
-	RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
-	RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_CANCEL_SYSCTR_ALARM;
+	RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = U8(TIMER_FUNC_CANCEL_SYSCTR_ALARM);
 	RPC_SIZE(&msg) = 1U;
 
 	sc_call_rpc(ipc, &msg, SC_FALSE);
@@ -407,3 +390,4 @@
 }
 
 /**@}*/
+