diff --git a/plat/imx/imx8mm/gpc.c b/plat/imx/imx8mm/gpc.c
index b2c4832..cd1d45c 100644
--- a/plat/imx/imx8mm/gpc.c
+++ b/plat/imx/imx8mm/gpc.c
@@ -188,6 +188,7 @@
 	IMX_PD_DOMAIN(VPU_G2),
 };
 
+static uint32_t gpc_wake_irqs[4] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, };
 static uint32_t gpc_imr_offset[] = { 0x30, 0x40, 0x1c0, 0x1d0, };
 /* save gic dist&redist context when NOC wrapper is power down */
 static struct plat_gic_ctx imx_gicv3_ctx;
@@ -585,7 +586,7 @@
 	/* clear last core's IMR based on GIC's mask setting */
 	for (int i = 0; i < 4; i++) {
 		if (pdn)
-			irq_mask = ~dist_ctx->gicd_isenabler[i];
+			irq_mask = ~dist_ctx->gicd_isenabler[i] | gpc_wake_irqs[i];
 		else
 			irq_mask = IMR_MASK_ALL;
 
@@ -594,6 +595,16 @@
 	}
 }
 
+static void imx_gpc_set_wake_irq(uint32_t hwirq, uint32_t on)
+{
+	uint32_t mask, idx;
+
+	mask = 1 << hwirq % 32;
+	idx = hwirq / 32;
+	gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] & ~mask :
+				 gpc_wake_irqs[idx] | mask;
+}
+
 static void imx_gpc_pm_domain_enable(uint32_t domain_id, uint32_t on)
 {
 	uint32_t val;
@@ -750,6 +761,9 @@
 	case FSL_SIP_CONFIG_GPC_PM_DOMAIN:
 		imx_gpc_pm_domain_enable(x2, x3);
 		break;
+	case FSL_SIP_CONFIG_GPC_SET_WAKE:
+		imx_gpc_set_wake_irq(x2, x3);
+		break;
 	default:
 		return SMC_UNK;
 	}