diff --git a/plat/imx/imx8mm/gpc.c b/plat/imx/imx8mm/gpc.c
index e02eaa7..0517e14 100644
--- a/plat/imx/imx8mm/gpc.c
+++ b/plat/imx/imx8mm/gpc.c
@@ -158,7 +158,7 @@
 #define COREx_PGC_PCR(core_id)	(0x800 + core_id * 0x40)
 #define COREx_WFI_PDN(core_id)	(1 << (core_id < 2 ? core_id * 2 : (core_id - 2) * 2 + 16))
 #define COREx_IRQ_WUP(core_id)	(core_id < 2 ? (1 << (core_id * 2 + 8)) : (1 << (core_id * 2 + 20)));
-#define LPM_MODE(local_state)	(local_state == PLAT_WAIT_OFF_STATE ? A53_LPM_WAIT : A53_LPM_STOP)
+#define LPM_MODE(local_state)	(local_state == PLAT_WAIT_RET_STATE ? A53_LPM_WAIT : A53_LPM_STOP)
 #define A53_CORE_WUP_SRC(core_id) (1 << (core_id < 2 ? 28 + core_id : 22 + core_id - 2))
 
 #define IMR_MASK_ALL		0xffffffff
@@ -379,7 +379,7 @@
 {
 	uint32_t val;
 
-	if (is_local_state_off(power_state)) {
+	if (!is_local_state_run(power_state)) {
 
 		/* config A53 cluster LPM mode */
 		val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
@@ -395,7 +395,13 @@
 		/* enable PLAT/SCU power down */
 		val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD);
 		val &= ~EN_L2_WFI_PDN;
-		val |= (L2PGE | EN_PLAT_PDN);
+
+		/* L2 cache memory is on in WAIT mode */
+		if (is_local_state_off(power_state))
+			val |= (L2PGE | EN_PLAT_PDN);
+		else
+			val |= EN_PLAT_PDN;
+
 		mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val);
 
 		/* config SLOT for PLAT power up/down */
diff --git a/plat/imx/imx8mm/imx8mm_psci.c b/plat/imx/imx8mm/imx8mm_psci.c
index 721e1a4..001e0e0 100644
--- a/plat/imx/imx8mm/imx8mm_psci.c
+++ b/plat/imx/imx8mm/imx8mm_psci.c
@@ -79,7 +79,7 @@
 
 	if (pwr_type == PSTATE_TYPE_POWERDOWN && state_id == 0x33) {
 		CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE;
-		CLUSTER_PWR_STATE(req_state) = PLAT_WAIT_OFF_STATE;
+		CLUSTER_PWR_STATE(req_state) = PLAT_WAIT_RET_STATE;
 	}
 
 	return PSCI_E_SUCCESS;
@@ -116,10 +116,8 @@
 		isb();
 	}
 
-	if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) {
+	if (!is_local_state_run(CLUSTER_PWR_STATE(target_state)))
 		imx_set_cluster_powerdown(core_id, CLUSTER_PWR_STATE(target_state));
-	} else
-		imx_set_cluster_standby(true);
 
 	/* do system level power mode setting */
 	if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
@@ -147,10 +145,8 @@
 	}
 
 	/* check the cluster level power status */
-	if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) {
+	if (!is_local_state_run(CLUSTER_PWR_STATE(target_state)))
 		imx_set_cluster_powerdown(core_id, PSCI_LOCAL_STATE_RUN);
-	} else
-		imx_set_cluster_standby(false);
 
 	/* check the core level power status */
 	if (is_local_state_off(CORE_PWR_STATE(target_state))) {
diff --git a/plat/imx/imx8mm/include/platform_def.h b/plat/imx/imx8mm/include/platform_def.h
index 28b8d06..74ddb59 100644
--- a/plat/imx/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8mm/include/platform_def.h
@@ -18,9 +18,9 @@
 #define PWR_DOMAIN_AT_MAX_LVL		1
 #define PLAT_MAX_PWR_LVL		2
 #define PLAT_MAX_OFF_STATE		4
-#define PLAT_MAX_RET_STATE		1
+#define PLAT_MAX_RET_STATE		2
 
-#define PLAT_WAIT_OFF_STATE		2
+#define PLAT_WAIT_RET_STATE		1
 #define PLAT_STOP_OFF_STATE		3
 
 #define BL31_BASE			0x920000