diff --git a/plat/imx/common/imx8m/dram.c b/plat/imx/common/imx8m/dram.c
new file mode 100644
index 0000000..e5a40c8
--- /dev/null
+++ b/plat/imx/common/imx8m/dram.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <ddrc.h>
+#include <dram.h>
+#include <mmio.h>
+
+static struct dram_info *dram_info;
+
+void dram_cfg_save(struct dram_cfg_param *params, int params_num)
+{
+	for (int idx = 0;  idx < params_num; idx++) {
+		params->cfg = mmio_read_32(params->reg);
+		params++;
+	}
+}
+
+void dram_cfg_restore(struct dram_cfg_param *params, int params_num)
+{
+	for (int idx = 0; idx < params_num; idx++) {
+		mmio_write_32(params->reg, params->cfg);
+		params++;
+	}
+}
+
+/* restore the ddrc config */
+void dram_umctl2_init(void)
+{
+	struct dram_cfg_param *params = dram_info->ddrc_cfg;
+	int params_num = dram_info->ddrc_cfg_num;
+
+	dram_cfg_restore(params, params_num);
+	mmio_write_32(DDRC_DBG1(0), 0x1);
+	mmio_write_32(DDRC_DFIMISC(0), 0x11);
+	mmio_write_32(DDRC_DFIUPD0(0),0xE0400018); 
+}
+
+/* resotre the dram phy config */
+void dram_phy_init(void)
+{
+	struct dram_cfg_param *ddrphy_params = dram_info->ddrphy_cfg;
+	int params_num = dram_info->ddrphy_cfg_num;
+
+	/* retore the phy config */
+	mmio_write_32(DDRPHY_REG(0xd0000), 0x0);
+	dram_cfg_restore(ddrphy_params, params_num);
+	mmio_write_32(DDRPHY_REG(0xd0000), 0x1);
+
+	/* load the PIE image */
+	ddrphy_load_pie_image();
+}
+
+void dram_info_init(void)
+{
+	uint32_t current_fsp, ddr_type;
+
+	/* get the dram type */
+	ddr_type = mmio_read_32(DDRC_MSTR(0)) & DDR_TYPE_MASK;
+
+	if (ddr_type == DDRC_LPDDR4) {
+		dram_info = &imx8m_lpddr4_dram_info;
+		dram_info->dram_type = ddr_type;
+	}
+
+	/* init the boot_fsp & current_fsp */
+	current_fsp = mmio_read_32(DDRC_DFIMISC(0));
+	current_fsp = (current_fsp >> 8) & 0xf;
+	dram_info->boot_fsp = current_fsp;
+	dram_info->current_fsp = current_fsp;
+
+	/* save the ddrc config */
+	dram_cfg_save(dram_info->ddrc_cfg, dram_info->ddrc_cfg_num);
+
+	/* save dram phy config */
+	mmio_write_32(DDRPHY_REG(0xd0000), 0x0);
+	mmio_write_32(DDRPHY_REG(0xc0080), 0x3);
+	dram_cfg_save(dram_info->ddrphy_cfg, dram_info->ddrphy_cfg_num);
+	mmio_write_32(DDRPHY_REG(0xc0080), 0x0);
+	mmio_write_32(DDRPHY_REG(0xd0000), 0x1);
+}
+
+void dram_enter_retention(void)
+{
+	/* TODO add the ddr4 support in the furture */
+	if (dram_info->dram_type == DDRC_LPDDR4)
+		lpddr4_enter_retention();
+}
+
+void dram_exit_retention(void)
+{
+	/* TODO add the ddr4 support in the furture */
+	if (dram_info->dram_type == DDRC_LPDDR4)
+		lpddr4_exit_retention();
+}
diff --git a/plat/imx/common/imx8m/lpddr4_phy_pie.c b/plat/imx/common/imx8m/lpddr4_phy_pie.c
new file mode 100644
index 0000000..ad87443
--- /dev/null
+++ b/plat/imx/common/imx8m/lpddr4_phy_pie.c
@@ -0,0 +1,593 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <dram.h>
+#include <mmio.h>
+
+struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ .reg = DDRPHY_REG(0xd0000),	.cfg = 0x0},
+
+	{ .reg = DDRPHY_REG(0x90000),	.cfg = 0x10},
+	{ .reg = DDRPHY_REG(0x90001),	.cfg = 0x400},
+	{ .reg = DDRPHY_REG(0x90002),	.cfg = 0x10e},
+	{ .reg = DDRPHY_REG(0x90003),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x90004),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x90005),	.cfg = 0x8},
+	{ .reg = DDRPHY_REG(0x90029),	.cfg = 0xb},
+	{ .reg = DDRPHY_REG(0x9002a),	.cfg = 0x480},
+	{ .reg = DDRPHY_REG(0x9002b),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x9002c),	.cfg = 0x8},
+	{ .reg = DDRPHY_REG(0x9002d),	.cfg = 0x448},
+	{ .reg = DDRPHY_REG(0x9002e),	.cfg = 0x139},
+	{ .reg = DDRPHY_REG(0x9002f),	.cfg = 0x8},
+	{ .reg = DDRPHY_REG(0x90030),	.cfg = 0x478},
+	{ .reg = DDRPHY_REG(0x90031),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x90032),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x90033),	.cfg = 0xe8},
+	{ .reg = DDRPHY_REG(0x90034),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x90035),	.cfg = 0x2},
+	{ .reg = DDRPHY_REG(0x90036),	.cfg = 0x10},
+	{ .reg = DDRPHY_REG(0x90037),	.cfg = 0x139},
+	{ .reg = DDRPHY_REG(0x90038),	.cfg = 0xf},
+	{ .reg = DDRPHY_REG(0x90039),	.cfg = 0x7c0},
+	{ .reg = DDRPHY_REG(0x9003a),	.cfg = 0x139},
+	{ .reg = DDRPHY_REG(0x9003b),	.cfg = 0x44},
+	{ .reg = DDRPHY_REG(0x9003c),	.cfg = 0x630},
+	{ .reg = DDRPHY_REG(0x9003d),	.cfg = 0x159},
+	{ .reg = DDRPHY_REG(0x9003e),	.cfg = 0x14f},
+	{ .reg = DDRPHY_REG(0x9003f),	.cfg = 0x630},
+	{ .reg = DDRPHY_REG(0x90040),	.cfg = 0x159},
+	{ .reg = DDRPHY_REG(0x90041),	.cfg = 0x47},
+	{ .reg = DDRPHY_REG(0x90042),	.cfg = 0x630},
+	{ .reg = DDRPHY_REG(0x90043),	.cfg = 0x149},
+	{ .reg = DDRPHY_REG(0x90044),	.cfg = 0x4f},
+	{ .reg = DDRPHY_REG(0x90045),	.cfg = 0x630},
+	{ .reg = DDRPHY_REG(0x90046),	.cfg = 0x179},
+	{ .reg = DDRPHY_REG(0x90047),	.cfg = 0x8},
+	{ .reg = DDRPHY_REG(0x90048),	.cfg = 0xe0},
+	{ .reg = DDRPHY_REG(0x90049),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x9004a),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x9004b),	.cfg = 0x7c8},
+	{ .reg = DDRPHY_REG(0x9004c),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x9004d),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x9004e),	.cfg = 0x1},
+	{ .reg = DDRPHY_REG(0x9004f),	.cfg = 0x8},
+	{ .reg = DDRPHY_REG(0x90050),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x90051),	.cfg = 0x45a},
+	{ .reg = DDRPHY_REG(0x90052),	.cfg = 0x9},
+	{ .reg = DDRPHY_REG(0x90053),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x90054),	.cfg = 0x448},
+	{ .reg = DDRPHY_REG(0x90055),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x90056),	.cfg = 0x40},
+	{ .reg = DDRPHY_REG(0x90057),	.cfg = 0x630},
+	{ .reg = DDRPHY_REG(0x90058),	.cfg = 0x179},
+	{ .reg = DDRPHY_REG(0x90059),	.cfg = 0x1},
+	{ .reg = DDRPHY_REG(0x9005a),	.cfg = 0x618},
+	{ .reg = DDRPHY_REG(0x9005b),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x9005c),	.cfg = 0x40c0},
+	{ .reg = DDRPHY_REG(0x9005d),	.cfg = 0x630},
+	{ .reg = DDRPHY_REG(0x9005e),	.cfg = 0x149},
+	{ .reg = DDRPHY_REG(0x9005f),	.cfg = 0x8},
+	{ .reg = DDRPHY_REG(0x90060),	.cfg = 0x4},
+	{ .reg = DDRPHY_REG(0x90061),	.cfg = 0x48},
+	{ .reg = DDRPHY_REG(0x90062),	.cfg = 0x4040},
+	{ .reg = DDRPHY_REG(0x90063),	.cfg = 0x630},
+	{ .reg = DDRPHY_REG(0x90064),	.cfg = 0x149},
+	{ .reg = DDRPHY_REG(0x90065),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x90066),	.cfg = 0x4},
+	{ .reg = DDRPHY_REG(0x90067),	.cfg = 0x48},
+	{ .reg = DDRPHY_REG(0x90068),	.cfg = 0x40},
+	{ .reg = DDRPHY_REG(0x90069),	.cfg = 0x630},
+	{ .reg = DDRPHY_REG(0x9006a),	.cfg = 0x149},
+	{ .reg = DDRPHY_REG(0x9006b),	.cfg = 0x10},
+	{ .reg = DDRPHY_REG(0x9006c),	.cfg = 0x4},
+	{ .reg = DDRPHY_REG(0x9006d),	.cfg = 0x18},
+	{ .reg = DDRPHY_REG(0x9006e),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x9006f),	.cfg = 0x4},
+	{ .reg = DDRPHY_REG(0x90070),	.cfg = 0x78},
+	{ .reg = DDRPHY_REG(0x90071),	.cfg = 0x549},
+	{ .reg = DDRPHY_REG(0x90072),	.cfg = 0x630},
+	{ .reg = DDRPHY_REG(0x90073),	.cfg = 0x159},
+	{ .reg = DDRPHY_REG(0x90074),	.cfg = 0xd49},
+	{ .reg = DDRPHY_REG(0x90075),	.cfg = 0x630},
+	{ .reg = DDRPHY_REG(0x90076),	.cfg = 0x159},
+	{ .reg = DDRPHY_REG(0x90077),	.cfg = 0x94a},
+	{ .reg = DDRPHY_REG(0x90078),	.cfg = 0x630},
+	{ .reg = DDRPHY_REG(0x90079),	.cfg = 0x159},
+	{ .reg = DDRPHY_REG(0x9007a),	.cfg = 0x441},
+	{ .reg = DDRPHY_REG(0x9007b),	.cfg = 0x630},
+	{ .reg = DDRPHY_REG(0x9007c),	.cfg = 0x149},
+	{ .reg = DDRPHY_REG(0x9007d),	.cfg = 0x42},
+	{ .reg = DDRPHY_REG(0x9007e),	.cfg = 0x630},
+	{ .reg = DDRPHY_REG(0x9007f),	.cfg = 0x149},
+	{ .reg = DDRPHY_REG(0x90080),	.cfg = 0x1},
+	{ .reg = DDRPHY_REG(0x90081),	.cfg = 0x630},
+	{ .reg = DDRPHY_REG(0x90082),	.cfg = 0x149},
+	{ .reg = DDRPHY_REG(0x90083),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x90084),	.cfg = 0xe0},
+	{ .reg = DDRPHY_REG(0x90085),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x90086),	.cfg = 0xa},
+	{ .reg = DDRPHY_REG(0x90087),	.cfg = 0x10},
+	{ .reg = DDRPHY_REG(0x90088),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x90089),	.cfg = 0x9},
+	{ .reg = DDRPHY_REG(0x9008a),	.cfg = 0x3c0},
+	{ .reg = DDRPHY_REG(0x9008b),	.cfg = 0x149},
+	{ .reg = DDRPHY_REG(0x9008c),	.cfg = 0x9},
+	{ .reg = DDRPHY_REG(0x9008d),	.cfg = 0x3c0},
+	{ .reg = DDRPHY_REG(0x9008e),	.cfg = 0x159},
+	{ .reg = DDRPHY_REG(0x9008f),	.cfg = 0x18},
+	{ .reg = DDRPHY_REG(0x90090),	.cfg = 0x10},
+	{ .reg = DDRPHY_REG(0x90091),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x90092),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x90093),	.cfg = 0x3c0},
+	{ .reg = DDRPHY_REG(0x90094),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x90095),	.cfg = 0x18},
+	{ .reg = DDRPHY_REG(0x90096),	.cfg = 0x4},
+	{ .reg = DDRPHY_REG(0x90097),	.cfg = 0x48},
+	{ .reg = DDRPHY_REG(0x90098),	.cfg = 0x18},
+	{ .reg = DDRPHY_REG(0x90099),	.cfg = 0x4},
+	{ .reg = DDRPHY_REG(0x9009a),	.cfg = 0x58},
+	{ .reg = DDRPHY_REG(0x9009b),	.cfg = 0xa},
+	{ .reg = DDRPHY_REG(0x9009c),	.cfg = 0x10},
+	{ .reg = DDRPHY_REG(0x9009d),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x9009e),	.cfg = 0x2},
+	{ .reg = DDRPHY_REG(0x9009f),	.cfg = 0x10},
+	{ .reg = DDRPHY_REG(0x900a0),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x900a1),	.cfg = 0x5},
+	{ .reg = DDRPHY_REG(0x900a2),	.cfg = 0x7c0},
+	{ .reg = DDRPHY_REG(0x900a3),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x900a4),	.cfg = 0x10},
+	{ .reg = DDRPHY_REG(0x900a5),	.cfg = 0x10},
+	{ .reg = DDRPHY_REG(0x900a6),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x40000),	.cfg = 0x811},
+	{ .reg = DDRPHY_REG(0x40020),	.cfg = 0x880},
+	{ .reg = DDRPHY_REG(0x40040),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40060),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40001),	.cfg = 0x4008},
+	{ .reg = DDRPHY_REG(0x40021),	.cfg = 0x83},
+	{ .reg = DDRPHY_REG(0x40041),	.cfg = 0x4f},
+	{ .reg = DDRPHY_REG(0x40061),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40002),	.cfg = 0x4040},
+	{ .reg = DDRPHY_REG(0x40022),	.cfg = 0x83},
+	{ .reg = DDRPHY_REG(0x40042),	.cfg = 0x51},
+	{ .reg = DDRPHY_REG(0x40062),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40003),	.cfg = 0x811},
+	{ .reg = DDRPHY_REG(0x40023),	.cfg = 0x880},
+	{ .reg = DDRPHY_REG(0x40043),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40063),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40004),	.cfg = 0x720},
+	{ .reg = DDRPHY_REG(0x40024),	.cfg = 0xf},
+	{ .reg = DDRPHY_REG(0x40044),	.cfg = 0x1740},
+	{ .reg = DDRPHY_REG(0x40064),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40005),	.cfg = 0x16},
+	{ .reg = DDRPHY_REG(0x40025),	.cfg = 0x83},
+	{ .reg = DDRPHY_REG(0x40045),	.cfg = 0x4b},
+	{ .reg = DDRPHY_REG(0x40065),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40006),	.cfg = 0x716},
+	{ .reg = DDRPHY_REG(0x40026),	.cfg = 0xf},
+	{ .reg = DDRPHY_REG(0x40046),	.cfg = 0x2001},
+	{ .reg = DDRPHY_REG(0x40066),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40007),	.cfg = 0x716},
+	{ .reg = DDRPHY_REG(0x40027),	.cfg = 0xf},
+	{ .reg = DDRPHY_REG(0x40047),	.cfg = 0x2800},
+	{ .reg = DDRPHY_REG(0x40067),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40008),	.cfg = 0x716},
+	{ .reg = DDRPHY_REG(0x40028),	.cfg = 0xf},
+	{ .reg = DDRPHY_REG(0x40048),	.cfg = 0xf00},
+	{ .reg = DDRPHY_REG(0x40068),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40009),	.cfg = 0x720},
+	{ .reg = DDRPHY_REG(0x40029),	.cfg = 0xf},
+	{ .reg = DDRPHY_REG(0x40049),	.cfg = 0x1400},
+	{ .reg = DDRPHY_REG(0x40069),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x4000a),	.cfg = 0xe08},
+	{ .reg = DDRPHY_REG(0x4002a),	.cfg = 0xc15},
+	{ .reg = DDRPHY_REG(0x4004a),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x4006a),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x4000b),	.cfg = 0x623},
+	{ .reg = DDRPHY_REG(0x4002b),	.cfg = 0x15},
+	{ .reg = DDRPHY_REG(0x4004b),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x4006b),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x4000c),	.cfg = 0x4028},
+	{ .reg = DDRPHY_REG(0x4002c),	.cfg = 0x80},
+	{ .reg = DDRPHY_REG(0x4004c),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x4006c),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x4000d),	.cfg = 0xe08},
+	{ .reg = DDRPHY_REG(0x4002d),	.cfg = 0xc1a},
+	{ .reg = DDRPHY_REG(0x4004d),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x4006d),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x4000e),	.cfg = 0x623},
+	{ .reg = DDRPHY_REG(0x4002e),	.cfg = 0x1a},
+	{ .reg = DDRPHY_REG(0x4004e),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x4006e),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x4000f),	.cfg = 0x4040},
+	{ .reg = DDRPHY_REG(0x4002f),	.cfg = 0x80},
+	{ .reg = DDRPHY_REG(0x4004f),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x4006f),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40010),	.cfg = 0x2604},
+	{ .reg = DDRPHY_REG(0x40030),	.cfg = 0x15},
+	{ .reg = DDRPHY_REG(0x40050),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40070),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40011),	.cfg = 0x708},
+	{ .reg = DDRPHY_REG(0x40031),	.cfg = 0x5},
+	{ .reg = DDRPHY_REG(0x40051),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40071),	.cfg = 0x2002},
+	{ .reg = DDRPHY_REG(0x40012),	.cfg = 0x8},
+	{ .reg = DDRPHY_REG(0x40032),	.cfg = 0x80},
+	{ .reg = DDRPHY_REG(0x40052),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40072),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40013),	.cfg = 0x2604},
+	{ .reg = DDRPHY_REG(0x40033),	.cfg = 0x1a},
+	{ .reg = DDRPHY_REG(0x40053),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40073),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40014),	.cfg = 0x708},
+	{ .reg = DDRPHY_REG(0x40034),	.cfg = 0xa},
+	{ .reg = DDRPHY_REG(0x40054),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40074),	.cfg = 0x2002},
+	{ .reg = DDRPHY_REG(0x40015),	.cfg = 0x4040},
+	{ .reg = DDRPHY_REG(0x40035),	.cfg = 0x80},
+	{ .reg = DDRPHY_REG(0x40055),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40075),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40016),	.cfg = 0x60a},
+	{ .reg = DDRPHY_REG(0x40036),	.cfg = 0x15},
+	{ .reg = DDRPHY_REG(0x40056),	.cfg = 0x1200},
+	{ .reg = DDRPHY_REG(0x40076),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40017),	.cfg = 0x61a},
+	{ .reg = DDRPHY_REG(0x40037),	.cfg = 0x15},
+	{ .reg = DDRPHY_REG(0x40057),	.cfg = 0x1300},
+	{ .reg = DDRPHY_REG(0x40077),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40018),	.cfg = 0x60a},
+	{ .reg = DDRPHY_REG(0x40038),	.cfg = 0x1a},
+	{ .reg = DDRPHY_REG(0x40058),	.cfg = 0x1200},
+	{ .reg = DDRPHY_REG(0x40078),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x40019),	.cfg = 0x642},
+	{ .reg = DDRPHY_REG(0x40039),	.cfg = 0x1a},
+	{ .reg = DDRPHY_REG(0x40059),	.cfg = 0x1300},
+	{ .reg = DDRPHY_REG(0x40079),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x4001a),	.cfg = 0x4808},
+	{ .reg = DDRPHY_REG(0x4003a),	.cfg = 0x880},
+	{ .reg = DDRPHY_REG(0x4005a),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x4007a),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x900a7),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x900a8),	.cfg = 0x790},
+	{ .reg = DDRPHY_REG(0x900a9),	.cfg = 0x11a},
+	{ .reg = DDRPHY_REG(0x900aa),	.cfg = 0x8},
+	{ .reg = DDRPHY_REG(0x900ab),	.cfg = 0x7aa},
+	{ .reg = DDRPHY_REG(0x900ac),	.cfg = 0x2a},
+	{ .reg = DDRPHY_REG(0x900ad),	.cfg = 0x10},
+	{ .reg = DDRPHY_REG(0x900ae),	.cfg = 0x7b2},
+	{ .reg = DDRPHY_REG(0x900af),	.cfg = 0x2a},
+	{ .reg = DDRPHY_REG(0x900b0),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x900b1),	.cfg = 0x7c8},
+	{ .reg = DDRPHY_REG(0x900b2),	.cfg = 0x109},
+	{ .reg = DDRPHY_REG(0x900b3),	.cfg = 0x10},
+	{ .reg = DDRPHY_REG(0x900b4),	.cfg = 0x2a8},
+	{ .reg = DDRPHY_REG(0x900b5),	.cfg = 0x129},
+	{ .reg = DDRPHY_REG(0x900b6),	.cfg = 0x8},
+	{ .reg = DDRPHY_REG(0x900b7),	.cfg = 0x370},
+	{ .reg = DDRPHY_REG(0x900b8),	.cfg = 0x129},
+	{ .reg = DDRPHY_REG(0x900b9),	.cfg = 0xa},
+	{ .reg = DDRPHY_REG(0x900ba),	.cfg = 0x3c8},
+	{ .reg = DDRPHY_REG(0x900bb),	.cfg = 0x1a9},
+	{ .reg = DDRPHY_REG(0x900bc),	.cfg = 0xc},
+	{ .reg = DDRPHY_REG(0x900bd),	.cfg = 0x408},
+	{ .reg = DDRPHY_REG(0x900be),	.cfg = 0x199},
+	{ .reg = DDRPHY_REG(0x900bf),	.cfg = 0x14},
+	{ .reg = DDRPHY_REG(0x900c0),	.cfg = 0x790},
+	{ .reg = DDRPHY_REG(0x900c1),	.cfg = 0x11a},
+	{ .reg = DDRPHY_REG(0x900c2),	.cfg = 0x8},
+	{ .reg = DDRPHY_REG(0x900c3),	.cfg = 0x4},
+	{ .reg = DDRPHY_REG(0x900c4),	.cfg = 0x18},
+	{ .reg = DDRPHY_REG(0x900c5),	.cfg = 0xe},
+	{ .reg = DDRPHY_REG(0x900c6),	.cfg = 0x408},
+	{ .reg = DDRPHY_REG(0x900c7),	.cfg = 0x199},
+	{ .reg = DDRPHY_REG(0x900c8),	.cfg = 0x8},
+	{ .reg = DDRPHY_REG(0x900c9),	.cfg = 0x8568},
+	{ .reg = DDRPHY_REG(0x900ca),	.cfg = 0x108},
+	{ .reg = DDRPHY_REG(0x900cb),	.cfg = 0x18},
+	{ .reg = DDRPHY_REG(0x900cc),	.cfg = 0x790},
+	{ .reg = DDRPHY_REG(0x900cd),	.cfg = 0x16a},
+	{ .reg = DDRPHY_REG(0x900ce),	.cfg = 0x8},
+	{ .reg = DDRPHY_REG(0x900cf),	.cfg = 0x1d8},
+	{ .reg = DDRPHY_REG(0x900d0),	.cfg = 0x169},
+	{ .reg = DDRPHY_REG(0x900d1),	.cfg = 0x10},
+	{ .reg = DDRPHY_REG(0x900d2),	.cfg = 0x8558},
+	{ .reg = DDRPHY_REG(0x900d3),	.cfg = 0x168},
+	{ .reg = DDRPHY_REG(0x900d4),	.cfg = 0x70},
+	{ .reg = DDRPHY_REG(0x900d5),	.cfg = 0x788},
+	{ .reg = DDRPHY_REG(0x900d6),	.cfg = 0x16a},
+	{ .reg = DDRPHY_REG(0x900d7),	.cfg = 0x1ff8},
+	{ .reg = DDRPHY_REG(0x900d8),	.cfg = 0x85a8},
+	{ .reg = DDRPHY_REG(0x900d9),	.cfg = 0x1e8},
+	{ .reg = DDRPHY_REG(0x900da),	.cfg = 0x50},
+	{ .reg = DDRPHY_REG(0x900db),	.cfg = 0x798},
+	{ .reg = DDRPHY_REG(0x900dc),	.cfg = 0x16a},
+	{ .reg = DDRPHY_REG(0x900dd),	.cfg = 0x60},
+	{ .reg = DDRPHY_REG(0x900de),	.cfg = 0x7a0},
+	{ .reg = DDRPHY_REG(0x900df),	.cfg = 0x16a},
+	{ .reg = DDRPHY_REG(0x900e0),	.cfg = 0x8},
+	{ .reg = DDRPHY_REG(0x900e1),	.cfg = 0x8310},
+	{ .reg = DDRPHY_REG(0x900e2),	.cfg = 0x168},
+	{ .reg = DDRPHY_REG(0x900e3),	.cfg = 0x8},
+	{ .reg = DDRPHY_REG(0x900e4),	.cfg = 0xa310},
+	{ .reg = DDRPHY_REG(0x900e5),	.cfg = 0x168},
+	{ .reg = DDRPHY_REG(0x900e6),	.cfg = 0xa},
+	{ .reg = DDRPHY_REG(0x900e7),	.cfg = 0x408},
+	{ .reg = DDRPHY_REG(0x900e8),	.cfg = 0x169},
+	{ .reg = DDRPHY_REG(0x900e9),	.cfg = 0x6e},
+	{ .reg = DDRPHY_REG(0x900ea),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x900eb),	.cfg = 0x68},
+	{ .reg = DDRPHY_REG(0x900ec),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x900ed),	.cfg = 0x408},
+	{ .reg = DDRPHY_REG(0x900ee),	.cfg = 0x169},
+	{ .reg = DDRPHY_REG(0x900ef),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x900f0),	.cfg = 0x8310},
+	{ .reg = DDRPHY_REG(0x900f1),	.cfg = 0x168},
+	{ .reg = DDRPHY_REG(0x900f2),	.cfg = 0x0},
+	{ .reg = DDRPHY_REG(0x900f3),	.cfg = 0xa310},
+	{ .reg = DDRPHY_REG(0x900f4),	.cfg = 0x168},
+	{ .reg = DDRPHY_REG(0x900f5),	.cfg = 0x1ff8}, 
+	{ .reg = DDRPHY_REG(0x900f6),	.cfg = 0x85a8}, 
+	{ .reg = DDRPHY_REG(0x900f7),	.cfg = 0x1e8}, 
+	{ .reg = DDRPHY_REG(0x900f8),	.cfg = 0x68}, 
+	{ .reg = DDRPHY_REG(0x900f9),	.cfg = 0x798}, 
+	{ .reg = DDRPHY_REG(0x900fa),	.cfg = 0x16a}, 
+	{ .reg = DDRPHY_REG(0x900fb),	.cfg = 0x78}, 
+	{ .reg = DDRPHY_REG(0x900fc),	.cfg = 0x7a0}, 
+	{ .reg = DDRPHY_REG(0x900fd),	.cfg = 0x16a}, 
+	{ .reg = DDRPHY_REG(0x900fe),	.cfg = 0x68}, 
+	{ .reg = DDRPHY_REG(0x900ff),	.cfg = 0x790}, 
+	{ .reg = DDRPHY_REG(0x90100),	.cfg = 0x16a}, 
+	{ .reg = DDRPHY_REG(0x90101),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x90102),	.cfg = 0x8b10}, 
+	{ .reg = DDRPHY_REG(0x90103),	.cfg = 0x168}, 
+	{ .reg = DDRPHY_REG(0x90104),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x90105),	.cfg = 0xab10}, 
+	{ .reg = DDRPHY_REG(0x90106),	.cfg = 0x168}, 
+	{ .reg = DDRPHY_REG(0x90107),	.cfg = 0xa}, 
+	{ .reg = DDRPHY_REG(0x90108),	.cfg = 0x408}, 
+	{ .reg = DDRPHY_REG(0x90109),	.cfg = 0x169}, 
+	{ .reg = DDRPHY_REG(0x9010a),	.cfg = 0x58}, 
+	{ .reg = DDRPHY_REG(0x9010b),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x9010c),	.cfg = 0x68}, 
+	{ .reg = DDRPHY_REG(0x9010d),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x9010e),	.cfg = 0x408}, 
+	{ .reg = DDRPHY_REG(0x9010f),	.cfg = 0x169}, 
+	{ .reg = DDRPHY_REG(0x90110),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x90111),	.cfg = 0x8b10}, 
+	{ .reg = DDRPHY_REG(0x90112),	.cfg = 0x168}, 
+	{ .reg = DDRPHY_REG(0x90113),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x90114),	.cfg = 0xab10}, 
+	{ .reg = DDRPHY_REG(0x90115),	.cfg = 0x168}, 
+	{ .reg = DDRPHY_REG(0x90116),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x90117),	.cfg = 0x1d8}, 
+	{ .reg = DDRPHY_REG(0x90118),	.cfg = 0x169}, 
+	{ .reg = DDRPHY_REG(0x90119),	.cfg = 0x80}, 
+	{ .reg = DDRPHY_REG(0x9011a),	.cfg = 0x790}, 
+	{ .reg = DDRPHY_REG(0x9011b),	.cfg = 0x16a}, 
+	{ .reg = DDRPHY_REG(0x9011c),	.cfg = 0x18}, 
+	{ .reg = DDRPHY_REG(0x9011d),	.cfg = 0x7aa}, 
+	{ .reg = DDRPHY_REG(0x9011e),	.cfg = 0x6a}, 
+	{ .reg = DDRPHY_REG(0x9011f),	.cfg = 0xa}, 
+	{ .reg = DDRPHY_REG(0x90120),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x90121),	.cfg = 0x1e9}, 
+	{ .reg = DDRPHY_REG(0x90122),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x90123),	.cfg = 0x8080}, 
+	{ .reg = DDRPHY_REG(0x90124),	.cfg = 0x108}, 
+	{ .reg = DDRPHY_REG(0x90125),	.cfg = 0xf}, 
+	{ .reg = DDRPHY_REG(0x90126),	.cfg = 0x408}, 
+	{ .reg = DDRPHY_REG(0x90127),	.cfg = 0x169}, 
+	{ .reg = DDRPHY_REG(0x90128),	.cfg = 0xc}, 
+	{ .reg = DDRPHY_REG(0x90129),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x9012a),	.cfg = 0x68}, 
+	{ .reg = DDRPHY_REG(0x9012b),	.cfg = 0x9}, 
+	{ .reg = DDRPHY_REG(0x9012c),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x9012d),	.cfg = 0x1a9}, 
+	{ .reg = DDRPHY_REG(0x9012e),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x9012f),	.cfg = 0x408}, 
+	{ .reg = DDRPHY_REG(0x90130),	.cfg = 0x169}, 
+	{ .reg = DDRPHY_REG(0x90131),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x90132),	.cfg = 0x8080}, 
+	{ .reg = DDRPHY_REG(0x90133),	.cfg = 0x108}, 
+	{ .reg = DDRPHY_REG(0x90134),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x90135),	.cfg = 0x7aa}, 
+	{ .reg = DDRPHY_REG(0x90136),	.cfg = 0x6a}, 
+	{ .reg = DDRPHY_REG(0x90137),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x90138),	.cfg = 0x8568}, 
+	{ .reg = DDRPHY_REG(0x90139),	.cfg = 0x108}, 
+	{ .reg = DDRPHY_REG(0x9013a),	.cfg = 0xb7}, 
+	{ .reg = DDRPHY_REG(0x9013b),	.cfg = 0x790}, 
+	{ .reg = DDRPHY_REG(0x9013c),	.cfg = 0x16a}, 
+	{ .reg = DDRPHY_REG(0x9013d),	.cfg = 0x1f}, 
+	{ .reg = DDRPHY_REG(0x9013e),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x9013f),	.cfg = 0x68}, 
+	{ .reg = DDRPHY_REG(0x90140),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x90141),	.cfg = 0x8558}, 
+	{ .reg = DDRPHY_REG(0x90142),	.cfg = 0x168}, 
+	{ .reg = DDRPHY_REG(0x90143),	.cfg = 0xf}, 
+	{ .reg = DDRPHY_REG(0x90144),	.cfg = 0x408}, 
+	{ .reg = DDRPHY_REG(0x90145),	.cfg = 0x169}, 
+	{ .reg = DDRPHY_REG(0x90146),	.cfg = 0xc}, 
+	{ .reg = DDRPHY_REG(0x90147),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x90148),	.cfg = 0x68}, 
+	{ .reg = DDRPHY_REG(0x90149),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x9014a),	.cfg = 0x408}, 
+	{ .reg = DDRPHY_REG(0x9014b),	.cfg = 0x169}, 
+	{ .reg = DDRPHY_REG(0x9014c),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x9014d),	.cfg = 0x8558}, 
+	{ .reg = DDRPHY_REG(0x9014e),	.cfg = 0x168}, 
+	{ .reg = DDRPHY_REG(0x9014f),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x90150),	.cfg = 0x3c8}, 
+	{ .reg = DDRPHY_REG(0x90151),	.cfg = 0x1a9}, 
+	{ .reg = DDRPHY_REG(0x90152),	.cfg = 0x3}, 
+	{ .reg = DDRPHY_REG(0x90153),	.cfg = 0x370}, 
+	{ .reg = DDRPHY_REG(0x90154),	.cfg = 0x129}, 
+	{ .reg = DDRPHY_REG(0x90155),	.cfg = 0x20}, 
+	{ .reg = DDRPHY_REG(0x90156),	.cfg = 0x2aa}, 
+	{ .reg = DDRPHY_REG(0x90157),	.cfg = 0x9}, 
+	{ .reg = DDRPHY_REG(0x90158),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x90159),	.cfg = 0x400}, 
+	{ .reg = DDRPHY_REG(0x9015a),	.cfg = 0x10e}, 
+	{ .reg = DDRPHY_REG(0x9015b),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x9015c),	.cfg = 0xe8}, 
+	{ .reg = DDRPHY_REG(0x9015d),	.cfg = 0x109}, 
+	{ .reg = DDRPHY_REG(0x9015e),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x9015f),	.cfg = 0x8140}, 
+	{ .reg = DDRPHY_REG(0x90160),	.cfg = 0x10c}, 
+	{ .reg = DDRPHY_REG(0x90161),	.cfg = 0x10}, 
+	{ .reg = DDRPHY_REG(0x90162),	.cfg = 0x8138}, 
+	{ .reg = DDRPHY_REG(0x90163),	.cfg = 0x10c}, 
+	{ .reg = DDRPHY_REG(0x90164),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x90165),	.cfg = 0x7c8}, 
+	{ .reg = DDRPHY_REG(0x90166),	.cfg = 0x101}, 
+	{ .reg = DDRPHY_REG(0x90167),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x90168),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x90169),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x9016a),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x9016b),	.cfg = 0x448}, 
+	{ .reg = DDRPHY_REG(0x9016c),	.cfg = 0x109}, 
+	{ .reg = DDRPHY_REG(0x9016d),	.cfg = 0xf}, 
+	{ .reg = DDRPHY_REG(0x9016e),	.cfg = 0x7c0}, 
+	{ .reg = DDRPHY_REG(0x9016f),	.cfg = 0x109}, 
+	{ .reg = DDRPHY_REG(0x90170),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x90171),	.cfg = 0xe8}, 
+	{ .reg = DDRPHY_REG(0x90172),	.cfg = 0x109}, 
+	{ .reg = DDRPHY_REG(0x90173),	.cfg = 0x47}, 
+	{ .reg = DDRPHY_REG(0x90174),	.cfg = 0x630}, 
+	{ .reg = DDRPHY_REG(0x90175),	.cfg = 0x109}, 
+	{ .reg = DDRPHY_REG(0x90176),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x90177),	.cfg = 0x618}, 
+	{ .reg = DDRPHY_REG(0x90178),	.cfg = 0x109}, 
+	{ .reg = DDRPHY_REG(0x90179),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x9017a),	.cfg = 0xe0}, 
+	{ .reg = DDRPHY_REG(0x9017b),	.cfg = 0x109}, 
+	{ .reg = DDRPHY_REG(0x9017c),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x9017d),	.cfg = 0x7c8}, 
+	{ .reg = DDRPHY_REG(0x9017e),	.cfg = 0x109}, 
+	{ .reg = DDRPHY_REG(0x9017f),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x90180),	.cfg = 0x8140}, 
+	{ .reg = DDRPHY_REG(0x90181),	.cfg = 0x10c}, 
+	{ .reg = DDRPHY_REG(0x90182),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x90183),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x90184),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x90185),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x90186),	.cfg = 0x4}, 
+	{ .reg = DDRPHY_REG(0x90187),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x90188),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x90189),	.cfg = 0x7c8}, 
+	{ .reg = DDRPHY_REG(0x9018a),	.cfg = 0x101}, 
+	{ .reg = DDRPHY_REG(0x90006),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x90007),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x90008),	.cfg = 0x8}, 
+	{ .reg = DDRPHY_REG(0x90009),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x9000a),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x9000b),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0xd00e7),	.cfg = 0x400}, 
+	{ .reg = DDRPHY_REG(0x90017),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x9001f),	.cfg = 0x2a}, 
+	{ .reg = DDRPHY_REG(0x90026),	.cfg = 0x6a}, 
+	{ .reg = DDRPHY_REG(0x400d0),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x400d1),	.cfg = 0x101}, 
+	{ .reg = DDRPHY_REG(0x400d2),	.cfg = 0x105}, 
+	{ .reg = DDRPHY_REG(0x400d3),	.cfg = 0x107}, 
+	{ .reg = DDRPHY_REG(0x400d4),	.cfg = 0x10f}, 
+	{ .reg = DDRPHY_REG(0x400d5),	.cfg = 0x202}, 
+	{ .reg = DDRPHY_REG(0x400d6),	.cfg = 0x20a}, 
+	{ .reg = DDRPHY_REG(0x400d7),	.cfg = 0x20b}, 
+	{ .reg = DDRPHY_REG(0x2003a),	.cfg = 0x2}, 
+	{ .reg = DDRPHY_REG(0x2000b),	.cfg = 0x5d}, 
+	{ .reg = DDRPHY_REG(0x2000c),	.cfg = 0xbb}, 
+	{ .reg = DDRPHY_REG(0x2000d),	.cfg = 0x753}, 
+	{ .reg = DDRPHY_REG(0x2000e),	.cfg = 0x2c}, 
+	{ .reg = DDRPHY_REG(0x9000c),	.cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x9000d),	.cfg = 0x173}, 
+	{ .reg = DDRPHY_REG(0x9000e),	.cfg = 0x60}, 
+	{ .reg = DDRPHY_REG(0x9000f),	.cfg = 0x6110}, 
+	{ .reg = DDRPHY_REG(0x90010),	.cfg = 0x2152}, 
+	{ .reg = DDRPHY_REG(0x90011),	.cfg = 0xdfbd}, 
+	{ .reg = DDRPHY_REG(0x90012),	.cfg = 0x60}, 
+	{ .reg = DDRPHY_REG(0x90013),	.cfg = 0x6152}, 
+	{ .reg = DDRPHY_REG(0x20010),	.cfg = 0x5a}, 
+	{ .reg = DDRPHY_REG(0x20011),	.cfg = 0x3}, 
+	{ .reg = DDRPHY_REG(0x40080),	.cfg = 0xe0}, 
+	{ .reg = DDRPHY_REG(0x40081),	.cfg = 0x12}, 
+	{ .reg = DDRPHY_REG(0x40082),	.cfg = 0xe0}, 
+	{ .reg = DDRPHY_REG(0x40083),	.cfg = 0x12}, 
+	{ .reg = DDRPHY_REG(0x40084),	.cfg = 0xe0}, 
+	{ .reg = DDRPHY_REG(0x40085),	.cfg = 0x12}, 
+	{ .reg = DDRPHY_REG(0x400fd),	.cfg = 0xf}, 
+	{ .reg = DDRPHY_REG(0x10011),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x10012),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x10013),	.cfg = 0x180}, 
+	{ .reg = DDRPHY_REG(0x10018),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x10002),	.cfg = 0x6209}, 
+	{ .reg = DDRPHY_REG(0x100b2),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x101b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x102b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x103b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x104b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x105b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x106b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x107b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x108b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x11011),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x11012),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x11013),	.cfg = 0x180}, 
+	{ .reg = DDRPHY_REG(0x11018),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x11002),	.cfg = 0x6209}, 
+	{ .reg = DDRPHY_REG(0x110b2),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x111b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x112b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x113b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x114b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x115b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x116b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x117b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x118b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x12011),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x12012),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x12013),	.cfg = 0x180}, 
+	{ .reg = DDRPHY_REG(0x12018),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x12002),	.cfg = 0x6209}, 
+	{ .reg = DDRPHY_REG(0x120b2),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x121b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x122b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x123b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x124b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x125b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x126b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x127b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x128b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x13011),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x13012),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x13013),	.cfg = 0x180}, 
+	{ .reg = DDRPHY_REG(0x13018),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x13002),	.cfg = 0x6209}, 
+	{ .reg = DDRPHY_REG(0x130b2),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x131b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x132b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x133b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x134b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x135b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x136b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x137b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x138b4),	.cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x2003a),	.cfg = 0x2}, 
+	{ .reg = DDRPHY_REG(0xc0080),	.cfg = 0x2}, 
+
+	{ .reg = DDRPHY_REG(0xd0000),	.cfg = 0x1}, 
+};
+
+void ddrphy_load_pie_image(void)
+{
+	unsigned int reg, cfg;
+	int num = ARRAY_SIZE(lpddr4_phy_pie);
+
+	for (int i = 0; i < num; i ++) {
+		reg = lpddr4_phy_pie[i].reg;
+		cfg = lpddr4_phy_pie[i].cfg;
+		mmio_write_32(reg, cfg);
+	}
+}
diff --git a/plat/imx/common/imx8m/lpddr4_retention.c b/plat/imx/common/imx8m/lpddr4_retention.c
new file mode 100644
index 0000000..55ea34f
--- /dev/null
+++ b/plat/imx/common/imx8m/lpddr4_retention.c
@@ -0,0 +1,1151 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <debug.h>
+#include <stdbool.h>
+#include <ddrc.h>
+#include <dram.h>
+#include <mmio.h>
+#include <platform_def.h>
+#include <soc.h>
+
+#define SRC_IPS_BASE_ADDR       IMX_SRC_BASE
+#define SRC_DDRC_RCR_ADDR	(SRC_IPS_BASE_ADDR + 0x1000)
+
+#define GPC_PU_PWRHSK		(IMX_GPC_BASE + 0x01FC)
+#define CCM_SRC_CTRL_OFFSET     (IMX_CCM_BASE + 0x800)
+#define CCM_CCGR_OFFSET         (IMX_CCM_BASE + 0x4000)
+#define CCM_SRC_CTRL(n)		(CCM_SRC_CTRL_OFFSET + 0x10 * n)
+#define CCM_CCGR(n)		(CCM_CCGR_OFFSET + 0x10 * n)
+
+struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	{ .reg =DDRC_DBG1(0),	 .cfg = 0x00000001},
+	{ .reg =DDRC_PWRCTL(0),  .cfg = 0x00000001},
+	{ .reg =DDRC_MSTR(0),	 .cfg = 0xa1080020},
+	{ .reg =DDRC_RFSHTMG(0), .cfg = 0x005b00d2},
+	{ .reg =DDRC_INIT0(0),   .cfg = 0xC003061B},
+	{ .reg =DDRC_INIT1(0),   .cfg = 0x009D0000},
+	{ .reg =DDRC_INIT3(0),   .cfg = 0x00D4002D},
+	{ .reg =DDRC_INIT4(0),   .cfg = 0x00330008},
+	{ .reg =DDRC_INIT6(0),   .cfg = 0x0066004a},
+	{ .reg =DDRC_INIT7(0),   .cfg = 0x0006004a},
+
+	{ .reg =DDRC_DRAMTMG0(0),  .cfg = 0x1A201B22},
+	{ .reg =DDRC_DRAMTMG1(0),  .cfg = 0x00060633},
+	{ .reg =DDRC_DRAMTMG3(0),  .cfg = 0x00C0C000},
+	{ .reg =DDRC_DRAMTMG4(0),  .cfg = 0x0F04080F},
+	{ .reg =DDRC_DRAMTMG5(0),  .cfg = 0x02040C0C},
+	{ .reg =DDRC_DRAMTMG6(0),  .cfg = 0x01010007},
+	{ .reg =DDRC_DRAMTMG7(0),  .cfg = 0x00000401},
+	{ .reg =DDRC_DRAMTMG12(0), .cfg = 0x00020600},
+	{ .reg =DDRC_DRAMTMG13(0), .cfg = 0x0C100002},
+	{ .reg =DDRC_DRAMTMG14(0), .cfg = 0x000000E6},
+	{ .reg =DDRC_DRAMTMG17(0), .cfg = 0x00A00050},
+
+	{ .reg =DDRC_ZQCTL0(0), .cfg = 0x03200018},
+	{ .reg =DDRC_ZQCTL1(0), .cfg = 0x028061A8},
+	{ .reg =DDRC_ZQCTL2(0), .cfg = 0x00000000},
+
+	{ .reg =DDRC_DFITMG0(0), .cfg = 0x0497820A},
+	{ .reg =DDRC_DFITMG1(0), .cfg = 0x00080303},
+	{ .reg =DDRC_DFIUPD0(0), .cfg = 0xE0400018},
+
+	{ .reg =DDRC_DFIUPD1(0), .cfg = 0x00DF00E4},
+	{ .reg =DDRC_DFIUPD2(0), .cfg = 0x80000000},
+	{ .reg =DDRC_DFIMISC(0), .cfg = 0x00000011},
+	{ .reg =DDRC_DFITMG2(0), .cfg = 0x0000170A},
+
+	{ .reg =DDRC_DBICTL(0),     .cfg = 0x00000001},
+	{ .reg =DDRC_DFIPHYMSTR(0), .cfg = 0x00000000},
+	{ .reg =DDRC_RANKCTL(0),    .cfg = 0x00000c99},
+	{ .reg =DDRC_DRAMTMG2(0),   .cfg = 0x070E171a},
+
+	/* ADDRMAP */
+	{ .reg =DDRC_ADDRMAP0(0), .cfg = 0x0000001f},
+	{ .reg =DDRC_ADDRMAP1(0), .cfg = 0x00080808},
+	{ .reg =DDRC_ADDRMAP2(0), .cfg = 0x00000000},
+	{ .reg =DDRC_ADDRMAP3(0), .cfg = 0x00000000},
+	{ .reg =DDRC_ADDRMAP4(0), .cfg = 0x00001f1f},
+	{ .reg =DDRC_ADDRMAP5(0), .cfg = 0x07070707},
+	{ .reg =DDRC_ADDRMAP6(0), .cfg = 0x07070707},
+	{ .reg =DDRC_ADDRMAP7(0), .cfg = 0x00000f0f},
+
+	/* perf */
+	{ .reg =DDRC_SCHED(0),    .cfg = 0x29001701},
+	{ .reg =DDRC_SCHED1(0),   .cfg = 0x0000002c},
+	{ .reg =DDRC_PERFHPR1(0), .cfg = 0x04000030},
+	{ .reg =DDRC_PERFLPR1(0), .cfg = 0x900093e7},
+	{ .reg =DDRC_PCCFG(0),    .cfg = 0x00000111},
+	{ .reg =DDRC_PCFGW_0(0),  .cfg = 0x000072ff},
+	{ .reg =DDRC_PCFGQOS0_0(0), .cfg = 0x02100e07},
+	{ .reg =DDRC_PCFGQOS1_0(0), .cfg = 0x00620096},
+	{ .reg =DDRC_PCFGWQOS0_0(0), .cfg = 0x01100e07},
+	{ .reg =DDRC_PCFGWQOS1_0(0), .cfg = 0x0000012c},
+
+	/* shadow registers for P1 & P2 */
+
+	/* init fsp */
+	{ .reg =DDRC_MSTR2(0), .cfg = 0x0},
+};
+
+struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+
+	/* phy init config */
+	{ .reg = DDRPHY_REG(0x1005f), .cfg = 0x15f}, 
+	{ .reg = DDRPHY_REG(0x1015f), .cfg = 0x15f}, 
+	{ .reg = DDRPHY_REG(0x1105f), .cfg = 0x15f}, 
+	{ .reg = DDRPHY_REG(0x1115f), .cfg = 0x15f}, 
+	{ .reg = DDRPHY_REG(0x1205f), .cfg = 0x15f}, 
+	{ .reg = DDRPHY_REG(0x1215f), .cfg = 0x15f}, 
+	{ .reg = DDRPHY_REG(0x1305f), .cfg = 0x15f}, 
+	{ .reg = DDRPHY_REG(0x1315f), .cfg = 0x15f}, 
+	{ .reg = DDRPHY_REG(0x55),    .cfg = 0x16f}, 
+	{ .reg = DDRPHY_REG(0x1055),  .cfg = 0x16f}, 
+	{ .reg = DDRPHY_REG(0x2055),  .cfg = 0x16f}, 
+	{ .reg = DDRPHY_REG(0x3055),  .cfg = 0x16f}, 
+	{ .reg = DDRPHY_REG(0x4055),  .cfg = 0x16f}, 
+	{ .reg = DDRPHY_REG(0x5055),  .cfg = 0x16f}, 
+	{ .reg = DDRPHY_REG(0x6055),  .cfg = 0x16f}, 
+	{ .reg = DDRPHY_REG(0x7055),  .cfg = 0x16f}, 
+	{ .reg = DDRPHY_REG(0x8055),  .cfg = 0x16f}, 
+	{ .reg = DDRPHY_REG(0x9055),  .cfg = 0x16f}, 
+	{ .reg = DDRPHY_REG(0x200c5), .cfg = 0x19}, 
+	{ .reg = DDRPHY_REG(0x2002e), .cfg = 0x2}, 
+	{ .reg = DDRPHY_REG(0x90204), .cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x20024), .cfg = 0xab}, 
+	{ .reg = DDRPHY_REG(0x2003a), .cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x20056), .cfg = 0x3}, 
+	{ .reg = DDRPHY_REG(0x1004d), .cfg = 0xe00}, 
+	{ .reg = DDRPHY_REG(0x1014d), .cfg = 0xe00}, 
+	{ .reg = DDRPHY_REG(0x1104d), .cfg = 0xe00}, 
+	{ .reg = DDRPHY_REG(0x1114d), .cfg = 0xe00}, 
+	{ .reg = DDRPHY_REG(0x1204d), .cfg = 0xe00}, 
+	{ .reg = DDRPHY_REG(0x1214d), .cfg = 0xe00}, 
+	{ .reg = DDRPHY_REG(0x1304d), .cfg = 0xe00}, 
+	{ .reg = DDRPHY_REG(0x1314d), .cfg = 0xe00}, 
+	{ .reg = DDRPHY_REG(0x10049), .cfg = 0xfbe}, 
+	{ .reg = DDRPHY_REG(0x10149), .cfg = 0xfbe}, 
+	{ .reg = DDRPHY_REG(0x11049), .cfg = 0xfbe}, 
+	{ .reg = DDRPHY_REG(0x11149), .cfg = 0xfbe}, 
+	{ .reg = DDRPHY_REG(0x12049), .cfg = 0xfbe}, 
+	{ .reg = DDRPHY_REG(0x12149), .cfg = 0xfbe}, 
+	{ .reg = DDRPHY_REG(0x13049), .cfg = 0xfbe}, 
+	{ .reg = DDRPHY_REG(0x13149), .cfg = 0xfbe}, 
+	{ .reg = DDRPHY_REG(0x43),    .cfg = 0x63}, 
+	{ .reg = DDRPHY_REG(0x1043),  .cfg = 0x63}, 
+	{ .reg = DDRPHY_REG(0x2043),  .cfg = 0x63}, 
+	{ .reg = DDRPHY_REG(0x3043),  .cfg = 0x63}, 
+	{ .reg = DDRPHY_REG(0x4043),  .cfg = 0x63}, 
+	{ .reg = DDRPHY_REG(0x5043),  .cfg = 0x63}, 
+	{ .reg = DDRPHY_REG(0x6043),  .cfg = 0x63}, 
+	{ .reg = DDRPHY_REG(0x7043),  .cfg = 0x63}, 
+	{ .reg = DDRPHY_REG(0x8043),  .cfg = 0x63}, 
+	{ .reg = DDRPHY_REG(0x9043),  .cfg = 0x63}, 
+	{ .reg = DDRPHY_REG(0x20018), .cfg = 0x3}, 
+	{ .reg = DDRPHY_REG(0x20075), .cfg = 0x4}, 
+	{ .reg = DDRPHY_REG(0x20050), .cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x20008), .cfg = 0x2ee}, 
+	{ .reg = DDRPHY_REG(0x20088), .cfg = 0x9}, 
+	{ .reg = DDRPHY_REG(0x200b2), .cfg = 0x1d4}, 
+	{ .reg = DDRPHY_REG(0x10043), .cfg = 0x5a1}, 
+	{ .reg = DDRPHY_REG(0x10143), .cfg = 0x5a1}, 
+	{ .reg = DDRPHY_REG(0x11043), .cfg = 0x5a1}, 
+	{ .reg = DDRPHY_REG(0x11143), .cfg = 0x5a1}, 
+	{ .reg = DDRPHY_REG(0x12043), .cfg = 0x5a1}, 
+	{ .reg = DDRPHY_REG(0x12143), .cfg = 0x5a1}, 
+	{ .reg = DDRPHY_REG(0x13043), .cfg = 0x5a1}, 
+	{ .reg = DDRPHY_REG(0x13143), .cfg = 0x5a1}, 
+	{ .reg = DDRPHY_REG(0x200fa), .cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x20019), .cfg = 0x1}, 
+	{ .reg = DDRPHY_REG(0x200f0), .cfg = 0x600}, 
+	{ .reg = DDRPHY_REG(0x200f1), .cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x200f2), .cfg = 0x4444}, 
+	{ .reg = DDRPHY_REG(0x200f3), .cfg = 0x8888}, 
+	{ .reg = DDRPHY_REG(0x200f4), .cfg = 0x5655}, 
+	{ .reg = DDRPHY_REG(0x200f5), .cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x200f6), .cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x200f7), .cfg = 0xf000}, 
+	{ .reg = DDRPHY_REG(0x20025), .cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x2002d), .cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0x200c7), .cfg = 0x21}, 
+	{ .reg = DDRPHY_REG(0x200ca), .cfg = 0x24}, 
+	{ .reg = DDRPHY_REG(0x20060), .cfg = 0x2}, 
+	{ .reg = DDRPHY_REG(0xd0000), .cfg = 0x0}, 
+	{ .reg = DDRPHY_REG(0xd0000), .cfg = 0x1}, 
+
+	/* trained CSR */
+	{ .reg = DDRPHY_REG(0x200b2),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1200b2), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2200b2), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x200cb),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10043),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110043), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x210043), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10143),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110143), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x210143), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11043),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x111043), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x211043), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11143),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x111143), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x211143), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12043),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x112043), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x212043), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12143),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x112143), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x212143), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13043),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x113043), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x213043), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13143),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x113143), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x213143), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x80),     .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x200080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1080),   .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x101080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x201080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2080),   .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x102080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x202080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x3080),   .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x103080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x203080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x4080),   .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x104080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x204080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x5080),   .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x105080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x205080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x6080),   .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x106080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x206080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x7080),   .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x107080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x207080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x8080),   .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x108080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x208080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x9080),   .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x109080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x209080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10080),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x210080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10180),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110180), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x210180), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11080),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x111080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x211080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11180),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x111180), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x211180), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12080),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x112080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x212080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12180),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x112180), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x212180), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13080),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x113080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x213080), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13180),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x113180), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x213180), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10081),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110081), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x210081), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10181),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110181), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x210181), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11081),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x111081), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x211081), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11181),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x111181), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x211181), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12081),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x112081), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x212081), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12181),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x112181), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x212181), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13081),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x113081), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x213081), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13181),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x113181), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x213181), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100d0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1100d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2100d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x101d0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1101d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2101d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110d0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1110d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2110d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x111d0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1111d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2111d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120d0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1120d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2120d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x121d0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1121d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2121d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x130d0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1130d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2130d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x131d0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1131d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2131d0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100d1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1100d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2100d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x101d1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1101d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2101d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110d1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1110d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2110d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x111d1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1111d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2111d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120d1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1120d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2120d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x121d1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1121d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2121d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x130d1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1130d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2130d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x131d1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1131d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2131d1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10068),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10168),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10268),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10368),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10468),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10568),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10668),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10768),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10868),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11068),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11168),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11268),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11368),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11468),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11568),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11668),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11768),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11868),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12068),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12168),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12268),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12368),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12468),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12568),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12668),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12768),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12868),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13068),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13168),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13268),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13368),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13468),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13568),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13668),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13768),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13868),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10069),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10169),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10269),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10369),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10469),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10569),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10669),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10769),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10869),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11069),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11169),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11269),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11369),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11469),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11569),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11669),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11769),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11869),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12069),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12169),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12269),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12369),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12469),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12569),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12669),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12769),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12869),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13069),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13169),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13269),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13369),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13469),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13569),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13669),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13769),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13869),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1008c),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11008c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21008c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1018c),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11018c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21018c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1108c),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11108c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21108c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1118c),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11118c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21118c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1208c),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11208c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21208c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1218c),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11218c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21218c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1308c),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11308c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21308c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1318c),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11318c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21318c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1008d),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11008d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21008d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1018d),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11018d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21018d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1108d),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11108d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21108d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1118d),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11118d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21118d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1208d),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11208d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21208d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1218d),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11218d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21218d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1308d),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11308d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21308d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1318d),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11318d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x21318d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1100c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2100c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x101c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1101c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2101c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x102c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1102c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2102c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x103c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1103c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2103c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x104c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1104c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2104c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x105c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1105c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2105c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x106c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1106c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2106c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x107c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1107c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2107c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x108c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1108c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2108c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1110c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2110c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x111c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1111c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2111c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x112c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1112c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2112c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x113c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1113c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2113c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x114c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1114c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2114c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x115c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1115c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2115c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x116c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1116c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2116c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x117c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1117c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2117c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x118c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1118c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2118c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1120c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2120c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x121c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1121c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2121c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x122c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1122c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2122c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x123c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1123c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2123c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x124c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1124c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2124c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x125c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1125c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2125c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x126c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1126c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2126c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x127c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1127c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2127c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x128c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1128c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2128c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x130c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1130c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2130c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x131c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1131c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2131c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x132c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1132c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2132c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x133c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1133c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2133c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x134c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1134c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2134c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x135c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1135c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2135c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x136c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1136c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2136c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x137c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1137c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2137c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x138c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1138c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2138c0), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1100c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2100c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x101c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1101c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2101c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x102c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1102c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2102c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x103c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1103c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2103c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x104c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1104c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2104c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x105c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1105c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2105c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x106c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1106c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2106c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x107c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1107c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2107c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x108c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1108c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2108c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1110c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2110c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x111c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1111c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2111c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x112c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1112c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2112c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x113c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1113c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2113c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x114c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1114c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2114c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x115c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1115c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2115c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x116c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1116c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2116c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x117c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1117c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2117c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x118c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1118c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2118c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1120c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2120c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x121c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1121c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2121c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x122c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1122c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2122c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x123c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1123c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2123c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x124c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1124c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2124c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x125c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1125c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2125c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x126c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1126c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2126c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x127c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1127c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2127c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x128c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1128c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2128c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x130c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1130c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2130c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x131c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1131c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2131c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x132c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1132c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2132c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x133c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1133c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2133c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x134c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1134c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2134c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x135c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1135c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2135c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x136c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1136c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2136c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x137c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1137c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2137c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x138c1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1138c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2138c1), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10020),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110020), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x210020), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11020),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x111020), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x211020), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12020),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x112020), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x212020), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13020),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x113020), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x213020), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x20072),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x20073),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x20074),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100aa),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110aa),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120aa),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x130aa),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x20010),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120010), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x220010), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x20011),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120011), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x220011), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100ae),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1100ae), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2100ae), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100af),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1100af), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2100af), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110ae),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1110ae), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2110ae), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110af),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1110af), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2110af), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120ae),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1120ae), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2120ae), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120af),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1120af), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2120af), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x130ae),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1130ae), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2130ae), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x130af),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x1130af), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2130af), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x20020),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120020), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x220020), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100a0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100a1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100a2),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100a3),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100a4),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100a5),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100a6),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x100a7),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110a0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110a1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110a2),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110a3),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110a4),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110a5),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110a6),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x110a7),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120a0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120a1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120a2),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120a3),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120a4),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120a5),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120a6),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x120a7),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x130a0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x130a1),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x130a2),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x130a3),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x130a4),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x130a5),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x130a6),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x130a7),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2007c),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12007c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x22007c), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x2007d),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12007d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x22007d), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x400fd),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x400c0),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x90201),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x190201), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x290201), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x90202),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x190202), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x290202), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x90203),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x190203), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x290203), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x90204),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x190204), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x290204), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x90205),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x190205), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x290205), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x90206),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x190206), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x290206), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x90207),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x190207), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x290207), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x90208),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x190208), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x290208), .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10062),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10162),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10262),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10362),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10462),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10562),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10662),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10762),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10862),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11062),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11162),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11262),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11362),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11462),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11562),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11662),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11762),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11862),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12062),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12162),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12262),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12362),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12462),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12562),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12662),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12762),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12862),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13062),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13162),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13262),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13362),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13462),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13562),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13662),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13762),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13862),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x20077),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10001),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11001),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12001),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13001),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10040),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10140),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10240),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10340),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10440),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10540),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10640),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10740),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10840),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10030),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10130),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10230),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10330),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10430),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10530),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10630),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10730),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x10830),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11040),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11140),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11240),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11340),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11440),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11540),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11640),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11740),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11840),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11030),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11130),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11230),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11330),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11430),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11530),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11630),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11730),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x11830),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12040),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12140),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12240),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12340),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12440),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12540),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12640),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12740),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12840),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12030),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12130),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12230),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12330),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12430),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12530),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12630),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12730),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x12830),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13040),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13140),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13240),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13340),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13440),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13540),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13640),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13740),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13840),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13030),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13130),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13230),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13330),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13430),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13530),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13630),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13730),  .cfg = 0 },
+	{ .reg = DDRPHY_REG(0x13830),  .cfg = 0 },
+};
+
+struct dram_info imx8m_lpddr4_dram_info = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+};
+
+
+
+void lpddr4_enter_retention(void)
+{
+	unsigned int tmp, tmp_t, i;
+	INFO("enter lpddr4 retention\n");
+
+	/* wait DBGCAM to be empty */
+	do {
+		tmp = mmio_read_32(DDRC_DBGCAM(0));
+	} while(tmp != 0x36000000);
+
+	/* Blocks AXI ports from taking anymore transactions */
+	mmio_write_32(DDRC_PCTRL_0(0), 0x00000000);
+
+	/* Waits unit all AXI ports are idle */
+	do {
+		tmp = mmio_read_32(DDRC_PSTAT(0));
+	} while(tmp & 0x10001);
+
+	/* enters self refresh */
+	//reg32setbit(DDRC_PWRCTL(0), 5);
+	mmio_write_32(DDRC_PWRCTL(0), 0x000000aa);
+
+	tmp=0;
+	/* self-refresh state */
+	while (tmp!=0x223) {
+		tmp  = 0x33f & (mmio_read_32((DDRC_STAT(0))));
+		INFO("C: waiting for STAT selfref_type= Self Refresh\n");
+	} 
+
+	mmio_write_32(DDRC_DFIMISC(0), 0x00000000);
+
+	/* set SWCTL.sw_done to disable quasi-dynamic register programming outside reset. */
+	mmio_write_32(DDRC_SWCTL(0), 0x00000000);
+
+	mmio_write_32(DDRC_DFIMISC(0), 0x00001f00);
+	mmio_write_32(DDRC_DFIMISC(0), 0x00001f20);
+
+	/* wait DFISTAT.dfi_init_complete to 0 */
+	tmp_t = 0;
+	while (tmp_t==1) {
+		tmp  = mmio_read_32(DDRC_DFISTAT(0));
+		tmp_t = tmp & 0x01;
+	}
+
+	mmio_write_32(DDRC_DFIMISC(0), 0x00001f00);
+
+	/* wait DFISTAT.dfi_init_complete to 1 */
+	tmp_t = 0;
+	while (tmp_t==0) {
+		tmp  = mmio_read_32(DDRC_DFISTAT(0));
+		tmp_t = tmp & 0x01;
+	}
+
+	/* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */
+	mmio_write_32(DDRC_SWCTL(0), 0x00000001);
+
+	/* should check PhyInLP3 pub reg */
+	dwc_ddrphy_apb_wr(0xd0000,0x0);
+	tmp = mmio_read_32(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*0x00090028);
+	tmp = tmp & 0x1;
+	if (tmp)
+		INFO("C: PhyInLP3 = 1\n");
+	else
+		INFO("vt_fail5\n");
+	dwc_ddrphy_apb_wr(0xd0000,0x1);
+
+	for (i=0; i<20; i++){
+ 	}
+
+#ifdef M850D
+	/* pwrdnreqn_async adbm/adbs of ddr */
+	mmio_clrbits_32(GPC_PU_PWRHSK, (1 << 1));
+	do {
+		tmp = mmio_read_32(GPC_PU_PWRHSK);
+	//        printf("C: wait pwrdnackn_async clr\n");
+	} while(tmp&(0x1<<18));//wait untill pwrdnackn_async=0
+	mmio_setbits_32(GPC_PU_PWRHSK, (1 << 1));
+#else
+	/* pwrdnreqn_async adbm/adbs of ddr */
+	mmio_clrbits_32(GPC_PU_PWRHSK, (1 << 2));
+	do {
+		tmp = mmio_read_32(GPC_PU_PWRHSK);
+		INFO("C: wait pwrdnackn_async clr\n");
+	} while(tmp&(0x1<<20));//wait untill pwrdnackn_async=0
+	mmio_setbits_32(GPC_PU_PWRHSK, (1 << 2));
+#endif
+	/* remove PowerOk */
+	mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F000008); 
+	INFO("vt_event1\n");
+
+	for (i=0; i<20; i++) {
+	}
+
+	mmio_write_32(CCM_CCGR(5),0);
+	mmio_write_32(CCM_SRC_CTRL(15),2);// when test on chip, this should be 0x2
+	INFO("C: gated all DRAM clocks \n");
+
+	for (i=0; i<20; i++) {
+	}
+	/* enable the phy iso */
+	mmio_setbits_32(0x303a0d40, 1);
+	mmio_setbits_32(0x303a0104, (1 << 5));
+}
+
+void lpddr4_exit_retention(void)
+{
+	unsigned int tmp, tmp_t, i;
+
+	INFO("exit lpddr4 retention\n");
+
+	for (i=0; i<50; i++) {
+	}
+
+	for (i=0; i<50; i++) {
+	}
+
+	/*assert all reset */
+#ifdef M850D
+	mmio_write_32(SRC_DDRC_RCR_ADDR+0x4, 0x8F000003); // assert [0]src_system_rst_b!
+	mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F00000F); // assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n,
+	mmio_write_32(SRC_DDRC_RCR_ADDR+0x4, 0x8F000000); // deassert  [4]src_system_rst_b!
+#else
+	mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F00001F); // assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n
+	mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F00000F); // assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n
+#endif
+
+	mmio_write_32(CCM_CCGR(5),2);
+	mmio_write_32(CCM_SRC_CTRL(15),2);
+	INFO("C: enable all DRAM clocks \n");
+
+	/* change the clock source of dram_apb_clk_root */
+	mmio_write_32(0x3038a088, (0x7<<24)|(0x7<<16));
+	mmio_write_32(0x3038a084, (0x4<<24)|(0x3<<16));
+
+	/* disable iso */
+	mmio_write_32(0x303A00EC,0x0000ffff); //PGC_CPU_MAPPING
+	mmio_setbits_32(0x303a00f8, (1 << 5));
+
+	mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F000006); // release [0]ddr1_preset_n,  [3]ddr1_phy_pwrokin_n
+
+	/* ddrc re-init */
+	dram_umctl2_init();
+
+	/*
+	 * Skips the DRAM init routine and starts up in selfrefresh mode
+	 * Program INIT0.skip_dram_init = 2'b11
+	 */
+	mmio_write_32(DDRC_INIT0(0), 0xc0000000 | (mmio_read_32(DDRC_INIT0(0))));
+	mmio_write_32(DDRC_MSTR2(0), 0x0);
+	/* Keeps the controller in self-refresh mode */
+	mmio_write_32(DDRC_PWRCTL(0), 0x000000aa);
+	mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F000004); /* release all reset */
+	mmio_write_32(SRC_DDRC_RCR_ADDR, 0x8F000000); /* release all reset */
+	mmio_write_32(DDRC_DBG1(0), 0x00000000);
+
+	/* before write Dynamic reg, sw_done should be 0 */
+	mmio_write_32(DDRC_SWCTL(0), 0x00000000);
+	mmio_write_32(DDRC_DDR_SS_GPR0, 0x01); /*LPDDR4 mode */
+	mmio_write_32(DDRC_DFIMISC(0), 0x00000000);
+
+	/* dram phy re-init */
+	dram_phy_init();
+
+	INFO("ddrphy config to 3000mts\n");
+
+	/* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x0); 
+	do {
+		tmp_t = mmio_read_32(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0x00020097); 
+		INFO("C: Waiting for CalBusy = 0x%x\n",tmp_t);
+	} while (tmp_t != 0);
+	dwc_ddrphy_apb_wr(0xd0000,0x1);
+
+	/* before write Dynamic reg, sw_done should be 0 */
+	mmio_write_32(DDRC_SWCTL(0), 0x00000000);
+	mmio_write_32(DDRC_DFIMISC(0), 0x00000020); 
+
+	/* wait DFISTAT.dfi_init_complete to 1 */
+	tmp_t = 0;
+	while (tmp_t==0) {
+		tmp  = mmio_read_32(DDRC_DFISTAT(0));
+		tmp_t = tmp & 0x01;
+		INFO("wait DFISTAT.dfi_init_complete to 1\n");
+	}
+
+	/* clear DFIMISC.dfi_init_start */
+	mmio_write_32(DDRC_DFIMISC(0), 0x00000000);
+	/* set DFIMISC.dfi_init_complete_en */
+	mmio_write_32(DDRC_DFIMISC(0), 0x00000001);
+	/* set SWCTL.sw_done to enable quasi-dynamic register programming outside reset. */
+	mmio_write_32(DDRC_SWCTL(0), 0x00000001);
+
+	/* wait SWSTAT.sw_done_ack to 1 */
+	tmp_t = 0;
+	while(tmp_t!=0x1){
+		tmp  = mmio_read_32(DDRC_SWSTAT(0));
+		tmp_t = tmp & 0x1;
+		INFO("1wait SWSTAT.sw_done_ack to 1\n");
+	}
+
+	mmio_write_32(DDRC_PWRCTL(0), 0x000000aa); 
+	mmio_write_32(DDRC_SWCTL(0), 0x00000000); 
+	mmio_write_32(DDRC_DFIMISC(0), 0x00000001); 
+	mmio_write_32(DDRC_SWCTL(0), 0x00000001); 
+
+	/* wait SWSTAT.sw_done_ack to 1 */
+	tmp_t = 0;
+	while(tmp_t!=0x1){
+		tmp  = mmio_read_32(DDRC_SWSTAT(0));
+		tmp_t = tmp & 0x1;
+		INFO("2wait SWSTAT.sw_done_ack to 1\n");
+	}
+
+	mmio_write_32(DDRC_PWRCTL(0), 0x00000088); 
+
+	/* wait STAT to normal state */
+	tmp_t = 0;
+	while(tmp_t!=0x1) {
+		tmp  = mmio_read_32(DDRC_STAT(0));
+		tmp_t = tmp & 0x7;
+		INFO("wait STAT to normal state\n");
+	}
+ 
+	mmio_write_32(DDRC_DERATEEN(0), 0x00000302);
+
+	mmio_write_32(DDRC_PCTRL_0(0), 0x00000001); 
+	 /* dis_auto-refresh is set to 0 */
+	mmio_write_32(DDRC_RFSHCTL3(0), 0x00000000);
+
+	/* should check PhyInLP3 pub reg */
+	mmio_write_32(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0000,0x0);
+	tmp = mmio_read_32(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0x00090028);
+	tmp = tmp & 0x1;
+	if(!tmp)
+		INFO("C: PhyInLP3 = 0\n");
+	else
+		INFO("vt_fail6\n");
+	mmio_write_32(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0000,0x1);
+
+}
diff --git a/plat/imx/common/include/dram.h b/plat/imx/common/include/dram.h
new file mode 100644
index 0000000..5545fad
--- /dev/null
+++ b/plat/imx/common/include/dram.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __DRAM_H__
+#define __DRAM_H__
+
+#include <utils_def.h>
+
+#define DDRC_LPDDR4	BIT(5)
+#define DDR_TYPE_MASK	0x3f
+
+#define DDRPHY_REG(x)	(0x3c000000 + 4*x)
+
+/* reg & config param */
+struct dram_cfg_param {
+	unsigned int reg;
+	unsigned int cfg;
+};
+
+struct dram_info {
+	int dram_type;
+	int current_fsp;
+	int boot_fsp;
+	struct dram_cfg_param *ddrc_cfg;
+	unsigned int ddrc_cfg_num;
+	struct dram_cfg_param *ddrphy_cfg;
+	unsigned int ddrphy_cfg_num;
+};
+
+/* lpddr4 ddrc and phy config info */
+extern struct dram_info imx8m_lpddr4_dram_info;
+
+void ddrphy_load_pie_image(void);
+void dram_info_init(void);
+void lpddr4_enter_retention(void);
+void lpddr4_exit_retention(void);
+void dram_umctl2_init(void);
+void dram_phy_init(void);
+void dram_enter_retention(void);
+void dram_exit_retention(void);
+
+#endif /* __DRAM_H__ */
diff --git a/plat/imx/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8mm/imx8mm_bl31_setup.c
index c6baf85..26f7e15 100644
--- a/plat/imx/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8mm/imx8mm_bl31_setup.c
@@ -12,6 +12,7 @@
 #include <context_mgmt.h>
 #include <debug.h>
 #include <stdbool.h>
+#include <dram.h>
 #include <mmio.h>
 #include <platform.h>
 #include <platform_def.h>
@@ -248,6 +249,9 @@
 	/* map GIC */
 	mmap_add_region(PLAT_GIC_BASE, PLAT_GIC_BASE, 0x100000,  MT_DEVICE | MT_RW);
 
+	/* Map DDRC/PHY/PERF */
+	mmap_add_region(0x3c000000, 0x3c000000, 0xC000000, MT_DEVICE | MT_RW);
+
 #if USE_COHERENT_MEM
 	mmap_add_region(BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_BASE,
 		BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE,
@@ -265,12 +269,16 @@
 	/* select the CKIL source to 32K OSC */
 	mmio_write_32(0x30360124, 0x1);
 
+	/* init the dram info */
+	dram_info_init();
+
 	/* init the GICv3 cpu and distributor interface */
 	plat_gic_driver_init();
 	plat_gic_init();
 
 	/* gpc init */
 	imx_gpc_init();
+
 }
 
 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
diff --git a/plat/imx/imx8mm/imx8mm_psci.c b/plat/imx/imx8mm/imx8mm_psci.c
index 001e0e0..893001c 100644
--- a/plat/imx/imx8mm/imx8mm_psci.c
+++ b/plat/imx/imx8mm/imx8mm_psci.c
@@ -8,6 +8,7 @@
 #include <arch_helpers.h>
 #include <debug.h>
 #include <stdbool.h>
+#include <dram.h>
 #include <plat_imx8.h>
 #include <psci.h>
 #include <mmio.h>
@@ -121,6 +122,7 @@
 
 	/* do system level power mode setting */
 	if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
+		dram_enter_retention();
 		imx_set_sys_lpm(true);
 		imx_anamix_pre_suspend();
 		noc_wrapper_pre_suspend(core_id);
@@ -142,6 +144,7 @@
 		imx_anamix_post_resume();
 		noc_wrapper_post_resume(core_id);
 		imx_clear_rbc_count();
+		dram_exit_retention();
 	}
 
 	/* check the cluster level power status */
diff --git a/plat/imx/imx8mm/include/ddrc.h b/plat/imx/imx8mm/include/ddrc.h
new file mode 100644
index 0000000..8eb42fd
--- /dev/null
+++ b/plat/imx/imx8mm/include/ddrc.h
@@ -0,0 +1,304 @@
+#ifndef __IMX_DDRC_H
+#define __IMX_DDRC_H
+
+#define DDRC_IPS_BASE_ADDR(X)	(0x3d400000 + (X * 0x2000000))
+#define DDRC_DDR_SS_GPR0        0x3d000000
+
+/* DWC ddr umctl2 REGs offset*/
+/**********************/
+#define DDRC_MSTR(X)             (DDRC_IPS_BASE_ADDR(X) + 0x00)
+#define DDRC_STAT(X)             (DDRC_IPS_BASE_ADDR(X) + 0x04)
+#define DDRC_MSTR1(X)            (DDRC_IPS_BASE_ADDR(X) + 0x08)
+#define DDRC_MRCTRL0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x10)
+#define DDRC_MRCTRL1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x14)
+#define DDRC_MRSTAT(X)           (DDRC_IPS_BASE_ADDR(X) + 0x18)
+#define DDRC_MRCTRL2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1c)
+#define DDRC_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x20)
+#define DDRC_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x24)
+#define DDRC_MSTR2(X)            (DDRC_IPS_BASE_ADDR(X) + 0x28)
+#define DDRC_PWRCTL(X)           (DDRC_IPS_BASE_ADDR(X) + 0x30)
+#define DDRC_PWRTMG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x34)
+#define DDRC_HWLPCTL(X)          (DDRC_IPS_BASE_ADDR(X) + 0x38)
+#define DDRC_HWFFCCTL(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3c)
+#define DDRC_HWFFCSTAT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x40)
+#define DDRC_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x50)
+#define DDRC_RFSHCTL1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x54)
+#define DDRC_RFSHCTL2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x58)
+#define DDRC_RFSHCTL3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x60)
+#define DDRC_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x64)
+#define DDRC_ECCCFG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x70)
+#define DDRC_ECCCFG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x74)
+#define DDRC_ECCSTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0x78)
+#define DDRC_ECCCLR(X)           (DDRC_IPS_BASE_ADDR(X) + 0x7c)
+#define DDRC_ECCERRCNT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x80)
+#define DDRC_ECCCADDR0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x84)
+#define DDRC_ECCCADDR1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x88)
+#define DDRC_ECCCSYN0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x8c)
+#define DDRC_ECCCSYN1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x90)
+#define DDRC_ECCCSYN2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x94)
+#define DDRC_ECCBITMASK0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x98)
+#define DDRC_ECCBITMASK1(X)      (DDRC_IPS_BASE_ADDR(X) + 0x9c)
+#define DDRC_ECCBITMASK2(X)      (DDRC_IPS_BASE_ADDR(X) + 0xa0)
+#define DDRC_ECCUADDR0(X)        (DDRC_IPS_BASE_ADDR(X) + 0xa4)
+#define DDRC_ECCUADDR1(X)        (DDRC_IPS_BASE_ADDR(X) + 0xa8)
+#define DDRC_ECCUSYN0(X)         (DDRC_IPS_BASE_ADDR(X) + 0xac)
+#define DDRC_ECCUSYN1(X)         (DDRC_IPS_BASE_ADDR(X) + 0xb0)
+#define DDRC_ECCUSYN2(X)         (DDRC_IPS_BASE_ADDR(X) + 0xb4)
+#define DDRC_ECCPOISONADDR0(X)   (DDRC_IPS_BASE_ADDR(X) + 0xb8)
+#define DDRC_ECCPOISONADDR1(X)   (DDRC_IPS_BASE_ADDR(X) + 0xbc)
+#define DDRC_CRCPARCTL0(X)       (DDRC_IPS_BASE_ADDR(X) + 0xc0)
+#define DDRC_CRCPARCTL1(X)       (DDRC_IPS_BASE_ADDR(X) + 0xc4)
+#define DDRC_CRCPARCTL2(X)       (DDRC_IPS_BASE_ADDR(X) + 0xc8)
+#define DDRC_CRCPARSTAT(X)       (DDRC_IPS_BASE_ADDR(X) + 0xcc)
+#define DDRC_INIT0(X)            (DDRC_IPS_BASE_ADDR(X) + 0xd0)
+#define DDRC_INIT1(X)            (DDRC_IPS_BASE_ADDR(X) + 0xd4)
+#define DDRC_INIT2(X)            (DDRC_IPS_BASE_ADDR(X) + 0xd8)
+#define DDRC_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0xdc)
+#define DDRC_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0xe0)
+#define DDRC_INIT5(X)            (DDRC_IPS_BASE_ADDR(X) + 0xe4)
+#define DDRC_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0xe8)
+#define DDRC_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0xec)
+#define DDRC_DIMMCTL(X)          (DDRC_IPS_BASE_ADDR(X) + 0xf0)
+#define DDRC_RANKCTL(X)          (DDRC_IPS_BASE_ADDR(X) + 0xf4)
+#define DDRC_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x100)
+#define DDRC_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x104)
+#define DDRC_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x108)
+#define DDRC_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x10c)
+#define DDRC_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x110)
+#define DDRC_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x114)
+#define DDRC_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x118)
+#define DDRC_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x11c)
+#define DDRC_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x120)
+#define DDRC_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x124)
+#define DDRC_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x128)
+#define DDRC_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x12c)
+#define DDRC_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x130)
+#define DDRC_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x134)
+#define DDRC_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x138)
+#define DDRC_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x13C)
+#define DDRC_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x140)
+#define DDRC_DRAMTMG17(X)        (DDRC_IPS_BASE_ADDR(X) + 0x144)
+
+#define DDRC_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x180)
+#define DDRC_ZQCTL1(X)           (DDRC_IPS_BASE_ADDR(X) + 0x184)
+#define DDRC_ZQCTL2(X)           (DDRC_IPS_BASE_ADDR(X) + 0x188)
+#define DDRC_ZQSTAT(X)           (DDRC_IPS_BASE_ADDR(X) + 0x18c)
+#define DDRC_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x190)
+#define DDRC_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x194)
+#define DDRC_DFILPCFG0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x198)
+#define DDRC_DFILPCFG1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x19c)
+#define DDRC_DFIUPD0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1a0)
+#define DDRC_DFIUPD1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1a4)
+#define DDRC_DFIUPD2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1a8)
+#define DDRC_DFIMISC(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1b0)
+#define DDRC_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1b4)
+#define DDRC_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1b8)
+#define DDRC_DFISTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1bc)
+
+#define DDRC_DBICTL(X)           (DDRC_IPS_BASE_ADDR(X) + 0x1c0)
+#define DDRC_DFIPHYMSTR(X)       (DDRC_IPS_BASE_ADDR(X) + 0x1c4)
+#define DDRC_TRAINCTL0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1d0)
+#define DDRC_TRAINCTL1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1d4)
+#define DDRC_TRAINCTL2(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1d8)
+#define DDRC_TRAINSTAT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1dc)
+#define DDRC_ADDRMAP0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x200)
+#define DDRC_ADDRMAP1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x204)
+#define DDRC_ADDRMAP2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x208)
+#define DDRC_ADDRMAP3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x20c)
+#define DDRC_ADDRMAP4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x210)
+#define DDRC_ADDRMAP5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x214)
+#define DDRC_ADDRMAP6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x218)
+#define DDRC_ADDRMAP7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x21c)
+#define DDRC_ADDRMAP8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x220)
+#define DDRC_ADDRMAP9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x224)
+#define DDRC_ADDRMAP10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x228)
+#define DDRC_ADDRMAP11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x22c)
+
+#define DDRC_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x240)
+#define DDRC_ODTMAP(X)           (DDRC_IPS_BASE_ADDR(X) + 0x244)
+#define DDRC_SCHED(X)            (DDRC_IPS_BASE_ADDR(X) + 0x250)
+#define DDRC_SCHED1(X)           (DDRC_IPS_BASE_ADDR(X) + 0x254)
+#define DDRC_PERFHPR1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x25c)
+#define DDRC_PERFLPR1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x264)
+#define DDRC_PERFWR1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x26c)
+#define DDRC_PERFVPR1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x274)
+
+#define DDRC_PERFVPW1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x278)
+
+#define DDRC_DQMAP0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x280)
+#define DDRC_DQMAP1(X)           (DDRC_IPS_BASE_ADDR(X) + 0x284)
+#define DDRC_DQMAP2(X)           (DDRC_IPS_BASE_ADDR(X) + 0x288)
+#define DDRC_DQMAP3(X)           (DDRC_IPS_BASE_ADDR(X) + 0x28c)
+#define DDRC_DQMAP4(X)           (DDRC_IPS_BASE_ADDR(X) + 0x290)
+#define DDRC_DQMAP5(X)           (DDRC_IPS_BASE_ADDR(X) + 0x294)
+#define DDRC_DBG0(X)             (DDRC_IPS_BASE_ADDR(X) + 0x300)
+#define DDRC_DBG1(X)             (DDRC_IPS_BASE_ADDR(X) + 0x304)
+#define DDRC_DBGCAM(X)           (DDRC_IPS_BASE_ADDR(X) + 0x308)
+#define DDRC_DBGCMD(X)           (DDRC_IPS_BASE_ADDR(X) + 0x30c)
+#define DDRC_DBGSTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0x310)
+
+#define DDRC_SWCTL(X)            (DDRC_IPS_BASE_ADDR(X) + 0x320)
+#define DDRC_SWSTAT(X)           (DDRC_IPS_BASE_ADDR(X) + 0x324)
+#define DDRC_OCPARCFG0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x330)
+#define DDRC_OCPARCFG1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x334)
+#define DDRC_OCPARCFG2(X)        (DDRC_IPS_BASE_ADDR(X) + 0x338)
+#define DDRC_OCPARCFG3(X)        (DDRC_IPS_BASE_ADDR(X) + 0x33c)
+#define DDRC_OCPARSTAT0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x340)
+#define DDRC_OCPARSTAT1(X)       (DDRC_IPS_BASE_ADDR(X) + 0x344)
+#define DDRC_OCPARWLOG0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x348)
+#define DDRC_OCPARWLOG1(X)       (DDRC_IPS_BASE_ADDR(X) + 0x34c)
+#define DDRC_OCPARWLOG2(X)       (DDRC_IPS_BASE_ADDR(X) + 0x350)
+#define DDRC_OCPARAWLOG0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x354)
+#define DDRC_OCPARAWLOG1(X)      (DDRC_IPS_BASE_ADDR(X) + 0x358)
+#define DDRC_OCPARRLOG0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x35c)
+#define DDRC_OCPARRLOG1(X)       (DDRC_IPS_BASE_ADDR(X) + 0x360)
+#define DDRC_OCPARARLOG0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x364)
+#define DDRC_OCPARARLOG1(X)      (DDRC_IPS_BASE_ADDR(X) + 0x368)
+#define DDRC_POISONCFG(X)        (DDRC_IPS_BASE_ADDR(X) + 0x36C)
+#define DDRC_POISONSTAT(X)       (DDRC_IPS_BASE_ADDR(X) + 0x370)
+#define DDRC_ADVECCINDEX(X)      (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ADVECCSTAT(X)       (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ECCPOISONPAT0(X)    (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ECCPOISONPAT1(X)    (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ECCPOISONPAT2(X)    (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_HIFCTL(X)           (DDRC_IPS_BASE_ADDR(X) + 0x3)
+
+#define DDRC_PSTAT(X)            (DDRC_IPS_BASE_ADDR(X) + 0x3fc)
+#define DDRC_PCCFG(X)            (DDRC_IPS_BASE_ADDR(X) + 0x400)
+#define DDRC_PCFGR_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x404)
+#define DDRC_PCFGR_1(X)          (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404)
+#define DDRC_PCFGR_2(X)          (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404)
+#define DDRC_PCFGR_3(X)          (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404)
+#define DDRC_PCFGW_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x408)
+#define DDRC_PCFGW_1(X)          (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408)
+#define DDRC_PCFGW_2(X)          (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408)
+#define DDRC_PCFGW_3(X)          (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408)
+#define DDRC_PCFGC_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x40c)
+#define DDRC_PCFGIDMASKCH(X)     (DDRC_IPS_BASE_ADDR(X) + 0x410)
+#define DDRC_PCFGIDVALUECH(X)    (DDRC_IPS_BASE_ADDR(X) + 0x414)
+#define DDRC_PCTRL_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490)
+#define DDRC_PCTRL_1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0)
+#define DDRC_PCTRL_2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0)
+#define DDRC_PCTRL_3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0)
+#define DDRC_PCFGQOS0_0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x494)
+#define DDRC_PCFGQOS1_0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x498)
+#define DDRC_PCFGWQOS0_0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x49c)
+#define DDRC_PCFGWQOS1_0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x4a0)
+#define DDRC_SARBASE0(X)         (DDRC_IPS_BASE_ADDR(X) + 0xf04)
+#define DDRC_SARSIZE0(X)         (DDRC_IPS_BASE_ADDR(X) + 0xf08)
+#define DDRC_SBRCTL(X)           (DDRC_IPS_BASE_ADDR(X) + 0xf24)
+#define DDRC_SBRSTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0xf28)
+#define DDRC_SBRWDATA0(X)        (DDRC_IPS_BASE_ADDR(X) + 0xf2c)
+#define DDRC_SBRWDATA1(X)        (DDRC_IPS_BASE_ADDR(X) + 0xf30)
+#define DDRC_PDCH(X)             (DDRC_IPS_BASE_ADDR(X) + 0xf34)
+
+/* SHADOW registers */
+#define DDRC_FREQ1_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2020)
+#define DDRC_FREQ1_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2024)
+#define DDRC_FREQ1_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2050)
+#define DDRC_FREQ1_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2064)
+#define DDRC_FREQ1_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20dc)
+#define DDRC_FREQ1_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20e0)
+#define DDRC_FREQ1_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20e8)
+#define DDRC_FREQ1_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20ec)
+#define DDRC_FREQ1_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2100)
+#define DDRC_FREQ1_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2104)
+#define DDRC_FREQ1_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2108)
+#define DDRC_FREQ1_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x210c)
+#define DDRC_FREQ1_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2110)
+#define DDRC_FREQ1_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2114)
+#define DDRC_FREQ1_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2118)
+#define DDRC_FREQ1_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x211c)
+#define DDRC_FREQ1_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2120)
+#define DDRC_FREQ1_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2124)
+#define DDRC_FREQ1_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2128)
+#define DDRC_FREQ1_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x212c)
+#define DDRC_FREQ1_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2130)
+#define DDRC_FREQ1_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2134)
+#define DDRC_FREQ1_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2138)
+#define DDRC_FREQ1_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x213C)
+#define DDRC_FREQ1_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2140)
+#define DDRC_FREQ1_DRAMTMG17(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2144)
+#define DDRC_FREQ1_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x2180)
+#define DDRC_FREQ1_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2190)
+#define DDRC_FREQ1_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2194)
+#define DDRC_FREQ1_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
+#define DDRC_FREQ1_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
+#define DDRC_FREQ1_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x2240)
+
+#define DDRC_FREQ2_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3020)
+#define DDRC_FREQ2_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3024)
+#define DDRC_FREQ2_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3050)
+#define DDRC_FREQ2_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x3064)
+#define DDRC_FREQ2_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30dc)
+#define DDRC_FREQ2_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30e0)
+#define DDRC_FREQ2_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30e8)
+#define DDRC_FREQ2_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30ec)
+#define DDRC_FREQ2_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3100)
+#define DDRC_FREQ2_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3104)
+#define DDRC_FREQ2_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3108)
+#define DDRC_FREQ2_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x310c)
+#define DDRC_FREQ2_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3110)
+#define DDRC_FREQ2_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3114)
+#define DDRC_FREQ2_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3118)
+#define DDRC_FREQ2_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x311c)
+#define DDRC_FREQ2_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3120)
+#define DDRC_FREQ2_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3124)
+#define DDRC_FREQ2_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3128)
+#define DDRC_FREQ2_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x312c)
+#define DDRC_FREQ2_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3130)
+#define DDRC_FREQ2_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3134)
+#define DDRC_FREQ2_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3138)
+#define DDRC_FREQ2_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x313C)
+#define DDRC_FREQ2_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3140)
+#define DDRC_FREQ2_DRAMTMG17(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3144)
+#define DDRC_FREQ2_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x3180)
+#define DDRC_FREQ2_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x3190)
+#define DDRC_FREQ2_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x3194)
+#define DDRC_FREQ2_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x31b4)
+#define DDRC_FREQ2_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x31b8)
+#define DDRC_FREQ2_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x3240)
+
+#define DDRC_FREQ3_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4020)
+#define DDRC_FREQ3_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4024)
+#define DDRC_FREQ3_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4050)
+#define DDRC_FREQ3_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x4064)
+#define DDRC_FREQ3_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40dc)
+#define DDRC_FREQ3_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40e0)
+#define DDRC_FREQ3_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40e8)
+#define DDRC_FREQ3_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40ec)
+#define DDRC_FREQ3_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4100)
+#define DDRC_FREQ3_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4104)
+#define DDRC_FREQ3_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4108)
+#define DDRC_FREQ3_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x410c)
+#define DDRC_FREQ3_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4110)
+#define DDRC_FREQ3_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4114)
+#define DDRC_FREQ3_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4118)
+#define DDRC_FREQ3_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x411c)
+#define DDRC_FREQ3_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4120)
+#define DDRC_FREQ3_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4124)
+#define DDRC_FREQ3_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4128)
+#define DDRC_FREQ3_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x412c)
+#define DDRC_FREQ3_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4130)
+#define DDRC_FREQ3_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4134)
+#define DDRC_FREQ3_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4138)
+#define DDRC_FREQ3_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x413C)
+#define DDRC_FREQ3_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4140)
+
+#define DDRC_FREQ3_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x4180)
+#define DDRC_FREQ3_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x4190)
+#define DDRC_FREQ3_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x4194)
+#define DDRC_FREQ3_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x41b4)
+#define DDRC_FREQ3_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x41b8)
+#define DDRC_FREQ3_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x4240)
+#define DDRC_DFITMG0_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2190)
+#define DDRC_DFITMG1_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2194)
+#define DDRC_DFITMG2_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
+#define DDRC_DFITMG3_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
+#define DDRC_ODTCFG_SHADOW(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2240)
+
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
+#define dwc_ddrphy_apb_rd(addr) mmio_read_32(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))
+#define dwc_ddrphy_apb_wr(addr, val) mmio_write_32(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), val)
+
+#endif /*__IMX_DDRC_H */
diff --git a/plat/imx/imx8mm/include/platform_def.h b/plat/imx/imx8mm/include/platform_def.h
index 74ddb59..cbf0d18 100644
--- a/plat/imx/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8mm/include/platform_def.h
@@ -63,6 +63,7 @@
 #define IMX_AIPS1_BASE			0x30200000
 #define IMX_AIPS4_BASE			0x32c00000
 #define IMX_ANAMIX_BASE			0x30360000
+#define IMX_CCM_BASE			0x30380000
 #define IMX_SRC_BASE			0x30390000
 #define IMX_GPC_BASE			0x303a0000
 #define IMX_RDC_BASE			0x303d0000
diff --git a/plat/imx/imx8mm/platform.mk b/plat/imx/imx8mm/platform.mk
index d40394d..570fa55 100644
--- a/plat/imx/imx8mm/platform.mk
+++ b/plat/imx/imx8mm/platform.mk
@@ -9,6 +9,10 @@
 				plat/common/plat_gicv3.c		\
 				plat/imx/common/plat_imx8_gic.c
 
+PLAT_DRAM_SOURCES	:=	plat/imx/common/imx8m/dram.c		\
+				plat/imx/common/imx8m/lpddr4_retention.c  \
+				plat/imx/common/imx8m/lpddr4_phy_pie.c
+
 BL31_SOURCES		+=	plat/imx/common/imx8_helpers.S		\
 				plat/imx/common/mxcuart_console.S	\
 				plat/imx/common/imx8_sip_svc.c		\
@@ -27,7 +31,7 @@
 				lib/cpus/aarch64/cortex_a53.S		\
 				drivers/console/aarch64/console.S	\
 				${PLAT_GIC_SOURCES}			\
-				${PLAT_DDR_SOURCES}			\
+				${PLAT_DRAM_SOURCES}			\
 				drivers/arm/tzc/tzc380.c
 
 ENABLE_PLAT_COMPAT	:=	0